JPS60134364A - Bus interface control system - Google Patents

Abstract

PURPOSE:To execute a bus interface control for improving a throughput of a common bus, by assigning together a time slot of a microprocessor and a time slot of an I/O adaptor. CONSTITUTION:Time slot signals A-D are always assigned to a microprocessor 1. As for an adaptor 4 and an adaptor 5, time slot signals A'-D' are assigned to one adaptor. The microprocessor 1, the adaptor 4 or the adaptor 5 regards the time slow signals A-D or A'-D' as one unit as a memory cycle, but as for an address bus 10 in a bus 6, A' and C, B' and D, C' and A, and D' and B are overlapped, respectively. Accordingly, as for an address, A-B or A'- B' are varied as one unit, and a data corresponding to it is offered to the microprocessor 1, the adaptor 4 or the adaptor 5, respectively, in a time slot period of D or D'.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a bus interface control method, and particularly to a bus interface control method for a microprocessor sensor system.

[Background of the invention]

Virtual memory methods have also been adopted in the field of microprocessors. To support virtual memory, an address translation mechanism is required to translate logical addresses to real addresses.

This address translation mechanism includes an address translation memory for storing a correspondence table between logical addresses and real addresses. Static memory, which has a fast access time, is usually used as this memory. However, compared to the conventional real storage system, an extra step is added to convert a logical address into a real address using an address translation mechanism. This overhead not only increases the microprocessor's instruction execution time, but also degrades the throughput of the bus shared by the microprocessor, main memory, and I10 adapter. Hereinafter, such a state will be specifically explained using the drawings.

FIG. 1 is a block diagram of a microprocessor system. The microprocessor 1 executes instructions and
The adapter 4 and adapter 5 are devices that control the entire system, and the main storage section 3 is a microprocessor 1. A storage device that is commonly accessed by the adapter 4 and the adapter 5, the main memory control unit 2 is a part that controls the main memory unit 3, and the bus 6 is a transfer path for addresses, data, etc. for accessing the main memory unit 3. .

A memory access request to the main memory section 3 is accepted and processed by the main memory control section 2, and its control method is usually a priority control method. That is, microprocessor 1. When there are access requests from two or more devices at the same time among the adapters 4 and 5, the J picture is serviced in series from the device with the highest priority according to a predetermined priority order. By the way, as one of the virtual memory support methods, there is a case where the main memory control unit 2 includes an address translation mechanism. That is, the device can access the main memory control section 2 using a logical address, and the main memory control section 2 converts this into a real address and accesses the main memory section 3 using the real address. Even in this case, if the conventional bus interface control method based on priority control is used, the memory access time (memory cycle) of the microprocessor 1 will be longer than before, and during this time, even if there is an access from the adapter 4 or the adapter 5, it will not be accepted. Because there is no
There is a problem with the DMA operation of these I10 adapters in that data transfer overruns or underruns are likely to occur. It is also clear that the total throughput of the bus 6 is reduced.

On the other hand, address translation? If you try to make it JIRA, you will have to use a cylinder-speed address conversion memory, which will lead to an expensive amplifier.

[Purpose of the invention]

An object of the present invention is to provide a bus interface control method that improves the throughput of a shared bus when memory cycles are relatively long.

[Summary of the invention]

The present invention assumes that the entire access operation to a storage device consists of at least two phases in which different processes are sequentially performed, and a plurality of time slots are allocated,
A time slot is always assigned to the microprocessor sensor, and a time slot is assigned to a selected one of the I10 adapters in parallel so that a phase different from that of the microprocessor is executed at the same time. [Embodiment of the Invention] An embodiment of the present invention will be described below with reference to FIG. m1. The overall system configuration is the same as the conventional one shown in FIG. FIG. 2 shows a more specific configuration of the bus 6 JiJJ side. Address information from the microprocessor 1 is transferred to the address bus 10 via a three-skate address buffer 12.
is output to.

This is taken into the address buffer 13 of the main memory control section 2 and used as the address of the address translation mechanism 18. The output of the address conversion mechanism 18 is the address launch 1
9 and is used as the address of the main storage unit 3. Note that when the device specifies a real address, this address is latched from the address buffer 13 to the interview address latch 19 via the selector 26. The data at the addressed location is outputted to the data bus 11 via the 3-state buffer 16. The microprocessor 1 receives this content via the data buffer 15 and completes a series of operations. In other words, the memory cycle from the device's perspective includes different phases of address conversion processing and memory access operation. These series of operation controls are carried out using time slots determined by the system. In this specific example, the time slots are as shown in FIG. 3. FIG. This is a timing chart showing the control method of the data bus 11 focusing on the microprocessor 1 and the adapter 4 or 5. The microprocessor 1 is always assigned time slot signals A to D. This time slot signal is The slots are divided based on the optimum values of the address determination time, address conversion time, and main memory access time based on the instruction fetch, data read, or data write cycle of the processor 1. In this embodiment, four slots are shown. However, it may be more or less than that.

For adapters 4 and 5, common time slot signals A' to D' are assigned to either adapter. Microprocessor 1. The adapter 4 or adapter 5 views the time slot signals A-D or A'-B' as one unit as a memory cycle, but
As shown in FIG. 3, address bus 10 within bus 6 has A' overlapping C and B', and C' and A1D' overlapping B. Therefore, the address changes A-B or A'-B' as one unit, and the corresponding data is transferred to the microprocessor 1 or the adapter 4 or the adapter 5 during the time slot period D or D.
provided respectively.

Address conversion and memory access are performed during the time period (DC) or +3'C' when the address is determined.

Returning to FIG. 2 again for further explanation, the three-state address buffer 712 is turned on during time slots A and B and outputs an address. During periods C and D, there are three states. It is also in good condition. When the adapter 4 wants to access the main memory section 3, it only has to output the address via the 3-state address buffer 17 during the AB period, and the rest is the same as the access from the processor 1 described above.

FIG. 4 shows the configuration of the time slot bus, and FIG. 5 shows its timing chart. In this example, the timing generation circuit shown in FIG. 5 or the time slot generation circuit 24 in the microprocessor 1 is used. This is then output by the time slot buffer 21,
Get on time slot bus 25. This content is received by the time slot buffers 722 and 23, and is controlled by each adapter and the main memory controller 2 according to the timing chart of FIG.

Note that common time slot signals 8' to D' are assigned to adapter 4 and adapter 5. Therefore, when there is memory access from both adapters at the same time, K is
Main memory: The Ul control unit 2 selects one of the adapters according to the priority control method and allocates time slots 413 A to 413) to that adapter.

Note that in the present invention, the main memory control unit 2
The present invention can be applied not only to the case of having a problem, but also to the case of performing other time-consuming processing (for example, processing under error "J", etc.).

〔Effect of the invention〕

According to the present invention, since the microprocessor time slot and the I10 adapter time slot are allocated in parallel, the throughput of the shared bus can be improved.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of the Micro 70 Cenoza system, Figure 2
The figure is a detailed diagram of the area around the bus, Figure 3 is a timing chart showing the skin condition of the time slot bus, Figure 4 is the (f7) diagram of the time slot bus, and Figure 5 is the Thai bus jinodohas W. This is Timenaya-I. - Micro 10 setter 2 main memory control i1 (3 main memory section 4.5, attack 6, bus 10, address bus 1, data bus 12, 3 state address node 7713, address buffer r 21, 22, 23... Time Slot No (Nofa 24・
・Time slot generation circuit 25...Time slot function Figure 4 1 Figure 1! 3rd class

Claims (1)

[Claims] 1. In a nox interface control method for controlling access to a shared storage device in which a microprocessor and an I10 adapter are connected via a common bus, the entire access operation to the storage device is handled differently. 11m, and a plurality of time slots are allocated to the microprocessor, and the time slot is allocated to the microprocessor at all times, and the time slot is allocated to a selected one of the I10 adapters. The bus interface control method 02 is characterized in that the microprocessor is controlled so that different phases are executed at the same time so that the time slots are allocated in parallel, one of the phases being a logical address. The method according to claim 1, characterized in that the address conversion process converts the address into a real address.