JPS61190603A - Multiprogrammable control device - Google Patents

Abstract

PURPOSE:To rationalize the capacity of a memory by providing the memory of a data link device with an address conversion mechanism for addressing of this memory. CONSTITUTION:A programmable controller (PC) 210 is constituted with an essential PC consisting of CPU211, a main memory 211A, an I/O 212, and a common bus 213, a bus interface 214, and the data link device consisting of a connecting circuit 215 and a link data storage part 218. This link data storage part 218 is provided with a memory 216 for buffer and an address conversion mechanism 217. The address conversion mechanism 217 performs the address conversion for correspondence between addresses on a bus 219 and addresses of the main memory 216. In this address conversion, a block to which a given input/output address belongs is discriminated, and an address of the main memory 216 to which this block corresponds is calculated.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention provides a programmable controller 7 (hereinafter referred to as a PC).
In particular, it relates to distributed multi-programmable control devices.

[Background of the invention]

Conventional distributed multi-PC C1cid, JP-A-58
There is No.-92006. Install multiple PCs, each PCK
H. Install data link equipment. These data link devices are interconnected via data link cables. Therefore, each data link device is connected not only to a corresponding PC but also to a data link cable.

Each data link device has a memory, and this memory contains
For its corresponding PC, it serves as a buffer for temporarily storing data. Corresponding P of memory a1 self
In addition to the area for storing input/output data captured in response to input/output equipment in C, an area for PCs other than the own is individually allocated.

Individually assign the next page to the area for PCs other than this one.
Stores input/output data from C in a PC-compatible manner. The input/output data stored in this area for PCs other than the own PC is data necessary for the own PC. That is, the PCs are installed in a distributed manner, and as a result, input/output control is performed between each PCH and the input/output devices independently connected to its own PC. However, there may be cases where data is required between input/output devices of other PCs. This is the so-called use of input/output data for other PCs on the own PC. Therefore, I tried to store the input/output data of other PCs in the memory of my own data link device and use it on my friend's PC.

According to this conventional device, a data link device is provided, a memory for a buffer is provided inside the device, input/output data from other PCs other than the own PC is stored in this memory, and the data link device for the buffer is stored in this memory. By freely accessing memory, the disadvantages of distributed installation can be uniquely solved.

However, there is a problem with the capacity of the buffer memory within the data link device.

First, memory capacity increases as the number of PCs increases. Second, by limiting the capacity that is provided individually for PCs, it is possible to prevent the capacity from increasing beyond a certain level, but originally the capacity required for a PC cannot be unambiguously determined. Therefore, it often has unnecessary capacity.

[Purpose of the invention]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a multi-programmable control device that allows optimization of memory capacity within a data link device.

[Summary of the invention]

In the present invention, an address conversion mechanism is provided next to the address specification of the memory of the data link device.

[Embodiments of the invention]

FIG. 1 is a diagram showing an embodiment of a multi-PC according to the present invention.

For convenience, the PCs 210, 220, . . . , 230 are shown to include the original PC and data link device in the conventional example. Each PC210, 220,...

230 has the same internal configuration. Each PC210°220
,...,230U data link cable 201
are mutually connected.

The explanation will be made using the PC 210 instead.

PC210 with CPU211 and main memory (MEM)2
11A, 110212, and a common bus 213, a bus interface (CBIP) 214, a data link device consisting of a coupling circuit (CE) 215, and a link data storage section 218.

The link data storage section 218i consists of a buffer memory 216 and an address conversion mechanism (AC) 217. AC217
First, I will explain the operation as a temporary one.

If the original PC function, CPU211 performs MEM2 according to the program stored in MEM211
Process the data in 11A and update l1021 as necessary.
Data is output to an external control system via 2, and data is input via 110212 if necessary. In addition, sequence control is performed from processing by the CPU 211.

The above are the original functions of a distributed PC. −
On the other hand, the MEM 216 of the data link device has a tPC compatible area that is determined to be compatible with other PCs, and the CPU 211 accesses the data in this area and uses it for its own sequence processing. Furthermore, it goes without saying that the MEM 216i has its own data buffer area for the PC.

Other PCs 220, 230 to MEM 216
Each PC 220, . . .

230 may be sent arbitrarily as necessary. In this case, for example, i, l1 on the PC 220
All or part of the data imported from 0222 to BIF2
24→CE225→Cable 201→CE215→ME
It may be stored via the M216, or the CPU 221 may make a certain judgment and send and store the result via the thread path, or it may be stored in the iMEM 211A and sent in the same way afterward. [Stored in MEM226, then CE2
It may also be sent via 25.

As another method, a transmission order may be determined for each i and pc, and the data may be sent according to that order. For example, PC210→P
The order of sending to the cable 201 is determined in the order of C220→...→PC230, and first, the PC210 sends its own I10 data to the cable 201 via the CF215. Other P C220゜..., 230, i, P
Select the data necessary for your PC from among the data sent from the C210 and send it to the internal MBM226.・・・・・・
It will be stored in.

When this process is completed, the PC 220 becomes the sender and sends the data to the cable 201 via the CE 225. Data tME necessary for other PC1, for example, PC210H1 itself
Store in M216. The same applies to the PC 230.

Thereafter, similar processing is performed for the PCs below PC 220, and the data of the frame and all PCs is stored in the MEM 216 for each corresponding area.

As above, the address translation mechanism 217t will be omitted and the following explanation will be given.

The address translation mechanism 217 performs address translation for associating the address on the path 219 with the address of the MEM 216. When the total address space of the MEM 216 is M1 and the total address space handled on the bus 219 is M2, it is assumed that M1<M2, particularly M1<<M2.

FIG. 2 is a correspondence table between the input/output addresses of Ilo and the addresses of MEM 216 for the memory 216 of the PC 210t-own PC. Now assume that the total number of PCs is set to 128. The input/output addresses for these 128 PCs are allocated as shown in the figure. That is, the entire address space of the input/output addresses of the device 10 is allocated to correspond to the PC. In the figure, addresses are allocated as follows.

Own PC...ooooo~0OF1'FPCI...0
1000~0IFFF PC2...02000~02FF'FPC3...0
3000~03FFF PC127...7F'OOO~7FFFF If the shaded area in this address is the area that is actually used, the self-P
For C, all of h, oooo to 0OFF are used, and for other PCs, a part of them is used as shown by diagonal lines. The shaded portions of PC2 to PCI27 are respectively referred to as blocks.

Each block contains consecutive addresses. Memory 216μ
Each block has an allocated area. The AC 217 associates addresses in the memory 216 with blocks and addresses within blocks. For example, if the data from PC2 is block B2, it is stored in block B2H memory 216 as block MB2.

The AC 217 performs the atto-VS correspondence between the block B2 and the block MB2.

In FIG. 2, the address area from OOOOO to 00FFF is a part that does not require address translation.

This reason for a1's own PC is i, oooooo ~ 001'
This is because the TCPU 211 can directly access the FF H1I 10212.

Next, the address translation method will be described.

For address conversion, it is determined which block a given input/output address belongs to, and the MEM 21 to which the block corresponds
This is done by calculating the address of 6.

For block determination, the first input/output address and the final input/output address of each block are registered and compared with these for determination. To calculate the address of the MEM 216 corresponding to the input/output address, if the first input/output address of the block is tA1 and the corresponding address of the MEM 216 is t-A2, for each block, register the value of A3 such that A3 = A2 - At. Then, for the input/output address A4 of the corresponding block,
By calculating λ3, the address corresponding to A4 of the MEM 216 is obtained.

Figure 8g3 shows the configuration of the address conversion table.

The table 104 contains the starting address BTAI of the frame block.

BTA2. BTA3. ...... is stored. B'r
A1 is the start address of the block with block number 1 (second
The first address of the block with BTA2rc block number 2 (the first address of iB3 in FIG. 2) is shown. Other instruction contents have similar roles.

Table 105 shows the final address BEAI of block a1.

BEA2. BEλ3. ...... is stored. BEA
l indicates the final address of block B2, BEA2i, the final address of block B3, etc.

Table 106 shows the addition values corresponding to each block a1 (A 3 shown in FIG. 2) BDATAI, BDATA2.
... is stored. Note that the numbers at the left end of FIG. 3 are block corresponding numbers. Therefore, when a block number is designated, the corresponding number (address) can be accessed immediately. In the following, for simplicity, the block numbers are 0.1.2...
It shall be possible to specify as follows.

FIG. 4 is a flowchart of address conversion. It is not as shown in Figure @4 because it is parallel processing to the operation of the actual address converter, but! Figure 4 shows the concept of the frame. When the input/output address is given in 501, the block number is set to O in 502.
Then, in 503, the block number and block number are checked, and if the block number is less than the block number, in 504, the values 104 and 105 accessed by the block number, that is, 2 of the first input/output address and the last input/output address of the block. Compare the given input/output addresses for each one, and if it is greater than or equal to the first input/output address of the block and less than or equal to the last input/output address, it is within the range of that block, so 505 is the value of 106 accessed by the block number. is added to the given input/output address to calculate the MEM address corresponding to the given friend output address, and the MEM address calculated in step 506 is used to access the MEM. If it is outside the range in step 504, the index is updated in step H1507, and the process is repeated from step 503 for the next block. If the block number is greater than or equal to the block number in step 503, there is no block corresponding to the given friend output address, so in step 508, an at-V error is determined. The above is the flow of address conversion.

Figure 8@5 is a block diagram of an address converter.

219 is a bus, 217 is an AC, and 216 is an MEM.

l0LH A register (
L7V'rCH), a counter (COUNT) giving the 102 block number, a source of the clock signal CLK given to the 112i counter 102, 107#-! In the AND gate between the clock generation source 112 and the counter 102, when the output of the NOR gate 113 is '1'', the signal of the clock source 112 is transmitted to the counter 102, and when the output of the NOR gate 113 is 10'', the signal of the clock source 112 is transmitted to the counter 102. counter 10
2, and the counter 102 no longer counts up. 108 is a block number upper limit comparator (GEICO
M), if the input from the counter 102 is greater than or equal to the input from the limit value setting register 103 (L, IME, EG), the output is t t 7a't'', representing an atto V error. 109μ, lower limit comparator So, register 104
(TOP ADDRREG) (starting input/output address of block) and input from latch register 101 (
If the latter is greater than or equal to the former, the output is a ``1'', and if the latter is less than the former, the output is 101. Register 105 (END
ADDR.

Compare the input from register 101 (final input/output address of the block) and the input from register 101, and if the latter is less than the former, output ``1'', and if the latter exceeds the former, output ``O''. Become. AND gate 114 is a range determiner,
If the input from the comparator 109 (GE CMP) and the input from the comparator (LE CMP) L10 are both @l'', the output 118 becomes @1'', indicating that address conversion has been completed. Otherwise, output 118 is 'O#. It is input from NOR gate 113112, outputs 117 and 118, and if either one is @1", the output is @0
”, and if both are IO”, the output will be “1”. The output 10” of the NOR gate 113 indicates that the address is being converted,
"1" indicates the end of address translation (including atto V error)
represents. This is the time required to compare one block in the period of the clock 112, and after determining the range of one block, the block number B! at the counter 102 is calculated. This is the period for updating. 111 is an adder (ADD) and a register (ADD
By adding the input from ATA BEG) 106 (conversion addition data) and the input from adder 101, M
The address of EM216 is sent to output 115. Output 118 is @
1”, the value of output 115 is valid, and output 1
18 is "0", the value of the output 115 is invalid.According to the signals 117 and 118 in the control circuit (CTRL) 116,
It controls the control signal to MEM216.

〔Effect of the invention〕

According to the present invention, since address conversion of input/output addresses can be performed in the link data storage section, data from widely distributed input/output devices can be efficiently stored in the link data storage section, that is, memory can be saved. Further, since there is no need for the main processing unit to perform address conversion processing, it can operate at high speed and simply. Friend, since input/output addresses can be centrally assigned to the input/output devices of other PCs and a wide space can be freely used, program creation and maintenance are easy.

[Brief explanation of drawings]

Figure 1a is an embodiment of the present invention, Figure 2 is an explanatory diagram of address conversion, Figure 3 is a diagram showing an address conversion table, Figure 4 is a processing flow diagram of address conversion, and Figure 5 is an illustration of the address conversion process. It is an example figure of a conversion mechanism. 201...Linkage cable (transmission line), 210
゜220.230...Program pull controller,
217.227...Ato Vs conversion mechanism, 216°22
6...Buffer memory.

Claims (1)

[Claims] 1. A programmable controller consisting of a plurality of programmable controllers and a linkage transmission line interconnecting the plurality of programmable controllers, each programmable controller consisting of a CPU, main memory, and I/O. It includes a main body and a buffer memory that captures and stores input/output data from other programmable controllers via a linkage transmission line, and also communicates the address of the buffer memory with the own programmable controller's main body and via the linkage transmission line. A multi-programmable control device in which an address conversion mechanism for associating the address with the buffer memory of each programmable controller is provided.