JPS6278668A - Shared memory device - Google Patents

Abstract

PURPOSE:To shorten the standby time in competition and to reduce the probability that competition may occur by installing a temporary memory circuit on the bus of a processor with data bit length different from the bit length of common data and limiting an access to the common data of one word to one. CONSTITUTION:Since the bit length of the common data is 16 bit and the data bit length of the processor 6b is eight bits, the common data of 16 bits is split into high order eight bits and low order eight bits, and the access is made from the high order first. Accordingly, at the time of writing the common data of 16 bits is read out of a shared memory 5 when the high eight bits are read and accessed, and stored in temporary memory elements 23d and 23e. For writing, right after the low order eight bits are stored in a temporary memory element 22e, the common data of 16 bits is written in the memory 5 from the elements 22d and 22e. Thus the common data is read and written by 16 bits without fail, and one word can be accessed once.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a shared memory device accessed by a plurality of processors having different data bit lengths.

In particular, the present invention relates to a shared memory device suitable when each processor is required to perform high-speed processing.

[Background of the invention]

As shown in FIG. 7, a conventional shared memory device 1 of this type includes a shared memory 5, a shared memory control circuit 2 for determining shared memory access requests from each processor 6a and 6b, and each processor 6a.

Gates 21a, 2lb, 22a control the connection between the buses 8a, 8b of 6b and the shared memory bus 9.
.

22b, 22c, 23a, 23b, 23c and the gates 21a, 21b, 22a, 22b, 22C.

Bus control circuit 3 that controls 23a, 23b, and 23c
It consists of Note that 7m and 7b are main memories.

The operation of the shared memory device 1 as described above is of the fifth order.

The shared memory control circuit 2 detects access requests from each of the processors 6a and 6b, and the circuit 2 determines which request is to be granted, and the access request is sent to the bus 8a of the granted processor 6a or 6b. Alternatively, it instructs the bus control circuit 3 to connect the bus 8b and the shared memory bus 9, and outputs permission to access the common memory to the processor 6a or 6b that has granted the permission. After that, the processor 6a or 6b that received the access permission and the shared memory 5
Data is transferred between the two.

Here, the processors 6a or 6b having data bit lengths different from the bit length of the common data (for example, 8 bits and 16 bits) need to access the shared memory at least twice in order to match the data bit lengths.
Until this access is completed, requests from the other processor 6b or 6a cannot be accepted. For this reason.

As shown in FIG. 2, the access is detected within the shared memory control circuit 2, and acceptance of access requests from the other processor 6b or 6a is prohibited. For accessing the above two or more times.

In the core processor 6a or 6b, since the processing is performed by software, it takes several μs+several μs, and during this time the other processor 6b or 6a has to wait, reducing the processing efficiency of the processor 6b or 6a. The disadvantage is that the single-line method cannot be applied when high-speed processing is required.

Regarding this type of device, the Special Publication No. 58-
No. 36381 is mentioned, but it is concerned only with a shared memory control unit, and does not consider access from two processors having different data bit lengths.

[Purpose of the invention]

An object of the present invention is to access data from two processors having different data bit lengths.

Provided is a shared memory device that enables each processor to perform high-speed processing by ensuring that each processor accesses one word of common data only once, reducing waiting time during contention and reducing the probability of contention occurring. It's about doing.

[Summary of the invention]

In order to achieve the above object, the present invention provides a shared memory that is accessed by two processors that have different data bit lengths and handles common data using the data bit length of either processor, and a shared memory access request from each processor. In a shared memory device comprising a shared memory control circuit that determines a shared memory control circuit, and a bus control circuit that controls connection between a bus of each processor and the shared memory bus, the processor has a data bit length different from the bit length of the common data. In addition to providing a temporary memory circuit on the bus.

The present invention is characterized in that a temporary storage control circuit is provided for controlling common data between the storage circuit and the shared memory so that common data can be accessed at one time.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

To simplify the explanation, a case will be described in which one is a 16-bit processor, the other is an 8-bit processor, and the bit length of the common data is 16 bits.

FIG. 1 is a block diagram showing an embodiment of the present invention.

The embodiment shown in FIG. 1 differs from the shared memory device shown in FIG. 7 in that the address bus 8b-1 of the processor 6b has a data bit length different from the common data bit length.
，! : To data bus 8b-2.

Temporary memory circuits 21c, 22d, 22e, 23d.

23e and the temporary storage circuit 21c*22
dr22e, 23d, 23eO gates 2lb, 22b that control the storage timing and the output signals of the temporary storage circuits 2IC, 22d, 22e, 23d, 2313;

Temporary storage control circuit 4 that controls 22c, 23b, 23c
1. The detailed circuit configuration will be explained with reference to FIG.

one! f, the read operation of the 16-bit processor 6a is
This will be explained with reference to the figures.

The shared memory control circuit 2 detects an access request from the addresses A6s to Ame output from the processor 6a and the data transfer request signal 8TB-a, and if there is no access request from the other processor 6b, the gate 13a , through the D-FF14a, the request acceptance signal ACK is received.
-a is output to the bus control circuit 3. In the bus control circuit 3, the address bus gate 21afc is opened in response to the request acceptance signal 1ycK-a, and read signals R, D are sent to the shared memory 5 from the request acceptance signal ACK-a and the read/write signal 几/W-a.
-a and opens the data bus gate 23a. Thereafter, the access permission signal RDY-a is output from the on-delay timer 17a in the shared memory control circuit 2 after the shared memory 5 access time. The processor 6a receives this access enable signal RDY-a and reads data from the shared memory 5.

Furthermore, the write operation of the 16-bit processor 6a is the same as the read operation described above until the bus control circuit 3 receives the request acceptance signal ACK-8 and opens the address bus gate 21a (see FIG. 5).

After this, the request acceptance signal ACK-a and the read/write signal R
/W-a opens the data bus gate 22a and outputs access permission signals R, DY-a from the on-delay timer 17a.
At the time when the processor 6a is output, the data from the processor 6a is stored in the shared memory 5.

An access request from the processor 6a is sent to the processor 6a.
It is released by resetting the data transfer request signal STBa from .

Next, the operation of the 8-bit processor 6b will be explained. Since the bit length of the common data is 16 bits, and the data bit distribution of the processor 6b is 8 bits, the 16-bit common data is divided into the th-order 8 bits and the lower 8 bits, and is always accessed from the higher order. Therefore, when reading, the shared memory 5 is accessed when reading the upper 8 bits.
The common data of 16 bits is read out and stored in the temporary storage elements 23d and 23e, and when writing, immediately after storing the lower 8 bits in the temporary storage element 22e, the data is stored in the temporary storage element 22 (1, 2211) in the shared memory 5. !Write 16-bit common data. In this way.

Reading and writing of common data is always done in units of 16 bits, and one word is always accessed once.

Hereinafter, the above operation will be explained in detail starting from the read operation without referring to FIG.

In the shared memory control circuit 2, the gate 31a outputs the common data from the address AHh-A++b output from the processor 6b, the data transfer request signal 5TB-b, the read/write signal R/W-b, and the lowest bit kob of the address bus. If a read request for the upper 8 bits is detected and there is no access request from the other processor 6a, the gate 13
b, request acceptance signal ACK-b through D-FF14b
is output to the bus control circuit 3. In the bus control circuit 3, the address bus game is executed by the request acceptance signal ACK-b) 2
l b'i is opened and a read signal D-b is output to the shared memory 5 in response to the request acceptance signal ACK-b and the read/write signal R/W-b. After this, the access permission signal FLDY is sent from the on-delay timer 17b in the shared memory control circuit 2.
-b is output after the access time of the shared memory 5, and at the time of this output, the temporary storage circuit 23d.

23a stores read data from the shared memory 5. At this time, the output gate 23b of the temporary storage circuit 23d is already opened in response to a read request for the upper 8 bits, and the upper 8 bits of the common data are placed on the data bus 8b-2 of the processor 6b.

For subsequent read requests for the lower 8 bits.

Detected by the gate 31b, the output gate 23c of the temporary storage circuit 23e opens in response to a read request for the lower 8 bits, and the lower 8 bits of the common data of the data buses 8b-21C of the processor 6b are turned on.

In the write operation, as shown in FIG. 6, the gate 31C detects a write request for the upper 8 bits of the shared data, outputs a latch signal to the temporary storage circuit 22d, and stores the write data from the processor 6b. do. A subsequent write request for the lower 8 bits is detected by the gate 31d, and a latch signal is output to the temporary storage circuit 22e to generate write data from the processor 6b. Then, with the data transfer request signal 8TB-b at the time of write access of the lower 8 bits, the shared memory access data v x
WOD -F
.

The access request signal FLEQb-2 is output to the line 2. The shared memory control circuit 2 confirms that there is no access request from the other processor 6a.

A request acceptance signal ACK-b is output to the bus control circuit 3.

In the bus control circuit 3, the address bus gate 21b is opened and the data bus gate 22b is passed through the gate 25b.
, open 22C. Thereafter, the on-delay timer 17b operates the one-shot multi 29 through the gate 28 after the shared memory 5 access time. The output from the one-shot multi 29 is the write signal W of the shared memory 5.
R-b, ensuring the pulse width necessary for the write signal. At the fall of the write signal W1%-b, the access request signals R, EQ-2 and the temporary storage circuit 21C are unlatched.

Note that the gates 15 and 16 in the shared memory control circuit 2 perform priority determination when access requests to the shared memory conflict. In this example, the 16-bit processor 6a side is given priority 1.
I am...

As described above, in the shared memory device 1 according to the present invention, one word of common data from each processor can always be accessed once, so the waiting time in the case of conflicting access requests is limited to at most Within the access time.

Specific effects of this example! In ~, the waiting time in the case of conflicting access requests is from several 88 to several μ in the conventional method.
s, whereas in this embodiment.

It can be set to 1 μS or less. In addition, the number of times that contention can occur is 1 when reading the upper 8 bits in an 8-bit processor, compared to 4 times in the conventional case, when reading the common data 1 WF4 at a time. Similarly, in the case of a 16-bit processor, the number of times is 2 compared to the conventional 4 times.

In this way, in this embodiment, the waiting time during contention can be reduced and the probability of contention occurring can be reduced to less than half.

〔Effect of the invention〕

As described above, according to the present invention, data is accessed by two processors with different data bit lengths, and one word of common data can always be accessed once from each processor, so the waiting time during contention is significantly reduced. By shortening the term, the probability of conflict occurring can also be reduced to less than half.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a shared memory device according to the present invention, FIG. 2 is a circuit diagram showing a specific circuit configuration of an embodiment of the present invention, and FIG. 3 is a block diagram showing a specific circuit configuration of an embodiment of the present invention. Figure 4 is a time chart for write access of a 16-bit processor, Figure 5 is a time chart for read access of an 8-bit processor, Figure 6 is a time chart for write access of an 8-bit processor, and Figure 7 is a conventional time chart. FIG. 8 is a block diagram showing a shared memory device according to the present invention, and FIG. 8 is a time chart at the time of γ access of the conventional shared memory device. 1... Shared memory device, 2... Shared memory control circuit. 3... Bus control circuit, 4... Temporary memory control circuit, 5
... shared memory, 6... processor, 7... memory, 8... bus, 9... shared memory bus.

Claims (1)

[Claims] 1. A shared memory that is accessed by two processors with different data bit lengths and which handles common data using the data bit length of either processor, and a shared memory control circuit that determines shared memory access requests from each processor. , a shared memory device comprising a bus control circuit for controlling connection between a bus of each processor and a shared memory bus, wherein a temporary storage circuit is provided on the bus of the processor having a data bit length different from the data bit length; Common data is shared between the storage circuit and the shared memory.
1. A shared memory device characterized by being provided with a temporary storage control circuit for controlling access at any time.