JPH01118941A - Memory access control system - Google Patents

Abstract

PURPOSE:To shorten the waiting time of a CPU by reading successively data out of a latch holding the data on a memory map when the coincidence is obtained between the preceding address and the present address of the CPU in case data are successively read out of the memory maps in the same address respectively. CONSTITUTION:When the requests are received from a CPU and the devices using memories for read-out of the data on memory maps 111-11n, the present address is compared with the preceding address held by an address latch 14 by a comparator 15. Then the data on the maps 111-11n held by latches 121-12n are read out only when the coincidence is obtained between both addresses. Each of the maps 111-11n is selected by a multiplexer 13. Therefore the time required to hold the data on the maps 111-11n by the latches 121-12n, i.e., the memory reading time can be omitted since the data held by the latches 121-12n are read in case the data on the maps 111-11n are read out in the same address. As a result, the waiting time of the CPU is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Purpose of the Invention (Field of Industrial Application) The present invention relates to a memory access control system suitable for use in a display type memory.

(Prior Art) In recent years, with the development of man-machine interfaces, increasingly sophisticated functions have been required of display devices, which are the core of such interfaces. Typical examples include multi-color display and multi-window display. To realize these advanced functions, Bi, Toma, 7@
Control technology is essential, and a memory plane with pit mag memory as a plane structure is used. This bi, Toma,
When reading data from multiple memory maps located at the same address in the f-memory plane, the control circuit must be configured as shown in Figure 2.

In the figure, reference numeral 21 indicates a memory map, and by setting and tossing a value to a register (not shown) for selecting this, the corresponding one is selected by the multiplexer 22, and the latch 23
is supplied to

(Interlayer Points to be Solved by the Invention) That is, when reading the value of each memory map at a predetermined address, if there are N memory maps, N memory read operations are required. Therefore,
The read time increases in proportion to the number of memory maps and the number of memory map accesses, and the CPU wait time increases.Next.

The present invention was made in view of the above-mentioned drawbacks, and is a nine-memory access control method that reduces CPU waiting time by adding a small amount of hardware, improves drawing speed when used in a display system, and improves drawing speed. The purpose is to provide

[Structure of the invention (elaborative means for solving the problem) In the logic circuit of the display system, its resolution and display function (
One drawback to improving the performance of a computer (character count, one color tone, etc.) is the speed of the nine CPUs for reading memory as described above. One way to improve this speed is to reduce the number of memory map reads. To this end, the present invention includes a memory access control circuit including a plurality of memory maps, respective latches for holding output data for each memory map, and flag information indicating whether or not the held addresses and data are valid. A latch that was issued earlier and holds the 9th address, a comparator that compares the 9th address held in this latch and the address to be accessed currently, and a t-byte readout of data from multiple memory maps located at the same address. If the output is output, it will follow the output of the converter/9 controller.

This circuit consists of circuit means that sequentially obtains outputs from the channels.

(Operation) In the above configuration, when data is sequentially read from a plurality of memory maps located at the same address, the current address and the previous address of the CPU are compared in the comparator. This matches. Data is sequentially read out from the latches in which the data in memory master 7'' is held.This causes the data to be cleared from the memory map.

This can reduce the amount of time it takes to store data on-chip. Therefore, if this is adopted in a display system, the waiting time of the CPU will be reduced and the drawing speed will be improved as a result.

(Examples) Hereinafter, examples of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic diagram showing an embodiment of the present invention. In the figure, 111-=11n is a memory map in which display data is stored, and is composed of a plurality of planes. 12.
12n are latches, and each memory map 11. ~11
The data obtained from each is retained. 13 is a multiplexer (MUX), and each of the latches 12. ~1
Obtain the 2n output as input information, select the necessary data, and press C.
Supplies data to PU and other devices that use memory. 14
is an address latch. The address latch 14 holds the memory address of the data held in the memory masters 7''11. to 11n, and its output is
Supply to 5. Comparator 15 is Addressra, Chi 13
The current address information is compared with the previous address information held in the memory, and memory access is controlled according to the result.

Examples of the present invention will be described in detail below.

Memory map 111-11 from CPU and other memory using devices
When a request to read data n is issued, the memory map 11,
9 data stored in latches 121 to 12n are held in latches 121 to 12n, and the address at that time is held in address latch 14. Subsequently, when a request to read data from memory my 7aZ J 1 to 11n is issued from the CPU or other memory using device, the address and address latch 14 are first read.
A comparator 15 compares the addresses held in the . Only if there is a match, the latch 12.
Memory map 11.~12n. ~11n data f: Read each memory memory, f11. ~11
The selection of n is made by multiplexer 13. Therefore, at the same address, memory map 11. When reading data from latches 12 to 11Q, latch 12. Since the data held in memory map 11. ~1
Use the 1n data.

Ch12. ~12n, that is, the memory read time is omitted.

An enable pit is assigned to the address latch 14, and is held in the address latch 14 to store address information and the latch 11. This is cleared in the initial state to fully indicate that the data of ~11n is valid. Memory map 11. Write cycle of CPU and other memory using devices. ~1
Address of data written to 1n and address latch 14
If the address held in 9 matches, clear the enable pit or latch the same data as memory 1
2. It is also necessary to write to ~12. address latch 1
If the enable bit 4 is cleared and the read request is issued next and the addresses match in the comparator 15, the data held in the latches 121 to 12n will not be read out, but the data will be read from the memory map 11 to 12n. , latch 12. ~1 n 12 again and enable the command.

[Effects of the Invention] When data sounds are sequentially read from each memory mug at the same address, this action is performed M times.

If the number of data is N, the number of times the memory map is read is only - degrees each time, so the time saved is as follows.

MX (N-1) X (Memory master, 7° lead time)
Therefore, according to the present invention, in the display system logic circuit, the CPU
Waiting time is reduced, resulting in faster drawing speed.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing a conventional example. 11-1...Memory map, 12. ~12n...
・Latch, 13...Multiplexer, 14...Addresser. f, 15... Comparator. Applicant's representative Patent attorney Takehiko Suzue

Claims (1)

[Claims] Includes multiple memory maps, respective latches that hold output data for each memory map, and flag information indicating whether or not the held address and data are valid, including the address previously issued by the CPU. An address latch that holds the address latch, a comparator that compares the output of this address latch with the address information to be currently accessed, and when sequentially reading data from multiple memory maps located at the same address, the above comparator output is applicable. A memory access control method characterized by obtaining outputs sequentially from latches.