JPS62113257A - Data transfer circuit - Google Patents

Abstract

PURPOSE:To realize not only data transfer, but also an additional function for arithmetic operation and processing by providing a dedicated processor which performs multiple control over data transfer between an input/output control part and a memory, a memory and a memory, and an input/output control part and an input/output control part and has an arithmetic and processing function for data. CONSTITUTION:The DMA control circuit of each input/output control part is omitted, and the processor MVP exclusive to fast data transfer is introduced to perform centralized control over data transfer requests of many channels and also provide the arithmetic and processing function for data. A fast program transfer system is employed without employing any DMA system to reduce circuits and also improve the use efficiency of a bus, and a dual port memory DPM which can be accessed from a main processor at any time and a control signal interface are prepared as a command parameter transfer system for the main processor MPU. Further, two systems of bus control circuits BUSC are provided to calculate and process data efficiently. Consequently, additional function for the arithmetic processing of data and data transfer among plural paths are easily realized.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a data transfer method for an information processing device.

[Conventional technology]

The information processing device needs to frequently transfer various data between its internal components. A conventional column is shown in FIG. @Figure 4 shows the main processor M P on one system.
U, main memory MM, various input/output control units IO
U, ~l0Un are connected.

Various operations are performed under the control of the MPU. in general,
Data transfer between the input and output devices uses a DMA (direct memory access) method to significantly reduce the processing overhead of the MPU and to be able to keep up with high-speed input and output devices. Here - via the IOU from the input/output device l101, for example.

When transferring data to MM, input/output control circuit l0C
1 receives one transfer unit (normally byte or 2-byte data determined by the width of the data bus), the DMA III leg circuit DMC is activated and generates a DMA request DRQ1,
The MPU's arbiter ARB performs bus arbitration and priority control, and when the system bus becomes available, the DMA DAC returns 1, the IOU DMA cycle is executed, and data is transferred from l0U1 to MM. .If the transfer direction is from MM to l0Ul, it is also from l0Ct to D.
The MC is activated, bus arbitration is performed in the same manner as above, and the DMC outputs the MM address and various timing signals.

The data read from MM is received by l0UI and output to l101. Father, if you need data transfer between memories, M
The DMC within the PU is activated and data transfer within the MM is executed. In this case, the system bus transfer cycle is MM
Two cycles of read 2 and MM write are required.

[Problem that the invention seeks to solve]

What are the disadvantages of this method?

(2) A DMA control circuit is required for each input/output control section, which increases the amount of hardware including the arbitration circuit, resulting in high cost.

■ As the number of DMA channels increases, bus arbitration
The main circuit becomes complicated and expensive.

■ Previously, DMA L8I was dedicated as a DMA control circuit.
However, this LSI usually only has a control function for 2 to 4 channels, and is not used for multi-channel DMA.
If this is required, multi-stage connection of DMA LSIs is required.

As the circuit becomes more complex, the speed decreases.

■ Image processing 1 When applying to image processing.

Data calculations and processing may be required during memory-to-memory transfer, and conventional data transfer circuits can only perform simple data transfers and cannot provide additional functions such as calculation processing.

[Means for solving problems]

In order to solve the problems of the prior art and realize an economical data transfer method, the following measures have been taken.

■Delete the DMA control circuit of each input/output control section.

■ Introducing a processor dedicated to high-speed data transfer.

It centrally controls data transfer requests for multiple channels and provides data calculation and processing functions.

■ Use a high-speed program transfer method instead of the DMA method to reduce circuitry and improve bus usage efficiency.

■ A device that can be accessed at all times from the main processor as a method for passing command parameters to and from the main processor.
Prepare Alport memory and control signal interface.

■ Equipped with two bus control circuits to efficiently execute data calculations and processing.

〔Example〕

Next (C Figures 1 to J and f for an embodiment of the present invention)
This will be explained with reference to Table 41.

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram showing the MVP in FIG. 1, and FIG. 3 is a flow diagram showing the PU in FIG. 2. The embodiment shown in FIG.
It has a 2-bus structure.

The transfer processor MVP has a dedicated command interface 1 between it and the main processor MPU, and exchanges commands and result parameters.

On the A bus, there is a memo IJA (AM) and various input/output control units AIO*, AIO2-AIOn.

Similarly, on the B bus, there are a memory B (BM) and various input/output control units BIO1, BIO,..., BIOn.
The MVP accepts the transfer request 2 from each of these input/output control units, drives the A bus or the B bus, and performs data transfer according to the operation mode defined by the command given by MPUK.

2 in FIG. 2, PU is a high-speed microprogram processor, and together with read-only memory ROM and work memory I (AM) that store microprograms corresponding to each operation mode, manages data transfer control. mP-IF is This is an interface circuit with the main processor, and writes commands and receives result parameters via the dealboard memory DPM.
control circuit, and receives address information AB from the MPU.

The OMPC and DPM, which control the DPM 2 and generate the data transfer end interrupt signal INT in response to the control signal C0NT, are dedicated interfaces that can be accessed at all times from the MPU, thereby increasing the speed of multi-channel control. P
U is connected to M by the dealboard memory control circuit DPMC.
Adds commands and parameters given by the PU, and writes result parameters at the end of command operation. The data transfer requests REQ, -REQn are received by the transfer request reception circuit REQC, and the priority circuit REQ of each request is
A specific RBQ is selected by P and notified to the PU. REQ
Although P is a fixed priority circuit in this embodiment, it may optionally be a one-rotation priority circuit. BU8C is A-BU
D, B-BUS address signal (A), data signal (D
), this is a circuit that generates and outputs a control signal (C).

A-BUS or B depending on the operation mode according to the instructions from the PU
- Drive BUS or A-BUSg and B-BUS simultaneously.

As an example of the operation mode table shown in Table 1, the case of mode number 2 will be explained. In the operation mode rA-A-OJ, as shown in the operation details, in the case of a single bus, the source address position (SCA) of the 6tl-Bus, the c data are etched 7 times, the specified operation (OPB) is executed, and the destination data is This means writing to the address (DTA). BOA
, OPR, and DTA are given from the MPU to the DPM as parameters attached to the command. This data transfer requires three cycles. This transfer is different from the conventional DM method in that an Ilo or memory address is generated by MVP and the program is transferred. next,
As an example of 2-bus operation, the case of mode number 11 will be explained. rAB-A-OJ fetches data from the source address SCA of the A bus and the source address SCB of the B bus, and uses the contents of SCA (SCA) and S
The contents of OB (SCB) are calculated and the result is written to the address indicated by DTA on the A bus indicated by DTA. In this case, since 80A and 8CB are on different buses, they can be accessed at the same time. Therefore, 1 transfer is SC, ~/8
CU-01) In the case of rAA-B-OJ, which is executed in 3 cycles of R-DT A and has mode number 10.

This is a mode in which data is fetched from sources 5CAI and 5CA2 from the A bus, calculated, and written to the DTB address on the B bus.Since the A bus is empty at 2 in the DTB cycle, the next data 8C'At cycle is executed at the same time. No way. Therefore, the second data transfer cycle and subsequent cycles are executed in three cycles to improve transfer efficiency.

FIG. 3 shows 70 states of state control controlled by the PU. First, when initialization is instructed from the MPU, the MV
P clears the microgram counter, performs initial diagnosis of the internal circuit, and if normal, returns to "command state"
to go into. In the command state, check the DPM command area.

Check whether there is a command from the MPU. The command usually consists of 6 to 8 words, including (1) operation mode, (2) operation channel number, (2) address, data transfer length, and (2) operation designation. When a command is detected, the Nosura meter is incremented by one word and set in the work buffer 7 of the corresponding channel.
Turns on the software flag during command processing. In the command state, when one word of the command parameter is processed, the process moves to the next transfer state. This is because the MVP is a centralized multi-operation data transfer device and requires that (I2 number of channels can be operated simultaneously).

That is, it is necessary to be able to accept commands on idle channels even during data transfer operations on active channels.

The remaining parameters are processed when moving to the next command state. When the last parameter is processed, the REQ port of the designated channel is made available for reception, the 7 lag during command processing is turned off, and the next command reception call is notified to the MPU. In the transfer state, the presence or absence of a bus gQ is checked, and if a bus BQn is present and the bus is not occupied, a bus request B is issued to the MPU, the 7 lag during a bus request is turned on, and the transition is made to a result state. Acquire bus in transfer state (BACK)
When detected, the process moves to data transfer processing for the corresponding channel.1
Execute a data transfer cycle.

Next, it moves to the result state and checks whether there is a data transfer completed channel. If there is a result, the result parameter is written to the DPM in order to similarly speed up the multi-channel REQ command search in the command state, and when one word is processed, the command state shifts to the next command state. As a result parameter, ■Completion status (normal/
abnormal).

There are contents of abnormal termination, channel number■address at the time of termination, and data transfer length. DPM the last result parameter
When written to, an interrupt is generated to the MPU to notify the end of the command. In particular, if there is an REQ with a high-speed request specified by the command °, it is possible to bend the result processing and pass control to the transfer state so that it can follow the REQ from the high-speed input/output 11ua section. 2 in Figure 3
The execution time for one loop of the command-transfer-result command is the execution time to
If a high-speed processor with ons/1 microinstruction speed is used, this can be achieved in an average of about 0.7 μs. In the case of A-A mode, the data transfer processing time depends on the access time of the memory and input/output control unit, but if it is 0.8 μs, the time for one transfer cycle is 1.5 μs, which is approximately A transfer capacity of 667KW/8ECB is possible.

〔Effect of the invention〕

As explained above, the present invention is as follows.

(1) Additional processor dedicated to high-speed data transfer (M
VP) to centrally control data transfer requests from each implant/output control unit.

(2) This MVP must exchange command state information with the main processor through a delle port memory interface that can be accessed at all times.

(3) MVI' has the function of controlling multiple buses and the function of data calculation processing, and by devising that data transfer is by program transfer, 2. A low-cost, centralized data transmission system that eliminates the need for human sub-control circuits, bus arbitrage circuits, and easily implements additional functions such as data calculation processing and data transfer between multiple buses. We can provide the circuit.

[Brief explanation of drawings]

PU... Processor, R, OM...
・Redirection, f memory, RAM...-Work memory, DPM...Dairport memory + M
PC: main processor interface control circuit, DPMe: dual hold memory control circuit,
RgQC...Data transfer request reception circuit, RFl
iQP...Data transfer request priority control circuit,
BU8C...Bus control circuit, DB...
Data bus, BRQ...Bus request signal, BAC
K... Bus permission (1, AB... Address bus. C0NT... Control signal, INT... Interrupt signal. MVP...... Data transfer processor, MPU...
--- Main processor, A, BUS --- Bus A
, B-13Us...Bus B, AM...
Memory A, A I O8, A I O2...B I
O, --- Various input/output control units on bus A, BM
...Memory B, 8101. BIO2...BI
Un... Each Sennin Deba control IC 11 section on bus B, l...-- Control interface between M P LJ-8 IVP, 2... Input/output side (to) section Data transfer request from 3...Bus signal input from MVP to bus B, 4...Bus signal input/output from MVP to bus person, MPU... -・Main processor section. DMC...D M A control 1 circuit, A control B...
...Request conflict control circuit, MM...Main memory IJ, I (JU,. l0Un...Various input/output control units, l0C1, I
O.C. ...Input/output itt control circuit, I/D 1
, I/Qn...Input/output device, 5-BUS
・・・・・・System bus, I) 几Q1゜DI(Q,
-, , , DMA transfer request, D ACK1. f
)ACKn---DMA request acceptance signal. 1 Bojinsu 1 Ryuushi Uchihara Susumu 2 Kunikaga 3 Diagram

Claims (1)

[Scope of Claims] A dedicated interface circuit including a command/result exchange circuit via the main processor and shared memory, a signal requesting bus release of the main processor, a signal notifying the main processor of an interrupt, and a dedicated interface circuit under the main processor. Receives multiple data transfer requests from various input/output control units, and generates and controls the priority control circuit between the transfer request signals and address data and various timing signals for data transfer control on a single or multiple buses. The dedicated interface circuit functions and commands given by the main processor. Priority control circuit, controls the functions to be controlled, multiplexly controls data transfer between any input/output control unit and memory, between memories, and between input/output control units, and performs data calculation and processing. A data transfer circuit characterized in that it has a dedicated processor capable of performing the following functions.