JPH09223103A - Information processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain maximum parallel operation without blocking respective modules such as CPU modules, memory modules and I/O modules connected to buses due to bus queuing by multiplexing buses connecting respective modules in a system consisting of plural CPU modules, plural I/O modules having DMA functions, and so on. SOLUTION: The system consists of system buses 20A, 20B, 20C, CPU modules 21, 22, memory modules 23, 24, DMA controllers 26, 27, and a bus arbitration circuit 25 connected to the system buses 20A to 20C through respective bus INFs 210, 220, 230, 240, 260, 270 and I/O modules 261, 262, 271, 272 connected to the DMA controllers 26, 27. Since the system buses 20A to 20C are multiplexed, the circuit 25 automatically allocates a usable system bus to a system bus request even when a certain module uses one of the system buses 20A to 20C.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing system, and more particularly to an information processing system including an input device having a high-speed CPU, a memory, a DMA function and a system bus connecting those modules.

[0002]

2. Description of the Related Art FIG. 7 is a diagram for explaining an example of the configuration of a conventional information processing system.
A DMA controller 1 in which the PU 11, the main memory 12, the bus arbitration circuit 13, and the input / output devices 141 and 142 are connected.
4 is connected. The CPU 11 is the system bus 10
Instructions and data are fetched and data is written from the main memory 12 via the I / O device 14.
1, 142 are DMAs with the main memory 12 via the system bus 10 under the control of the DMA controller 14.
Transfer. The bus arbitration circuit 13 arbitrates the request of the system bus 10 according to a predetermined priority, and the CPU 11 and D
The bus right is given to the MA controller 14.

[0003]

In the conventional information processing system as described above, the main memory 12 and the input / output device 1 are used.
41, 142 DM a large amount of data such as image data
During the A transfer, the CPU 11 cannot use the system bus 10,
On the contrary, while the CPU 11 is accessing the main memory 12 via the system bus 10, even if there is another memory block, the DMA controller 14 sets the system bus 1
Since 0 cannot be used, the I / O devices 141 and 142 cannot perform DMA transfer with the memory block, which hinders improvement of the performance of the entire system.

Further, in a system having a plurality of CPUs and DMA controllers, while one CPU or DMA controller is using the system bus, another CPU or DMA controller cannot use the system bus and processing is blocked. System bus contention is a major obstacle to improving system performance.

In Japanese Patent Laid-Open No. 3-122744 (computer system), a CPU bus and a DMA bus are separately provided, but a plurality of CPUs and D
The problem cannot be solved for the competition between the CPUs and the competition between the DMA controllers in the system including the MA controller.

The present invention has been made in view of the above-mentioned circumstances, and in a system including a plurality of CPU modules, a plurality of memory modules, a plurality of I / O modules with a DMA function, etc., a bus connecting the modules is provided. It is designed to improve system performance by multiplexing and enabling modules connected to the CPU, memory, I / O, etc. buses to operate in parallel at the maximum without blocking due to waiting for the bus. is there.

[0007]

According to a first aspect of the present invention, there is provided a system bus, and a CPU module, a memory module and a DMA which are connected to the system bus via respective bus I / Fs.
In an information processing system including an I / O module connected to a controller, a bus arbitration circuit, a DMA controller, etc., the system bus is multiplexed, and even if a certain module is using one system bus, it responds to the system bus request. The bus arbitration circuit automatically allocates a usable system bus.

According to a second aspect of the present invention, a system bus, a CPU module connected to the system bus via each I / F, a memory module having a plurality of blocks, a DMA controller, a bus arbitration circuit, and an I / O connected to the DMA controller. In an information processing system including an O module, etc., the system bus is multiplexed, and a memory block for CPU access and a memory block for DMA access can be switched, and DMA operation and CPU
Memory access can be executed in parallel at the same time.

According to a third aspect of the present invention, a system bus, a CPU module connected to the system bus via each I / F, a memory module having a plurality of banks configured to be mapped in the same address space, a DMA controller, a bus arbitration circuit, In an information processing system including an output device and the like connected to a DMA controller, when the system bus is multiplexed and data is once written to a specific DMA address space by a CPU or a DMA controller, the data is a predetermined output device. Against D
When a data write request is made again from the CPU or the DMA controller before the MA transfer is completed, the memory bank controller automatically switches the memory banks in a predetermined order and the DMA transfer is not completed. The data is written in a memory bank different from the memory bank, and a DMA controller connected to a predetermined output device is notified that the data to be transferred by DMA transfer exists in a plurality of memory banks. is there.

According to a fourth aspect of the present invention, a system bus, a CPU module connected to the system bus via each bus I / F, a memory module having a plurality of banks configured to be mapped in the same address space, a DMA controller, and a bus arbitration circuit. In an information processing system including an input device connected to a DMA controller, the system bus is multiplexed, a specific DMA address space is determined, and data is transferred from a predetermined input device by DMA transfer in the address space. CPU is written after
Alternatively, if the data write request by the DMA transfer is made again from the input device before the data reading process is completed from the DMA controller, the memory bank controller automatically switches the memory banks in a predetermined order. New data from the input device is written to a memory bank different from the previously written memory bank prior to or at the same time as the reading process by the CPU or the DMA controller.

According to a fifth aspect of the present invention, in the third or fourth aspect, when there is unprocessed data in all the memory banks, a CPU or a DMA controller,
Alternatively, when a next data write request is issued from a specific input device, the memory bank controller returns a response indicating that the write is not possible to the request source.

According to a sixth aspect of the present invention, a system bus is connected to a CPU module connected to the system bus via each bus I / F, a memory module having a plurality of blocks, a DMA controller connected to an input device, and an output device. In an information processing system including a DMA controller, a bus arbitration circuit, etc., the system bus is multiplexed, and a memory block for writing data from an input device by DMA transfer, a memory block for CPU access, and data output by DMA transfer to an output device. The memory blocks can be switched so that an input DMA operation, a CPU memory access, and an output DMA operation can be simultaneously executed in parallel.

According to a seventh aspect of the present invention, a system bus, a CPU module connected to the system bus via each bus I / F, and a memory module of a plurality of banks configuration mapped in the same address space and having an access identification mark function. In an information processing system including a DMA controller connected to an input device, a DMA controller connected to an output device, a bus arbitration circuit, etc., the system bus is multiplexed, and all memory banks in a specific address space are first filled with When there is a data write request from the DMA controller connected to the input device and connected to the input device, the memory bank with the unused mark is connected, and when the data write by the input DMA transfer is completed, Marked as entered, C
When an access request is issued from the PU to the same address space, the memory bank with the input mark is connected, and C
When the PU processing is completed, a processed mark is added, and when there is a data read request from the DMA controller connected to the output device, the memory bank with the processed mark is connected as the DMA transfer source memory bank, and the output D
When the data reading by the MA transfer is completed, an unused mark is added to the memory bank so that the input DMA operation, the CPU memory access, and the output DMA operation can be simultaneously executed in parallel.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below.
Even if one CPU is accessing a memory block via the system bus, other CPUs and DMA controllers can simultaneously access other memory blocks via the open system bus. The memory space is made up of multiple banks and a bank switching mechanism is provided to improve the performance of an information processing system that performs a series of processing such as reading a large amount of data from an input device, processing it, and transferring it to an output device. It is a thing.

FIG. 1 is a diagram for explaining one embodiment of the invention of claim 1, and as shown in the figure, a CPU module 2
1, 22; memory modules 23, 24; DMA controllers 26, 27 are respectively bus I / Fs (210, 220; 230, 240; 2)
System bus 20A, 2 that has been triplicated via (60, 270)
It is connected to 0B and 20C. Further, there is a bus arbitration circuit 25 that arbitrates the bus use right from these modules, and a necessary control signal 101 is connected to each bus I / F.

FIG. 2 is a diagram for explaining an embodiment of a control signal connected to the bus arbitration circuit 25. When the CPU 1 (21 in FIG. 1) tries to use the system bus,
The bus arbitration circuit 25, which asserts (activates) the CPU1BR (CPU1BusRequest) that is a bus request signal, checks the BB1 (BusBusy1) signal indicating the usage status of the system bus, and sends the CPU1 CPU1BG1 (CPU1BusGrant) to the CPU1.
1) Assert the signal. CPU1 receives this and BB
Assert the 1 signal to start using the first system bus 20A.

Subsequently, in this state, the DMA controller 1
(27 in FIG. 1) is the system bus request signal DMA1
When BR is asserted, the bus arbitration circuit 25 checks the usage status signal BB1 of the first system bus 20A, but since it is in use, it checks the usage status signal BB2 of the second system bus 20B, and the DMA controller 1 (2
For 7), assert the DMA1BG2 signal. D
Upon receiving this signal, the MA controller 1 (27) immediately asserts the BB2 signal, and the second system bus 20B
Start using. When both the CPU1 (21) and the DMA controller 1 (27) finish using the bus, BB1 and BB2
Negate (deactivate).

FIG. 3 shows a bus of a triple system bus.
FIG. 1 is a diagram showing an example of a configuration of a master side bus I / F, in which a CPU 1 (41) that is a bus master has tripled system buses 40A, 40B, 40C and buffer circuits 43, 44,
It is connected through 45. These buffers are controlled by control signals 40d, 40e, 40f from the control unit 42.

A bus request signal 40 from the CPU 1 (41) is provided between the control unit 42 and the CPU 1 (41).
b, a bus use right acquisition signal 40c, and a system bus request signal 40g, a system bus use right acquisition signal 40h, and a bus busy signal 40i between the bus arbitration circuit.

A system bus clock 40k is also connected to the control unit 42. When the bus use request signal 40b is asserted from the CPU 1 (41), the control unit 42 asserts the bus request signal 40g to the bus arbitration circuit. Bus usage right acquisition signal C from the bus arbitration circuit
When one of PU1BG [1: 3] (40h) is asserted, the buffer enable signal 4
One of 0d, 40e, and 40f is asserted to connect any of the corresponding system buses 40A, 40B, and 40C to the signal 40a necessary for the data, address, and read / write operations from the CPU1 (41), and corresponding System bus busy signal BB1, BB2, BB3 (40
Assert one of i). At the same time, CPU1 (41)
The CPU 1 starts a system bus cycle by also asserting the bus acquisition signal BG (40c) to the CPU.

FIG. 4 shows a bus of a triple system bus.
FIG. 3 is a diagram for explaining a configuration example of a bus I / F on the slave side, in which a memory 51 as a slave module is connected via system buses 50A, 50B, 50C and buffer circuits 53, 54, 55. Has been done. These buffer circuits include an address decoding circuit, and assert the connection request signals 50d, 50e, 50f to the control unit 52 by decoding corresponding to the access from the system bus. The control unit 52 receives these connection request signals and, if the system bus and memory are not already connected, asserts enable signals 50g, 50h, 50i to the buffer that asserted the connection request to connect the system bus and memory. To do.

FIG. 5 is a diagram for explaining one embodiment of the invention of claim 7, which is a CPU module 61, a normal memory module 62, a DMA controller 1 (66), and a DM.
The A controller 2 (65) uses the bus I / F 610,
Three memory banks 631, 632, and 633 are connected to the bus I / F function and the memory via the 620, 660, and 650.
Via the memory bank controller 630 having a bank switching function, the tripled system bus 60A,
It is connected to 60B and 60C.

A bus arbitration circuit 64 for arbitrating bus use requests from each module and each bus I / F are connected by a control signal 601 required for bus arbitration. Furthermore, DM
The A controller 1 (66) has an input device 661 with a DM
An output device 651 is connected to the A controller 2 (65), and the image data input from the input device 661 is transferred to C
It is assumed that a series of processes in which the PU 61 performs a certain process and outputs it to the output device 651 is repeatedly executed.

FIG. 6 is a diagram for explaining one embodiment of the memory bank controller, in which three memory banks 71, 72,
System bus 70A, 70B, 70 in which 73 is tripled
It is connected to C. Memory bank controller 7
Reference numeral 0 includes a control unit 700, a system bus, buffer circuits 701, 702 and 703, and buffers (711,721,731; 712,722,732; 713,723,733) to each memory bank. Although not particularly shown, it is assumed that the access identification mark of each memory bank is held in the control unit 700, and the memory bank request / response signals 70a, 70 corresponding to each system bus are used as control signals.
b, 70c and the system bus clock 70k are connected. The access identification marks of the memory banks are all given unused marks by the initialization process. Then, an input request to the memory bank request signal 70a corresponding to the system bus 70A is issued by the DMA controller 1 (6
6) when asserted from the system bus 7 by the buffer enable signals 70d and 70c.
0A and the memory bank 71 to connect the buffer circuit 7
01 and 711 are enabled, and the DMA controller 1 receives the memory bank (reserve) response signal 70a.
Respond to (66).

As a result, data is written from the input device 661 to the memory bank 71 by DMA transfer. When the input is completed, the DMA controller 1
The controller 70 is notified of the end of input by the control signal 70a, whereby the buffer is disabled, the system bus 70A and the memory bank 71 are separated, and at the same time, the memory bank access identification mark corresponding to the memory bank 71 has been input. A mark is added, and only the processing request by the CPU can be received for this memory bank. Thereafter, the processing request from the CPU and the output request from the DMA controller 2 are processed in the same manner, and the input DMA
Transfer, CPU processing, and output DMA transfer are simultaneously executed in parallel.

[0026]

In an information processing system having a plurality of CPUs and DMA controllers, even if one CPU or DMA controller is using the system bus, another C
Since the PU and DMA controllers also use the dynamically available system bus, each processing module does not have a bus and is not blocked, and the maximum parallel operation can be performed to improve the system performance. Further, in a controller of a copying machine or a page printer, a process of fetching a large amount of image data from an input unit, performing image processing of the image data and transferring the image data to an output unit is repeated, but by performing parallel processing of input, processing, and output simultaneously. The performance of the entire copying machine and page printer can be improved.

[Brief description of drawings]

FIG. 1 is a block configuration diagram for explaining an embodiment of an information processing system according to the present invention.

FIG. 2 is a diagram for explaining an example of a control signal connected to a bus arbitration circuit.

FIG. 3 is a diagram for explaining an example of a bus I / F of a bus master example of a tripled system bus.

FIG. 4 is a diagram for explaining an example of a bus I / F on a bus / slave side of a tripled system bus.

FIG. 5 is a block configuration diagram for explaining another embodiment of the information processing system according to the present invention.

FIG. 6 is a diagram for explaining one embodiment of a memory bank controller.

FIG. 7 is a block configuration diagram for describing an example configuration of a conventional information processing system.

[Explanation of symbols]

11, 12, 22, 41, 61 ... CPU, 12, 23,
24, 51, 62 ... Memory, 13, 25, 64 ... Bus arbitration circuit, 14, 26, 29, 65, 66 ... DMA controller, 70 ... Memory bank controller, 71,
72, 73 ... Memory bank, 10; 20A, 20B, 2
0C; 40A, 40B, 40C; 50A, 50B, 50
C; 60A, 60B, 60C ... System bus.

Claims (7)

[Claims] 1. A system bus and a CPU module, a memory module, a DMA controller, a bus arbitration circuit, and a DM which are connected to the system bus via a bus I / F.
In an information processing system including an I / O module connected to an A controller, the system arbitration circuit responds to a system bus request even if the system bus is multiplexed and a certain module is using one system bus. An information processing system characterized in that an available system bus is automatically assigned. 2. A system bus and a CPU module connected to the system bus via each I / F, a memory module having a plurality of blocks, a DMA controller, a bus arbitration circuit, an I / O module connected to the DMA controller, and the like. In the information processing system, the system bus is multiplexed, and a memory block for CPU access and a memory block for DMA access can be switched so that the DMA operation and the memory access of the CPU can be simultaneously executed in parallel. Information processing system. 3. A system bus, a CPU module connected to the system bus via each I / F, a memory module having a plurality of banks configured to be mapped in the same address space, a DMA controller, a bus arbitration circuit, and a DMA controller. In an information processing system including output devices and the like, when the system bus is multiplexed and data is once written in a specific DMA address space by a CPU or a DMA controller, the data is DMA-transferred to a predetermined output device. If a data write request is issued again from the CPU or the DMA controller while the memory transfer is not completed, the memory bank controller automatically switches the memory banks in a predetermined order, and the memory transfer which has not completed the DMA transfer. Memory different from bank A DM in which data is written to the bank and a predetermined output device is connected.
An information processing system characterized by notifying an A controller that data to be transferred by DMA transfer exists in a plurality of memory banks. 4. A system bus, a CPU module connected to the system bus via each bus I / F, a memory module having a plurality of banks configured to be mapped in the same address space, a DMA controller, a bus arbitration circuit, and a DM.
In an information processing system including an input device connected to an A controller, the system bus is multiplexed, a specific DMA address space is determined, and data is transferred from a predetermined input device by DMA transfer in the address space. After the data is written, if the CPU or the DMA controller does not finish reading the data, and the input device again requests the data write by the DMA transfer, the memory bank controller automatically performs the predetermined order. Switch memory banks,
An information processing system characterized in that new data from an input device is written to a memory bank different from a previously written memory bank before or at the same time as a reading process by a CPU or a DMA controller. 5. The method according to claim 3 or 4, when there is unprocessed data in all the memory banks, and the next data write request is issued from the CPU or the DMA controller or a specific input device. ,
An information processing system characterized in that a response indicating that the memory bank controller is in a write-disabled state is returned to a request source. 6. A system bus, a CPU module connected to the system bus via a bus I / F, a memory module having a plurality of blocks, and a D connected to an input device.
In an information processing system including a MA controller, a DMA controller connected to an output device, a bus arbitration circuit, etc., a memory block and a CPU for multiplexing the system bus and writing data from an input device by DMA transfer
The memory block to be accessed and the memory block which outputs data by DMA transfer to the output device can be switched, and the input DMA operation, the CPU memory access, and the output D can be performed.
An information processing system characterized in that MA operations can be simultaneously executed in parallel. 7. A system bus, a CPU module connected to the system bus via each bus I / F, a memory module having a plurality of banks configured to be mapped in the same address space and having an access identification mark function, and an input device connected to each other. D controller with connected DMA controller and output device
In an information processing system including an MA controller, a bus arbitration circuit, etc., first, a DMA controller in which an unused mark is attached to all memory banks of a specific address space and the input device is connected to the system bus is multiplexed. When a data write request is made, a memory bank with an unused mark is connected. When the data write by the input DMA transfer is completed, the memory bank is marked with an input mark and the CPU writes the same address space. When an access request is made, a memory bank with an input mark is connected, and when the CPU processing is completed, the processed mark is added, and when there is a data read request from the DMA controller connected to the output device, the processed mark is displayed. The attached memory bank is the DMA transfer source memory bank. When the data is read out by the connection and output DMA transfer is completed, an unused mark is added to the memory bank so that the input DMA operation, the CPU memory access, and the output DMA operation can be simultaneously executed in parallel. Information processing system.