JPH0895899A - Dma transfer controller - Google Patents

Abstract

PURPOSE: To provide an I/O device, which is connected to a high-performance split type I/O bus, with a high-throughput, low-latency DMA transfer control function. CONSTITUTION: On the I/O device, plural controllers 123 and 124 which serve bus requests outputted to a split bus at the same time, a buffer 112 which temporarily holds response packets to a read request, a request packet generating circuit 111 which generates request packets from the outputs of the controllers 123 and 124, and a response packet processing circuit 110 which distributes the services of the response packets to corresponding read controllers are provided, and, by constituting the controllers 123 and 124 dividing into a function which services request packets and a function which services response packets, parallel processing in the controllers is made possible. Since not only the parallel operation of the controllers which serves a bus transaction, but also the parallel operation in the controllers are made possible, the DMA transfer controller which has higher performance than before is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a personal computer,
In a computer system such as a workstation, it is concerned with a high-speed DMA transfer control system in an I / O device connected to a split bus. In particular, it is suitable for realizing a low latency and high throughput DMA transfer device between a memory device and an I / O device.

[0002]

2. Description of the Related Art As a high performance bus, a split bus system is being adopted in place of the conventional interlock system bus. This movement is particularly noticeable in tightly coupled multiprocessor systems. The conventional interlocking type bus cannot start the next bus transaction until one bus transaction is completed. On the other hand, the split bus can effectively use the bus area by separating the bus transaction into a request phase and a response phase to avoid the lock of the bus as much as possible. Therefore, as compared with the interlock system bus, low latency and high throughput data transfer can be performed.

An example of the split bus is a bus called XDBus. (Nikkei Electronics 1993.10.25 (pp.9
(See 7-114)) In XDBus, information is transferred in the form of packets. A transaction is completed by a pair of request packet and response packet. In XDBus, the number of IDs assigned to I / O devices is limited to one, and all devices connected to XDBus must guarantee the correspondence between request packets and response packets on the output side of response packets. There is a limitation. 1 ID per I / O device like XDBus
In a split bus that has only this, there is a problem that it is necessary to store the order of arrival of request packets from one I / O device on the output side of the response packet and output the response packet in that order. To solve this problem, I / O devices are assigned multiple IDs, and different request packets are assigned different IDs.
ID (hereinafter called TID (Transaction ID)) is added to the request, and when the response side is ready to return the response packet, the TID attached to the request packet is attached to the response packet The response packets can be returned in any order by returning to. In addition, as a technique for increasing the processing speed of the split bus by using a plurality of TIDs, the following two means have been used.

(1) A plurality of packet control circuits are prepared for each TID, and they are operated in parallel. However, the packet control circuit is a circuit for sequentially controlling the request packet processing and the response packet processing corresponding to the request packet.

(2) The request packet output side outputs the request packet to the bus as continuously as possible. In order to realize this, it is necessary to execute the bus request reception process inside the I / O device and the bus request reception process on the bus asynchronously. This is because the order of reception of bus requests from the bus requester is set in advance. This can be implemented by storing the request packet in a queue inside the I / O device and outputting the request packet generated in advance to the bus when the bus grant signal is received from the bus.

[0006]

The method (1) of operating a plurality of packet control circuits in parallel inside the I / O device has been considered as a means for increasing the processing speed of the split bus. The method of overlapping the request packet processing and the response packet processing in the packet control circuit has not been considered so much.

[0007]

In order to solve the above-mentioned problems, request packet processing and response packet processing, which were conventionally executed only serially, are executed in parallel in one packet control circuit.

FIG. 4 shows the configuration of a packet control circuit that solves the above problems. In the configuration of Figure 4, the device has three TIDs.
Is assigned, and there is a packet control circuit for each TID, and up to two read bus transactions and one write bus transaction can operate in parallel. However, the read bus transaction consists of a request packet and a response packet, but the write bus transaction consists of only a request packet. In order to solve the above problem, the ID information of the bus requester that issued the bus request that causes the request packet in the read controller is the first tag ID, and the ID information of the bus requester that should receive the response packet data. The second tag ID
Memorize as. The write controller that completes the bus transaction with only the request packet is the first tag.
Has only an ID. The first tag ID stores the bus requester ID that issued the first bus request between the reception of the first bus request and the reception of the next second bus request, and the second tag ID is the first The bus requester ID that issued the first bus request is stored from the time when the bus grant corresponding to the second bus request is received until the time when the bus grant corresponding to the second bus request is received.

[0009]

[Operation] In the packet control circuit for controlling the service of the bus transaction in which the request packet and the response packet are completed as a pair in this way, the bus requester IDs of two consecutive bus request sources are stored in two tag IDs. Therefore, it is possible to accept a bus request from another bus requester while executing a service to a bus requester that expects a response packet, and process the request packet and the response packet in the same packet control circuit. The overlap operation can be performed, and the split bus processing speed can be increased.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a DMA transfer processing device which operates based on the DMA transfer control method of the present invention will be described in detail below with reference to FIGS.

FIG. 1 shows a block diagram of a DMA transfer processing device. Reference numeral 100 is a DMA transfer processing device connected to the bus. Here, the split bus 101 includes a request phase for outputting a request packet to the split bus and a response phase for receiving a response packet from the split bus when the bus transaction is DMA read.
In the case of DMA write, it is assumed that the bus includes only a request phase for outputting a request packet to the bus. Therefore,
The DMA read request packet includes a read address as request packet data, and the DMA write request packet similarly includes a write address and write data as request packet data. Further, the read data is included in the DMA read response packet as response packet data. 102 is a bus interface circuit. 107 is a timing signal indicating the arrival of the response packet, and 108 is the transaction ID value included in the response packet, which is the same value as the transaction ID value included in the read request packet corresponding to the response packet. However, the transaction ID value is a control signal on the bus that indicates the ID of the device that issued the request packet. 106 is an internal data bus.

The response packet processing circuit 110 has a function of generating the response data arrival timing signal 117 for the controller servicing the read request, and at the same time properly transferring the response packet to the bus requester. In addition,
The response packet data is written to the data buffer 112 according to the timing signal 129 before being delivered to the bus requester, and then the response packet arrives by the bus requester reading the contents of the data buffer in the order of the read request at an appropriate timing. Even if the order is reversed, the data can be delivered to the bus requester in the requested order.

FIG. 2 shows an embodiment of the response packet processing circuit. The comparator 201 compares the transaction ID value 108 included in the response packet with the ID value 206 of its own device. Since the transaction ID value included in the response packet is the same as the ID value of the device that issued the read request packet if the packet is addressed to its own device, this comparator causes the response packet on the split bus to be addressed to its own device. Can be determined. The comparator 202 determines whether the response packet is served by the read controller A123, and the comparator 203 determines whether the response packet is served by the read controller B124. Reference numeral 208 indicates the LSB bit of the transaction ID value attached to the request packet serviced by the read controller A, and 209 indicates the LSB bit of the transaction ID value attached to the request packet serviced by the read controller B. In the present embodiment, since there are only two read controllers, one bit is sufficient to distinguish the read controller that services the response packet, but if there are three or more read controllers, two or more bits are required. Is. Reference numeral 213 is a data valid signal indicating the timing at which a response packet to be serviced by the read controller A has arrived. Similarly, 214 is a data valid signal indicating the timing at which a response packet to be serviced by the read controller B has arrived. It is a signal. A decoder 215 generates a second tag ID value 128 corresponding to the bus requester expecting a response packet, and a data write timing signal 129 for the bus requester that issued the read request from the data valid signal.

The request packet processing circuit 111 generates a request packet for DMA read or DMA write based on the control signal from the packet control circuit 119 and transfers it to the bus interface circuit 102, and at the same time, a controller in the packet control circuit. And the data read timing signal 139 from the bus requester 130 which issued the write request.

FIG. 3 shows an embodiment of the request packet processing circuit. First, the bus request arbiter control circuit 116
The bus request signal 103 is asserted by receiving the read request signal 126 or the write request signal 137 from. Next, the bus request arbiter control circuit 116 stores the bus request order issued by the bus request arbiter control circuit 116 when the bus grant signal 105 is received and the request packet not yet output to the bus is stored in the bus request arbiter control circuit 116. Output to the bus in the order requested by. By asserting the bus grant signal, a read request bus grant signal 115 is returned if the next request packet to be output to the bus is a read request packet, and a write request bus grant signal 118 is returned if it is a write request packet. The bus request queue control circuit 304 is a state machine that controls the bus request queue. However, the bus request queue is a queue that stores the occurrence order of the activation request signal for each controller. This state machine performs enqueue processing by asserting the activation request signal to each controller in order to store the occurrence order of the activation request signal, and when the bus grant signal 105 is asserted, the activation request signal located at the head of the request queue is sent. At the same time as asserting the bus grant signal to the accepted controller, dequeue processing is performed. Also, the bus request priority TOP signal is asserted to the controller that services the bus request located at the head of the queue. Request signal of the read request packet during the period from issuing the bus request to receiving the bus grant TOP signal 12
5, the first tag ID value 128 corresponding to the bus requester that issued the read request, the request priority TOP signal of the write request packet
134. Since the tag ID value 138 corresponding to the bus requester that issued the write request does not change, the encoder 301 encodes this to generate the control signal 104 indicating the attribute of the request packet. However, the bus request order TOP signal 125 of the read controller and the bus request order TOP signal 134 of the write controller are exclusive signals, and the write data valid signal 135 is input to generate the data valid signal of the write request packet. The control signals that indicate the attributes of the request packet are the address valid signal, the data valid signal, and the ID of the own device.
It includes information such as a transaction ID value created from the value 206, a bus transaction command, and the like. Similarly, a timing signal 135 for the write controller to output the data contained in the write request packet to be serviced to the bus.
By decoding the tag ID value 138 and the tag ID value 138 by the decoder 302, the data read timing signal 139 for one bus requester that actually issued the bus request is generated. The bus request control circuit 303 asserts the bus request signal 108 by a signal obtained by logically ORing the activation request signal 126 for the read controller and the activation request signal 137 for the write controller, and negates the bus request signal 108 by asserting the bus grant signal 105. To do.

The packet control circuit 119 comprises a read controller A123, a read controller B124, and a write controller 135. The read request service and the write request service are independently controlled by each controller to enable parallel operation. . Each controller is a primitive DMA that does not depend on the split bus specifications.
Provides control functions only.

The bus request arbiter control circuit 116 serializes the bus requests from the plurality of bus requesters 120 that issued read requests and the plurality of bus requesters 130 that issued write requests, and then services the serialized bus requests. And has a function of permitting output of the next request by returning a grant signal to the bus requester that has accepted the request. When the serialized bus request is a read request, the read controller activation signal 126 is asserted, and when the serialized bus request is a write request, the write controller activation signal 137 is asserted. The bus request serialization algorithm is as follows, for example.

First of all, only bus requesters requesting service to the controller in the ready state are eligible to participate in serialization arbitration. Here, the ready state refers to a state in which bus transaction control for a bus request is not being executed. For example, when the ready signal 127 of the read controller is negated, the read request cannot be accepted even if the read request signal 121 is asserted. Therefore, in this case, the grant signal 122 indicating that the request has been accepted to the bus requester making the read request is not asserted. At this time, the light controller is in the ready state,
When the write request signal 131 from the bus requester is asserted, the write request is accepted as a result of serialization. Specifically, the write controller 135 is activated by asserting the write controller activation request signal 137, and at the same time, the grant signal 132 indicating that the request has been accepted is asserted to the bus requester that issued the write request. The write request signal 131 is negated by the assertion of the grant signal 132.

On the contrary, the ready signal 13 of the write controller
When 6 is negated and the read signal 127 of the read controller is asserted, the read request is accepted. Specifically, by asserting the read request signal 126, the read controller A123 or the read controller B124 is activated, and at the same time, the grant signal 122 indicating that the request has been accepted is asserted to the bus requester that issued the read request. . The read request signal 126 is negated by asserting the grant signal 122,
When there is a next read request, the read request signal 126 is asserted again. By having a plurality of read controllers in this way, the read controllers in the ready state can be activated one after another without waiting for the arrival of the response packet, so that read requests can be issued continuously. When both the read controller and the write controller are ready, only one controller is activated according to the priority order. For example, in the priority algorithm based on the round robin, when the previously serialized request is a read request, the write request is preferentially accepted when the next read request and the write request are asserted at the same time. Further, the bus request arbiter control circuit 116 converts the ID value of the bus requester requesting the service into the tag ID value 114 when activating the controller selected as a result of the serialization. Since the value changes, the tag ID value 114 is stored in the activated controller until the bus transaction is completed. The tag ID value uniquely corresponds to the selected bus requester ID value.

Next, FIG. 4 shows an embodiment of the packet control circuit in the case where the bus request queue control circuits 304 are dispersedly provided inside each controller. In this embodiment, like the packet control circuit 119 shown in FIG. 1, two read controllers and one write controller operate in parallel. This is different from the packet control circuit 119 shown in FIG. 1 in that the bus request queue control circuit 304 shown in FIG. 3 is distributed in each controller as a slave sequencer. First, the logic other than the sequencer necessary for the sequencer operation will be described. 403 and 413 are composed of two latches that store the tag ID value of the bus requester that issued the read request and a counter that detects the last data of the response packet. If there is a tag ID value corresponding to the request packet and a tag ID value corresponding to the response packet as the tag ID value, and when preparing to output the next request packet during the reception processing of the response packet, two tag ID values Have different values.
Similarly, the 423 also issued a write request. Tag I of the bus requester.
It consists of a latch to store the D value and a counter to detect the last data of the request packet.

Next, the sequencer operation inside each controller shown in FIG. 4 will be described in detail with reference to the state transition diagrams shown in FIGS. 5A, 5B and 5C. 5A is a state transition diagram of the master sequencers 401 and 411 in the read controller, and FIG.
Shows a state transition diagram of the master sequencer 422 in the write controller. FIG. 5C shows a state transition diagram of the slave sequencers 402, 412, 422 in each controller.

As an example, a bus request arbiter control circuit
The operation of each unit when the bus request is received by the 116 in the order of read, write, and read will be described step by step. To facilitate understanding of the following description, FIG. 6 shows a timing diagram of internal signals of each controller. First, assume that each controller is all ready. In the ready state, both the master sequencer and the slave sequencer are in the idle state. At the same time that the first read request 126A is received, the master sequencer 401 in the read controller A123 that has received the request transits to the bus grant wait state 502. In this bus grant wait state, the request packet set signal 404 continues to be asserted. Due to the assertion of the request packet set signal 404, the request packet set signals (414, 424) input from other controllers have not yet been asserted at this point, so the slave sequencer 402 transits to the bus grant wait top state 522. To do. In this bus grant wait order TOP state, the request packet TOP order signal 125 continues to be asserted. After that, when the bus grant signal 105 arrives, the slave sequencer 402 in the bus grant waiting order TOP state asserts the bus grant signal 405 to the master sequencer 401, thereby causing the master sequencer 401 to transit to the response packet waiting state 503. On the other hand, the top ranking for bus grants
The slave sequencer 402 in the state transits to the idle state 521 upon arrival of the bus grant signal. It should be noted that both the master packet sequencer and the slave cell sequencer are in a state transition due to the assertion of the bus grant signal 405 to the master sequencer 401, so that the request packet set signal 404 and the bus request order TOP signal 125A are both negated. When the response packet for the first read request arrives, the response packet arrival signal 117A is asserted, and as a result, the signal 406 is asserted at an appropriate timing, and the master sequencer 401 does not accept the next request. When the request is received, the state transits to the bus grant waiting state 502. Following the above sequence, the request packet output phase and the response packet reception processing phase for the first read request are completed. In the response packet reception processing phase, if the method of asserting the signal 406 when the first data of the response packet arrives, it is possible to start the output processing of the next read request packet during the reception processing of the response packet. Therefore, the read throughput performance is improved.

The first tag ID value 407 relating to the request packet processing is held until the bus grant arrives after the read controller A123 is activated, and the second tag ID value 408 relating to the response packet processing is , It is held between the arrival of one bus grant and the arrival of the next. Therefore, while the response packet arrives,
It is guaranteed that the value of the second tag ID value 408 will not change. Therefore, the second tag ID value 408 is set to the response packet processing circuit 1
By decoding at 10, it becomes possible to correctly write the response data contained in the response packet to the bus requester that actually issued the read request. If the method of asserting the signal 406 when the last data of the response packet arrives is adopted, the first tag ID value 407 and the second tag ID value 408
Can be output from the same latch and the hardware can be simplified, but the next request packet cannot be output during the reception process of the response packet, so if another read controller is not ready, the response packet Since the next read request cannot be received at the same time as the reception of, the read performance is degraded.

The master sequencer 421 in the write controller 133 which has received the write controller activation request signal 137 by the next write request transits to the bus grant wait state 512. On the other hand, when the bus grant for the previously issued read request has not arrived, the slave sequencer 422 has the bus grant wait priority second state because the request packet set signal 404 of the read controller A123 has already been asserted. When transitioning to 523 and the bus grant for the previously issued read request has already arrived, the request packet set signal of the read controller A123.
Since 404 is already negated, the state immediately transits to the bus grant waiting order TOP state 522. In this state, the bus request order TOP signal 134 continues to be asserted. After that, when the bus grant signal 105 arrives, the slave sequencer 422
Asserts a bus grant signal 426 to the master sequencer 421 to cause the master sequencer 421 to transition to the write data output end wait state 513, and at the same time the slave sequencer 422 to transition to the idle state 521. In the write data output end waiting state 513, the write data valid signal 135 is asserted. In addition, master sequencer 4
By asserting the bus grant signal 426 for 21, the request packet set signal 424 and the bus request order TOP signal 134 are both negated. When the signal 427 is asserted at the timing of outputting the last data of the write data to the bus and the master sequencer 401 does not accept the next write request, it enters the idle state 511, and when it accepts the next write request, it waits for the bus grant. Transition to state 512.

The second read request is always serviced by the read controller B124 because the read controller A123 is not in the ready state when the response packet for the first read request has not arrived. When the response packet processing for the is completed, the read controller A123 may be serviced by the read controller A123 because the read controller A123 is already in the ready state. However, in FIG. 6, unlike the first read request, the second read request is serviced by the read controller B. The operation of the master sequencer 411 in the read controller B124 is the read controller A123.
The operation is exactly the same as the master sequencer inside. on the other hand,
The state transition of the slave sequencer 412 has the following three cases depending on the arrival timing of the bus grant signal 105. (Fig. 6 shows the case of (2).) (1) If the bus grant for the first read request and the next write request has not yet arrived when the second read request is accepted. First, the waiting order for the bus grant
Wait for the bus grant when the bus grant for the first read request arrives in the third state 524. Wait for the bus grant when the bus grant for the first read request arrives and the bus grant for the second request arrives next. Transition to the TOP status 522.

(2) If the bus grant for the first read request has already arrived and the bus grant for the next write request has not arrived at the time when the second read request is accepted, first wait for the bus grant. It transits to the second priority state 523, and transits to the bus grant waiting priority TOP state 522 when the bus grant for the write request arrives next.

(3) If the bus grant for the first read request and the next write request have already arrived at the time when the second read request is accepted, the state immediately transits to the bus grant waiting order TOP state 522. .

In any of the above cases, the slave sequencer
412 receives the bus grant signal at the time when the state transits to the bus grant waiting order TOP state 522, transitions the master sequencer to the response packet waiting state 503, and processes the response packet when the next response packet arrives.

As can be seen from the above description, in the distributed control system in which the bus request queue control circuits are distributed and stored in the slave sequencer in each controller, the master sequencer does not operate in parallel and only its own controller operates independently. It can be considered that the slave sequencer operates as a so-called "sequencer", and the slave sequencer operates as a sequencer for arbitrating conflicting operations that occur when the controllers perform multiple operations.

In this embodiment, the read controller servicing the read request and the controller servicing the write request are composed of physically different circuits. However, as can be seen from the above description, the state transition of the master sequencer is read. There is no difference between the light and the light, so it can be used for both. That is, the packet control circuit of the I / O device that can use three transaction IDs can be composed of two read controllers, one write controller, or three read / write controllers.

[0031]

According to the present invention, not only the parallel operation of the controllers servicing bus transactions allocated for each TID but also the parallel operation inside the controllers becomes possible, so that the DMA transfer control with higher performance than the conventional one is possible. The effect is that the device can be realized. Further, by configuring the controller as a read / write controller, it is possible to locally increase the parallel operation degree of the controllers. Therefore, it is possible to achieve a higher DMA than the read-only controller and the write-only controller.
Transfer performance can be realized.

Further, since the controller assigned to each TID operates independently, unless the bus is saturated, the TID
There is also an effect that the DMA transfer performance can be improved in a scalable manner by increasing the number of.

Further, the internal logic change of the controller, which is necessary when the number of TIDs is increased, is limited to the slave sequencer, and moreover, the change is easy because the number of states of the slave sequencer only needs to be linearly increased. In addition, the data packet for temporarily storing the data in the response packet has more than the number of TIDs allocated to the device, and the buffer ID is included in the requester ID information to issue the bus request, and the response packet Even if the arrival order of is reversed, the data can be delivered in the correct order to the bus requester side.

[Brief description of drawings]

FIG. 1 is a block diagram of a DMA transfer control device.

FIG. 2 is a configuration block diagram of a response packet processing circuit.

FIG. 3 is a configuration block diagram of a request packet processing circuit.

FIG. 4 is a configuration block diagram of a read controller and a write controller.

FIG. 5 is a state transition diagram of a sequencer inside a read controller and a write controller.

FIG. 6 is a timing chart of the packet control circuit when bus requests are received in the order of read, write, and read.

[Explanation of symbols]

100 ... DMA transfer control device 101 ... Split bus 102 ... Bus interface circuit 103 ... Bus request signal 104 ... Signal that specifies request packet attribute 105 ... Bus grant signal 106 ... Internal data bus 107 ... Response packet data valid signal 108 ... Transaction ID value 110 of response packet ... Response packet processing circuit 111 ... Request packet processing circuit 112 ... Response data buffer for read transaction 114 ... Tag ID value of bus requester 115 ... Bus grant signal for read controller 116 ... Bus request arbiter control Circuit 117 ... Bundle signal composed of 117A and 117B 117A ... Response data valid signal to read controller A 117B ... Response data valid signal to read controller B 118 ... Bus grant signal to write controller 119 ... Packet control circuit 120 ... Read request bus request Star 121 ... Read request signal 122 ... Grant signal for read request 123 ... Read controller A 124 ... Read controller B 125 ... Bundle signal consisting of 125A and 125B 125A ... The bus request serviced by read controller A must be at the head of the request queue Signal 125B ... A signal indicating that the bus request serviced by read controller B is at the head of the request queue 126 ... 126A, a bundle signal consisting of 126B 126A ... Read controller start request signal 126B ... Read controller B to read controller A Read controller start request signal 127 ... Bundle signal composed of 127A and 127B 127A ... Read controller A ready signal 127B ... Read controller B ready signal 128 ... Tag ID value stored in read controller (tag ID value of request packet and response) (Consisting of the tag ID value of the packet) 129 Operation timing signal for read request bus requester 130 ... Write request bus requester 131 ... Write request signal 132 ... Grant signal for write request 133 ... Write controller 134 ... Signal indicating that the bus request serviced by the write controller is at the head of the request queue 135 ... Data valid signal for data of write request packet 136 ... Write controller ready signal 137 ... Write controller start request signal 138 ... Tag ID value stored in write controller 139 ... Operation timing signal for write request bus requester 201, 202 , 203 ... Comparator 204, 205 ... AND circuit 206 ... ID value of DMA transfer control device 207 ... Signal indicating that response packet is addressed to DMA transfer control device 208 ... TID included in request packet serviced by read controller A LSB value of 209 ... LSB value of the TID included in the request packet serviced by the tracker B 210, 211 ... Match output signal of the comparator 213 ... Signal indicating that the response packet serviced by the read controller A is valid 214 ... Serviced by the read controller B A signal indicating that the response packet is valid 215 ... Decoder 301 ... Encoder 302 ... Decoder 303 ... Bus request control circuit 304 ... Bus request queue control circuit 305 ... OR circuit 401 ... State machine 402 of the master sequencer in the read controller A ... State machine of slave sequencer in read controller A 403 ... Logic other than sequencer in read controller A 404 ... Request packet set signal that read controller A services 405 ... Bus grant signal to read controller A 406 ... Read controller A services Response packet Reception processing timing signal 407 ... Tag ID value corresponding to request packet serviced by read controller A 408 ... Tag ID value corresponding to response packet serviced by read controller A 411 ... State machine 412 of master sequencer in read controller B ... State machine of slave sequencer in read controller B 413 ... Logic other than sequencer in read controller B 414 ... Set signal of request packet serviced by read controller B 415 ... Bus grant signal to read controller B 416 ... Serviced by read controller B Response packet reception processing timing signal 417 ... Tag ID value corresponding to request packet serviced by read controller B 418 ... Tag ID value corresponding to response packet serviced by read controller B 421 ... in write controller State machine of master sequencer 422… State machine of slave sequencer in write controller 423… Logic other than sequencer in write controller 424… Set signal of request packet serviced by write controller 425… Request packet data valid signal serviced by write controller 426 ... Bus grant signal to write controller 427 ... Last timing signal of request packet data serviced by write controller 428 ... Tag ID value stored in write controller 500 ... State transition diagram of master sequencer in read controller 510 ... Write State transition diagram of the master sequencer in the controller 520 ... State transition diagram of the slave sequencer 501 ... Idle state of the master sequencer in the read controller 502 ... Waiting state for master PLC sequencer in read controller 503… Waiting state for master sequencer in write controller 511… Waiting state for master sequencer in write controller 512… Waiting state for master sequencer in write controller 513… Within write controller Master sequencer waits for last data 521… Slave sequencer is idle 522… Slave sequencer is at the top of the bus grant queue 523… Slave sequencer is second in the bus grant queue 524… Slave sequencer is the bus grant The third in the queue

Claims (6)

[Claims] 1. A first means for continuously outputting a read request and a write request issued by a plurality of bus requesters connected to an I / O device connected to the bus to the bus, and the read request. A second means for writing response data arriving from the bus to the bus requester to the bus requester in parallel with a bus transaction operation for the next read request or write request.
A transfer control device. 2. A bus request arbiter control circuit for arbitrating and serializing bus requests asynchronously output by a plurality of bus requesters in the first means, wherein the bus request arbiter control circuit receives the bus requests. , A request queue control circuit for storing the bus request order of a bus requester that has issued a bus request that has not yet been accepted by the bus, and simultaneously services read request bus transactions or write request bus transactions that are output to the bus A plurality of sequence control circuits, a bus request control circuit for asserting a bus request signal according to a bus request from the bus request arbiter control circuit, and a request packet control for generating a packet to be output to the bus in advance Has a circuit, bus request The bus request signal is asserted by the bus request arbitrated by the arbiter control circuit, and at the same time, the sequence control circuit that services the bus request is placed in the waiting state for the bus grant, and is positioned at the head of the request queue by asserting the bus grant signal. 6. A sequence control circuit that services a bus request is specified, and the request packet control circuit outputs the bus request packet to the bus in accordance with an instruction from the sequence control circuit that has obtained the right to use the bus. DMA described in 1
Transfer control device. 3. In the second means, a plurality of sequence control circuits for servicing a read bus transaction or a write bus transaction simultaneously performed on the bus, and the response packet are serviced from the contents of the response packet. A sequence control circuit that has a response packet processing circuit for specifying the sequence control circuit to be processed, specifies the sequence control circuit that should service the response packet at the same time as receiving the response packet, and waits for the response packet. 2. The DMA transfer control device according to claim 1, wherein writing is performed to a bus requester expecting the response packet according to an instruction of the circuit. 4. A sequence control circuit for servicing the read request receives first request identification information about the bus requester that issued the read request, and then receives a request acceptance permission signal for the read request and then responds to the next read request request. Holds the memory until the request acceptance permission signal is received,
Storage of the second identification information regarding the bus requester necessary for writing the response data to the read request to the bus requester during the period from the reception of the bus grant signal for the read request to the reception of the bus grant signal for the next read request. At the same time as the arrival of the response data corresponding to the read request, the sequence control circuit that should service the read bus transaction is transited to the state where the next read request can be accepted, and the response data is written to the device and the next read is performed. 4. The DMA transfer control device according to claim 3, wherein requests are received overlappingly in the same sequence control circuit. 5. The sequence control circuit according to claim 1, wherein if a read request is issued from a bus requester, the read bus transaction is controlled, and if the write request is issued, the write bus transaction is controlled. DMA transfer controller. 6. A request queue control circuit is distributed in the sequence control circuit, and whether or not a bus grant signal arriving from a bus is a bus grant signal for its own sequence control circuit is individually determined by each sequence control circuit. The DMA transfer control device according to claim 2, wherein the determination is made.