JPS58211269A - Multi-processor system - Google Patents

Abstract

PURPOSE:To process a program at a high speed, and also to protect exactly an internal memory, by providing a buffer control part having a buffer memory. CONSTITUTION:A processor 111 fetches a program from a discrete memory 121 through an internal bus 131, executes the processing, and stores a processed data in the memory 121. Subsequently, when this data is outputted to an I/O device 5, the processor 111 starts a transfer control part in a buffer control part 151, and transfers the data in the memory 121 to a buffer memory in the control part 151. Thereafer, an I/O control part 4 is made to fetch the data of the buffer memory through a common but adaptor 141. When all these data are inputted, the control part 4 outputs a data to the device 5. On the other hand, when the data is read from the device 5 and it is processed, the processor 111 starts the prescribed device 4 and transfers the data of the device 5 to the buffer memory. Thereafter, this data is transferred to the memory 121.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for configuring processor modules in a multiprocessor system.

In general, in a multi-processor system, even if the number of processor modules increases, the amount of data processed by each unit does not decrease, and the contents of the program or data may be destroyed due to a runaway processor module, etc. I hope so.

1 to 4 are block diagrams showing conventional examples of such systems.

In these figures, 1 (11 to 1n) is a processor module, 2 is a common memory, 3 is a common bus, and 4 (41 to 1n) is a processor module.
4. TI) is input/output control pi (IOC), 5 (51 to 5
．． TI) is an input/output device r9 (Ilo). That is, each processor module 1 fi shown in FIG.

Data is exchanged with the memory 2 via the 10C4 common bus 3. Therefore, in the configuration shown in FIG. 1, the number of installed processor modules 1 is limited due to the data transfer bottleneck or transfer capacity of the common bus 3, and since the memory 2 is shared, the program memory and data contents are There is a problem that there is a risk that it may be destroyed by the processor module l or l0C4.

On the other hand, Figure 2 shows a multiprocessor system that is an improved version of the configuration shown in Figure 1.The difference from Figure 1 is that each processor module has an individual (internal) memory
o) and an internal bus IB (IBI-I) 3n). Tsumashi, Processor P (P1
~Pn) reads the siprogram from the individual memory IM via the internal bus IB and executes processing, and stores the processed data in the individual memory IJIM or the common memory 2.

The l0C4 exchanges data with the individual memory IM or the common memory 2 via the common bus 3. Therefore, according to the configuration of FIG. 2, the individual memory IM and the internal bus I
Although the data transfer neck of common bus 3 can be solved by the effect with B, other processor remodules 1 or l0
The problem that the individual memo IJIM may be destroyed due to runaway of C4 etc. has not been solved at all.

On the other hand, FIGS. 3 and 4 were separately devised by the applicant, and are each a multiprocessor system that is a further improvement of FIG. 2.

That is, what is shown in FIG.
1 to Pn)
) in the individual memories IM (IMl~■Mo) and cha, i,
By providing two memory channels c (C1 to Cn) and connecting these to each other via an internal bus 113 (IB1-IBn), the individual memories are prevented from being directly accessed via the common bus 7. In addition to providing protection, the data transfer bottleneck described above is eliminated by not reducing the processing capacity of each processor.

On the other hand, in the configuration shown in FIG. 4, each processor module 1 connected to the common bus 3 has a program bus PB (P
B1~PBn) and data bus DB (DB, ~DB,...
), program memory (individual memory) PM (PM1 to PMn) is connected to the bus, and data memory (individual memory 'JT) M (L
)Ml to DMn) are respectively connected to the data bus to prevent the program (memory) from being destroyed even if a temporary error that has passed through the data bus occurs, and also to A data transfer channel C (C1 to Cn) is connected to the common bus, and transfer of data between the data memory DM and the common memory 2 and input/output control device 4 connected to the common bus 3 is performed via the channel. By doing so, the processing capacity of each processor P (P1 to Pn) is not reduced. In addition, in the same figure, DA (D
AI to DAn) tCA (CA1 to CAn) indicate a data bus adapter and a common bus adapter for the processor P to access the data bus DM and the common bus 3, respectively. However, according to the configuration of FIG. 3 or 4, when exchanging data between the input/output control device 10C and the processor module 1, the common memory 2 must be relayed or the buffer memory in the IOC must be used. It takes a long time to exchange data
The disadvantage is that the configuration of IOCs installed in large numbers is complex and expensive, and that problems remain in terms of economy.

The present invention has been made in view of these points, and is a multiprocessor system that is capable of high-speed program processing and that ensures protection of programs or program memory.
In particular, the object is to provide a configuration method for the processor module.

Its features include a common bus adapter that allows the processor to access each unit connected to the common bus, such as a common memory and input/output control device, and a common bus and internal bus for each processor module that makes up the multiprocessor system. Buffer memory that can be accessed from both (
By providing a dual port memory) and a buffer control unit having a data transfer control function between the buffer memory and the internal memory, the internal memory can be prevented from being directly accessed from the common bus, and each processor module can be It is possible to operate independently of the operation of the input control device or other processor modules so that its program processing ability is not degraded, and furthermore, by using the buffer memory, it is possible to operate independently of the operation of the input control device or other processor modules. The purpose of this invention is to perform data transfer without intervening a predetermined memory, thereby shortening the time required for data transfer by a factor of 5 to 5.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 5 is a block diagram showing an embodiment of the present invention, and FIG. 6 is a block diagram showing the detailed configuration of the buffer control section in FIG. 5. That is, FIG. 5 is an improved version of FIG. 3, and the difference from FIG. 3 is that the buffer controller 15 having a buffer memory
(151 to 15n) and a memory (not shown) installed in the common memory 2 or l0CJ during data transfer
This eliminates the need for

Its operation will be explained. Processor 11 (111~
11n) takes out a program from the individual memory 12 (12, to 12n) via the internal bus 13 (131 to 13n), executes the process, and stores the processed data in the individual memory 1.
Stored within 2. Then, when outputting this data to l105, the processor 11 outputs the buffer control unit 15 (
151 to 15n) is activated to transfer the data in the individual memory 12 to the buffer memory in the buffer control unit 15. After that, the common bus adapter 14 (
14, ~ 14n), common memory 2 or l0C
By accessing registers (not shown) in 4, l0
It communicates with C4 and causes l0C4 to send the data in the buffer memory in the buffer control unit 15 to C4. l0C4i When all this data is taken in, it outputs the data to l105.

On the other hand, when reading and processing the data from l105, the processor 11 activates a predetermined l0C4 via the common bus adapter 14, and transfers the data from l105 to the buffer memory in the buffer control unit 15. After that,
The transfer control unit in the buffer control unit 15 is activated to transfer data to the individual memory 12.

Next, details of the buffer control section will be explained with reference to FIG. 6. In the same figure, 1500 buffer memories,
1501 is an address selection gate, which is a so-called dual port that can be accessed from two buses, the common bus 3 and the internal bus 13.

1502 input data selection gates, 1503 output data buffer to common bus 3, 150'4 internal bus 13
1505 is a register for setting the start address of the individual memory 12, 1506 is a register for setting the start address of the H buffer memory 1500, 1507 is an address counter that is incremented by 1 each time data transfer is executed, 1508 1509 is an adder that adds the start address of the memory and the value of the address counter, 1510 is an address buffer that outputs the address of the individual memory, and 1511 is used to set the number of words of data to be transferred when data is transferred. A transfer word counter 1512 is incremented by 1 every time the transfer is executed, and generates a transfer end signal when it becomes zero.
and a control circuit that interfaces with the common bus 3 and executes data transfer control. In addition, buffer memory 1
Access to 500 is via two common buses 3 and internal buses 13.
This traffic control is done by the control circuit 1512.
For example, it is executed on a first-come, first-served basis. When an access from the common bus 3 is executed, signals G2 and G4 are valid, signals MS and WE are valid for a write operation, and signals M S , ! are valid for a read operation. : Each operation is executed by appropriately controlling G6. That is, the access operation is executed completely independently of the components 1504 to 1511.

Here, the operation of transferring data in the individual memory 12 to the buffer memory 1500 will be described as an example. The processor 11 sets the start address of the individual memory 12 in a register 1505 and the start address of the buffer memory 1500 in a register 1506 via the internal bus 13, respectively. Then, after setting the number of words of the transfer data in the transfer word counter 1511, a command to start the transfer control section is input to the control circuit 1512 via the internal bus 13.

When the control circuit 1512 obtains the availability of the internal bus 130 and the dual port memory (buffer memory), it enables the signal G7, sends the memory address from the address buffer 1510 onto the internal bus 13, and transfers the memory address to the individual memory 1.
2 read operation is executed. Individual memo January 2nd WRI
B l, the data on internal bus 13 is transferred to signals G1 and 63.
And set MS and WE to 1 and buffer memory 150
At the same time as writing to 0, the control circuit 1512
The interface operation with the buffer memory 15 is completed, and the buffer memory 15 is
Release the used c of 00, and further address counter 15.
07 by -H1 and transfer word number counter 1511 by -1.

This transfer order one operation is repeatedly executed until the contents of the transfer word counter become zero. Buffer memory 15
For the operation of transferring data 00 to the individual memory 12, instead of disabling the write signal WE of the buffer memory 1500, the output data buffer 1504 to the content bus 13 of the buffer memory is operated by enabling the signal G5. The only difference is that the other points are the same as above. In this way, since the buffer control unit 15 has an internal buffer memory, it is possible to directly transfer data between the buffer memory 1500 and l0C4 without going through other memory means, and it is also possible to perform transfer control. Since there is a section,
Data transfer between the individual memory 12 and the buffer memory 1500 is all automatically performed by a startup command from the processor 11.

FIG. 7 is a block diagram showing another embodiment of the invention, FIG. 8 is a block diagram showing still another embodiment of the invention, and FIG. 9 shows a detailed configuration of the buffer control section in FIG. 8. Block Diagrams FIGS. 10 and 11 are block diagrams showing another embodiment of the present invention.

That is, FIG. 7 shows a modification of FIG.
The difference from the diagram is that a plurality (k) of buffer control units 15 are provided. As a result, when there are multiple Ilo units to be serviced by the processor 11, if the buffer control unit 15 is prepared for each Ilo, the buffer control unit 15 (1511 to 15n) can be controlled by the program of the processor 11.
Since there is no need to control the usage of k), there are advantages in that the program is simple and the processing time can be shortened.

Note that as the number of buffer control units 15 increases, the amount of hardware increases accordingly.
(Large-scale integrated circuit) etc., this problem can be solved.

Moreover, FIG. 8 is an improvement plan of FIG. 4, and the difference from FIG. 4 is that a buffer control section 15 having a buffer memory is provided, and data can be transferred without going through the memory installed in the memory 2 or 10C4. This is what I did in step 5. In this configuration, compared to the embodiment shown in FIG. 5, the internal bus is separated into a program execution bus 13 and a data transfer bus 17.
There is no risk of destruction of the contents. Another advantage is that the program processing operation of the processor 11 is not affected by the data transfer operation of the 18% buffer memory, such as having to wait.

FIG. 9 shows a detailed configuration of the buffer control unit 15 in FIG. 8. The difference from that in FIG. Access from the processor 11 is configured to be executed via the program node 13. Note that the constituent elements are exactly the same as those in FIG. 6, and the operation is also the same as described in FIG.

Furthermore, FIG. 10 shows a modification of FIG.
The difference from the figure is that a plurality (k) of buffer control units 15 are prepared.
It is similar to that in the figure.

Further, FIG. 11 shows a configuration in which a buffer control section 15 is provided in FIG. 4, and the configuration and operation of the buffer control section 15 are the same as those described above. Note that among the components of the buffer control unit 15, the data transfer function from the data memory 18 to the buffer memory (in the buffer control unit 15) may be deleted. Also, from the block transfer channel 19 (191 to 19n), data memory 18←common memory 2 or l0C4
The data transfer function to the buffer memory (not shown) can be deleted. Note that the configuration shown in FIG. 11 has the advantage that data can be transferred directly from the processor module II to the processor module II.

Of course, a configuration in which a block transfer channel is added to the configuration shown in FIG. 8 is also possible. Furthermore, it is of course possible to provide the configuration shown in FIG. 8 with a plurality of block transfer channels and the configuration shown in FIG. This is the same as in the case of FIGS. 7 and 11.

As described above, according to the present invention, a common bus adapter for the processor 11 to communicate with other processor modules or the L0C4 and a buffer memory having a dual port configuration for data exchange are provided, and the common bus 3 side Since the internal memory (individual memory and data memory) cannot be accessed directly, the internal memory cannot be accidentally destroyed. Further, since the processor module Ic can operate independently of the operation of the 4th processor module 1 or l0C4, the program processing performance does not deteriorate even if the number of processor modules increases. Furthermore, when exchanging data between the l0C4 and the processor module, the common memory 2 and the l0C4 are
Since buffer memory in 0C4 is not required, IOC
The configuration can be as simple as the conventional one, and has the effect of shortening the time required for data exchange. Also, the first
In the configuration shown in FIG. 1, in which a buffer control unit and a block transfer channel are provided, data exchange between the processor modules 1 can be performed via IP' access without going through the common memory 2 or the like.

In addition, as mentioned above, data transfer between the individual memory, the data memory and the buffer memory, the buffer memory #common memory or the buffer memory within 1IOc, and the I/O from the individual memory or L data memory via the common bus.
When transferring data to the buffer memory in the OC, an error-correctable code such as a cyclic redundancy check ((, TLC) is applied to each byte or word data, and the data to be written to each memory is checked by a byte or word. By adopting a block data check method (if necessary, please refer to Japanese Patent Application No. 56-208195) in which data is checked in units, it is possible to achieve complete data fragmentation.

Furthermore, in a configuration in which a plurality of buffer control units are provided, or in a configuration in which a plurality of buffer control units and block transfer channels are provided (d), the processor program controls the cipher control unit and the use of the block transfer channel. Since there is no need to run the program over and over again, the program becomes simpler and the processing time is shortened.

Although the present invention is applicable to multiprocessor systems in general, it goes without saying that it can also be applied to systems in which IOCs and the like are configured with microprocessors.

[Brief explanation of drawings]

FIGS. 1 to 4 are block diagrams showing a conventional multiprocessor system, FIG. 5 is a block diagram showing an embodiment of the present invention, and FIG. 6 is a block diagram showing the detailed configuration of the buffer control section in FIG. 5. , FIG. 7 is a block diagram showing another embodiment of the invention, FIG. 8 is a block diagram showing still another embodiment of the invention, and FIG. 9 shows a detailed configuration of the buffer control section of FIG. 8. FIGS. 10 and 11 are block diagrams showing other embodiments of the present invention. Code explanation 1 (1, ~1n)...Processor module,
2...Common memory, 3...Common bus,
4 (41~4m) Input/output control device (IOC)
), 5 (51~5□n)... Crowd, ? [[(I
lo l 11, P... Processor module, 12', 18. IM, PM, I)M...
- Individual memory (internal memory), 13, 17. IB, pH
, I) B... Internal bus, 14. CA...
・Common path adapter, 15 (15tt~15nk)-・
...Buffer control unit, 16. DA...Data bus adapter, 19. C... Channel, 15
00...Buffer memory, 1501...
・Address selection gate, 1502...Input data selection gate, 1503.1504...Data buffer, 1505.1506...Start address register, 1507... address counter,
1508.1509... Adder, 1510...
... Address buffer, 1511 ... Transfer n74 number counter, 1! 'i12... Control circuit agent Patent attorney Akio Namiki Agent Patent attorney Kiyoshi Matsuzaki Figure 1 Figure 2 Figure 3 Figure 10 Figure 11

Claims (1)

[Scope of Claims] 1) A multiprocessor system in which a common memory, a plurality of processor modules, and a plurality of input/output control devices that control input/output devices are arranged in parallel on a common bus, wherein each processor The module includes an individual memory, a processor that executes predetermined processing based on programs and data stored in the individual memory or the common memory, and the processor is connected to the common memory and a common bus such as an input/output control device. A common bus adapter for accessing each unit, a buffer memory and a buffer control section having a data transfer control function between the buffer memory and the individual memory are connected to each other to an internal bus, and the The buffer memory v/l'in can be accessed from both an internal bus and a common bus, and data exchange between each unit and the individual memory is performed via the buffer control section. multiprocessor system. 2. The multiprocessor system according to claim 1, wherein each processor module includes a plurality of buffer control units. 3) In the multiprocessor system according to claim 1, the internal bus is connected to a data bus to which an individual memory for data storage mainly stores data, and the processor and a program mainly stores a program. A program bus is connected to an individual memory for storage, and the buffer control unit is connected to a common bus. Connect to each of the data bus and program bus,
A multiprocessor system characterized in that the processor accesses the data memory via a data bus adapter. 4) 4? 4. A multiprocessor system according to claim 3, characterized in that a plurality of said buffer control units are provided. 5) In the multiprocessor system according to claim 3, a block transfer channel connected to each of the common node, a data bus, and a program bus is arranged in parallel with the buffer control unit, and the data memory Data transfer from the unit to the buffer memory is mainly performed by a block transfer channel, and data transfer from each unit connected to the common bus to the data memory is performed by a buffer control section. processor system. 6) The multiprocessor system according to claim 5, characterized in that a plurality of buffer control units and a plurality of block transfer channels are provided.