JPS5856172A - Data processing system - Google Patents

Abstract

PURPOSE:To easily constitute a multiprocessing system by using plural data processing units having input and data ports differing in data width in combination, and only adding less hardware. CONSTITUTION:The control part 4 of a memory 3 connected to an external data bus 7 is provided with a multiplexer circuit 6 with a read modified write function. Then, a data processing unit 1 having an input and output port having data width less than the bus width of the bus 7, when reading data out of the memory, uses a multiplexer circuit 5 in the unit 1.For writing to the memory 3, the unit 1 uses the multiplexer circuit 6 in the memory control part 4 to write data through read modified write operation. A micro-processor unit 2 has an input and output port having the same width with the bus 7.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing system, and particularly to a multiprocessing system in which a plurality of data processing units having input/output data ports having different data widths are combined,
The present invention relates to a data processing system in which messages are shared via a common external data bus.

Conventionally, when configuring a multiprocessing system using, for example, a microprocessor, a data processing unit group with a data width of 1 byte or 2 bytes and a data processing unit group such as a slave memory and an I10 device are used. By connecting them via a common bus, a multiprocessing system was constructed. An example of the configuration of such a single multiprocessing system is shown in FIG. In FIG. 1, MPU0.
MPU1 is an i microprocessor unit,
The U0, MPUI, memory, and I10 devices are connected by control signal paths, address buses, and data buses. In general, the MPU0° MPUI, memory, and engineering/Φ device have the same input/output data port path width.

By the way, there has not been a multiprocessor system in the past in which data processing unit groups having different data widths directly transfer data to other data processing unit groups without an interface section. On the other hand, in recent years, various microprocessors with different bit widths have been manufactured, and due to various factors, there has been a desire to combine these microprocessors with different bit widths to configure a multiprocessor system. .

For example, one microprocessor was initially used to configure a single-processor system, but later, additional functionality was required, which required the use of a microprocessor with a different bit width than the original microprocessor. This is the case. In such a case, when attempting to configure a multiprocessor system, a special adapter circuit is required, resulting in a complicated configuration and a large amount of hardware.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to easily configure a multiprocessing system consisting of a plurality of data processing unit groups having different data widths. A data processing unit is provided with a plurality of data processing units having input/output data boats with different data widths between them and the data bus, and has input/output data boats with a data width smaller than the path width of the external data bus. A multiplexer circuit is provided, a multiplexer circuit having a read/modify/write function is provided in a control section of a memory connected to the external data bus, and an input/output port having a data width smaller than the path width of the external data bus is provided. When the data processing unit executes a read operation to the memory, a multiplexer circuit in the data processing unit is used to read data, and when the data processing unit executes a write operation to the memory, the multiplexer circuit in the memory control unit is used to read data. It is characterized by using a multiplexer circuit to write data through read-modify-write operations.

The present invention will be explained below with reference to the drawings.

FIG. 2 is a diagram of a multiprocessing system according to an embodiment of the present invention. In the figure, 1 is a microprocessor unit whose input/output data boat has a data width of 1 byte, and 2 is a microprocessor unit whose input/output data boat has a data width of 1 byte. is a 2-byte microprocessor unit, 3 is a memory, 4 is a memory control section, 5 is a multiplexer circuit that can be provided with a miter cost processor unit IK, and 6 is a multiplexer circuit that has read/modify/write functions that can be received by the memory control section 4. , γ is a common path (system path) and has a width of 2 bytes. Hiko, the illustration of the I/6 device is omitted.

FIG. 3 is a 1-bit configuration diagram of the multiplexer circuit 5 in the embodiment, in which 10 is a tri-state gate), 11 and 12 are receive buffer gates, 13 is a not gate, and 14 and 15 are AND gate, 16 is an OR gate, DOOO is the Oth bit output data line, DiQ
Q is the 0th bit input data line, CBOO and CBOB
indicate the 0th bit and the 8th bit in the external data bus, respectively. External data bus is CBoo-CBO
The first byte information line consisting of 7 and CBO3 to CB1
Since the circuit shown in FIG. 3 is related to the data of the O-th bit, the information line of the second byte consisting of 5 is connected to the CBOO bit at the head of the first byte and
Regarding the multipress circuit corresponding to the head of the byte, C
The BOI and CBO9 are configured to be connected.

The operation of the embodiment is as follows.

(1) Microprocessor unit) 2 (MPU
For memory access operations from I).

In this case, the data width of the input/output port of the microprocessor unit 2, the common path 7, and the memory control unit 4 are
Since the data widths of each memory 3 are the same, conventional read/write operations are performed.

(21 microprocessor units) 1 (MPUO>
For memory read operations from .

In the case of a memory read operation, two bytes are read from the memory side, so the multiplexer circuit 5 in the microprocessor unit 1 takes in one of the bytes.

For example, when taking in the lower CBOO-CBO7, the data selection signal shown in FIG. In addition, when taking in the upper CBO3 to CB15, the data selection signal shown in FIG.
Then, the AND gate 14 is closed, the AND gate 15 is opened, and the internal pressure of the T microprocessor unit l is drawn into the CBO3 to CB15 sides.

In the case of a memory read operation from the microprocessor unit 1 (MPUo), the TrI 5 shown in FIG.
Under the control of the tate ( ) ry state control signal, the output of the tri-state gate 10 is held in a high impedance state to prevent the illustrated DOOO signal from being output to the common path.

(3) Microprocessor Uniy) 1 (MP
For memory write operations from UQ).

During write operation, Trl 811te shown in Figure 3
()? (state) By controlling the control signal,
Tri-state gate 10 becomes conductive, and one byte of write data DOOO-D007 is transferred to memory control unit 4 through CBGO-CB07 of the common path.

Here, the memory control unit 4 performs read/after processing.
Operates in light mode. That is, 2-byte data is read from memory 3, 1-byte data to be rewritten without changing it, and 1-byte data to be written sent from mitertube processor 1 (MPUO) are read.・Synthesized by multiplexer circuit 6 with modify write function,
After that, it is written into the memory 3. At this time, the bytes changed are microprocessor unit l (MPU
It is determined by the address information sent from O).

In order to improve the reliability of the transferred data, a parity bit is provided on the path, and a parity check circuit is provided in both the microprocessor unit 1.2 and the memory control section 4 to check the parity attached to the transferred data. All you have to do is K.

Furthermore, in order to improve the reliability of the data in the memory 3, it is sufficient to provide an error correction circuit section. , 2 methods of making money can be considered, and it is possible to adopt either method as needed.

As explained above, according to the present invention, it is possible to easily and economically configure a multiprocessing system consisting of a plurality of data processing unit groups with different data widths by simply adding a small amount of hardware. is extremely large.

[Brief explanation of the drawing]

FIG. 1 is a configuration example of a conventional multiprocessing system, FIG. 2 is a block diagram of a multiprocessing system according to an embodiment of the present invention, and FIG. 3 is a configuration diagram of a multiplexer circuit in an embodiment. In Figure 2, 1 and 2 are microprocessor units, and 3 is a memo! J, 4ti memory control section, 5 and 6
is a multiplexer circuit, and 7 is a common node.

Claims (1)

[Claims] If multiple data processing units are provided with input/output data ports having different data widths between them and a commonly used external data bus, the input/output data width will be smaller than the path width of the external data bus by 1%. A multiplexer circuit is provided in a data processing unit having a data port, and a multiplexer circuit having a read/modify/write function is provided in a control section of a memory connected to the external data bus. When a data processing unit having an input/output port with a data width smaller than the data width performs a read operation to the memory, a multiplexer circuit in the data processing unit is used to read the data, and the data processing unit reads the data from the memory. A data processing system characterized in that when executing a write operation to the memory controller, a multiplexer circuit in the memory control section is used to write data by a read-modify-write operation.