JPS60124755A - Information processing unit - Google Patents

Abstract

PURPOSE:To improve the processing speed by providing a means supported by a cache memory to also a common storage device to run the program in the common storage device at the same performance of the program in the main storage. CONSTITUTION:A write signal fed from a bus 1 to the common storage device 3 is fed to an address converting circuit 120, where the address is converted into an internal address from an external address. Then the address is decided by an area deciding circuit 100 via a multiplexer 130 and when it is decided as a data area 220, and fed to a storage circuit 200 where a prescribed write is performed when the address is decided as a data area 220. When the area of the circuit 100 is decided as a program run area 210, an reverse conversion command signal is fed from the circuit 100 to an address reversed conversion circuit 111. Thus, the address is converted reversely from the inner address to the external address, fed to a bus 2 so as to start a write bus cycle. As a result, the coincidence between the contents of the cache memory and the contents of the area 210 is guaranteed, the cache memory is supported even to the storage device 3, allowing to improe the processing speed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to an information processing apparatus, and more particularly to an information processing apparatus equipped with a storage device shared by a central processing unit having a cache-memo IJ connected to each individual bus. Regarding.

(Prior Art) Conventionally, in information processing devices that share a storage device connectable to multiple buses and configure a multiprocessor system, the shared storage device cannot obtain cache memory support for the following reasons. do not have. The cache memory holds a copy of a portion of the storage device that the central processing unit reads into the storage device. When the gassy memory has data at the respected address of i-7, it has the role of transferring the data to the central processing unit at high speed in place of the main memory.

Therefore, the data held by the cache memory must always be the same as the data stored in the storage device. When data stored in the cache memory is written to a location in the storage device having the same address as the address occupied in the storage device, the corresponding data in the cache memory is also updated at the same time.

However, when a multiprocessor system is configured with such conventional information processing devices and the cache memory supports a shared storage device, if the contents of the shared storage device are changed from one processor system, the other processor system Because no write bus cycles are initiated for the bus, the cache memory connected to the other processor's bus is unaware of the data changes, and the contents of the shared storage device and the cache memory of the other processor's A discrepancy occurs with the content.

For this reason, in conventional information processing devices, the cache memory does not support the address area of the shared storage device.
A read request always reads data from the shared storage device. Therefore, when a program runs on a shared storage device, there is a drawback that performance deteriorates.

(Objective of the Invention) The object of the present invention is to provide a means by which a cache memory can support a shared storage device, so that a program can run on the shared storage device with the same performance as a program on the main memory, and the processing speed is increased. The purpose of the present invention is to provide an information processing device that significantly speeds up the processing.

(Structure of the Invention) The device of the present invention is an information processing device including a storage device shared by a plurality of central processing units each having a cache memory connected to a separate bus. an address conversion means for converting an external address of any - central processing unit of the plurality of corresponding central processing units to an external address of any other central processing unit, from the - central processing unit to the shared storage device; and write bus cycle activation means for activating the address conversion means to activate a write bus cycle on the bus to which the other central processing unit is connected when there is a write bus cycle.

(Example) Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The information processing device in FIG. 1 is a central processing unit 1 involved in a bus 1.
1, a cache memory 12, and a shared storage space 3 shared by the storage system 1 and the cache memory 12.

FIG. 2 shows a detailed block diagram of the shared storage device 3 used in FIG. 1. The shared storage device 3 in FIG. 2 is a storage circuit 2 consisting of a program running area 210 and a data area 220.
00, an area determination circuit 100 that determines which area of the memory circuit 200 the write is to be made and generates an inverse conversion command signal when writing to the program running area, and a write The write signal in the write signal is supplied with the command, the data to be written, and the address to be written in the common storage device 3 as seen from each central processing unit (these three pieces of information are hereinafter collectively referred to as the write signal). The address to be loaded is calculated from the address of the common storage device 3 seen from each central processing unit (hereinafter referred to as an external address in the claims) to the real address of the common storage device (hereinafter referred to as an internal address in the claims). Address conversion circuits 120 and 121 convert the addresses into addresses (referred to as addresses), and internal addresses in response to the supply of the input signal and the reverse conversion command signal. It is composed of address inverse conversion circuits 110 and 111 that generate control signals for inhibiting the operation tl of the address conversion circuit corresponding to the rape, and a multiplexer 130 that selects one of the two supplied write signals.

The program running area 210 of the memory circuit 200 is an area for storing programs for each central processing unit, data operated by the programs, and data changed by other thread central processing units. Each central processing unit manipulates data in the area, interrupts another central processing unit, and the central processing unit that receives the interrupt reads the data, making it possible to transmit information.

Furthermore, the data area 220 of the memory circuit 200 is mainly a DMA
This is an area for storing data that is handled by transfer and not directly changed by the program, and data that is used only by the central processing unit itself and is used infrequently.

Although the shared storage device 3 can naturally be read, reading is not directly related to the present invention, so FIG. 2 shows only the main parts related to writing.

Next, the operation of this embodiment will be explained with reference to FIGS. 1 and 2.

When the first system issues a write signal to the shared storage device 3 on the bus 1, the cache memory 12 monitors the write bus cycle and the data stored in the cache memory 12 is transferred to the shared storage device 3. Check Wd to see if it will be written to the same address as the internal address it was occupying. When it is determined that the write is to the same address, the corresponding data in the cache memory 12 is updated using the write data on the bus 1. This operation is similar to that of a conventional information processing device.

The write signal supplied from the bus 1 to the shared storage device 3 is supplied to an address translation circuit 120, where the address in the write signal is translated from an external address to an internal address, and a multiplexer 130 and other systems address inverse translation. The signal is supplied to the circuit 111. The write signal is then selected by the multiplexer 130 and supplied to the area determination circuit 100 to determine whether the write signal is for the program running area 210 or the data area 220, and at the same time the 1 write signal is stored. circuit 200
A predetermined leveling process is performed.

When the determination by the area determination circuit 100 is based on an internal address, an inverse conversion command signal is supplied from the area determination circuit 100 to the address inverse conversion circuits 110 and 111. Here, only the address inverse conversion circuit 111 that has been supplied with the write signal and the inverse conversion command signal starts operating, inversely converts the address in the pledge signal from an internal address to an external address, and supplies it to the bus 2. Initiating a write bus cycle and I
Control signal 4 is sent to the address conversion circuit 121 of the tlr system.
01 is supplied to inhibit the address translation operation.

A cache-memory 22 connected to bus 2 monitors write bus cycles and a cache-memory 22
When it is determined that the data stored in the cache memory 22 has been written to the same address as the internal address occupied by the memory circuit 200, the corresponding data in the cache memory 22 is updated. This operation is the same as the conventional device as described above.

The above explanation is about the case where a write operation is performed in the first system, but when the write operation in the second system is also to the program running area 210, the carriage The updating of the data in the memory 12 is the same as described above, so the explanation will be omitted.

As described above, when a write signal is received for the program running area 210, a write pass cycle is activated for the threads of both systems, and the contents are updated when necessary in the cache memory of both threads. As a result, it is possible to guarantee that the contents of the cache memories 12 and 22 match the contents of the program running area 210 in the shared storage device 3, and the shared storage device 3 can support cache memos 2 and 22. The processing speed of the processing device can be significantly improved.

(Effects of the Invention) The present invention has the effect that the processing speed can be significantly increased by supporting the cache memory even for a shared storage device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a detailed block diagram of the shared storage device used in FIG. 1. 1.2...Bus, 3...Shared storage device, 11゜21...Central processing unit (CPU), 1
2.22...°°Cache Memo 1c 13,23
......Peripheral device control section, 14.24...
Main memory, 100...Area determination circuit, 110,1
11...Address inverse conversion circuit, 120.121
...address conversion circuit, 130...°° multiplexer, 200...memory circuit, 210...
...Program running area, 220...Data area, 300.301...Write signal, 4
00.401... Control signal.

Claims (1)

[Claims] (1) In an information processing device including a storage device shared by a plurality of central processing units each having a cache memory connected to a separate bus, the plurality of central processing units correspond to an internal address of the shared storage device. an address translation means for converting an external address of any central processing unit of - to an external address of any other central processing unit, when there is a write bus cycle from the central processing unit of said - to said shared storage device; An information processing device comprising write bus cycle activation means for activating the address conversion means to activate a write bus cycle on the bus to which the other central processing unit is connected. Claim 1, further comprising area determination means for determining that the bus cycle is a bus cycle and generating a conversion command signal, and operating a write bus cycle starting means in response to the conversion command signal. information processing equipment.