JPH05151104A - Data processor - Google Patents

Abstract

PURPOSE:To improve the RAG function by writing the data into a address translation buffer (TLB) after inverting a generated parity. CONSTITUTION:A bad parity (BadPT) bit 201 is set to a mode register 20. Then this bit 201 is set at 1 together with a PED 221, etc., set at 1 respectively so that the data on a parity error can be written into a TLB 12. Meanwhile a ZTBD address 210 showing the address of a directory part of the TLB 12 is stored in an address register 21 of the directory part. At the same time, the ZTBD data 220, the PED 221, the TLBC 222 and the PEC 223 are stored in a data register 22. Under such conditions, the parity of the data is generated and this parity bit is inverted when the bit 201 of the register 20 is equal to '1' together with the PED 221 equal to '1' respectively. Then the data are written into the directory part of the TLB 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device for processing various data.

[0002]

2. Description of the Related Art Conventionally, in a data processing device,
A virtual memory system is adopted. In such a data processing device, a semi-custom LSI called VBACS for performing bus control and memory address conversion.
When the main memory unit (MMU) is accessed from the CPU or I / O, the virtual address is converted into the real address (physical address) using this VBACS.

FIG. 2 shows the configuration of such a conventional data processing apparatus. In the figure, 1 is an MMU,
An address conversion table is stored in a part of the MMU 1. Reference numeral 2 is VBACS, which is a semi-custom L for controlling the bus and translating the memory address.
It is SI. Further, 3 is an address translation buffer memory (TLB) which is a buffer memory (cache memory) for the address translation table.

In the figure, 4 is a CPU for controlling the entire system, 5 is an SVP for writing / reading data to / from the TLB, and 6 is an I / O for inputting / outputting, VBACS2, CPU4, SVP5 and I / O6 are
It is connected via the AV bus 7.

In the above data processing device configuration, CP
U4 sends VBACS2 from I / O6 through AV bus 7.
Send a 32-bit address to. At this time, in the real address mode, the VBACS 2 passes the address on the AV bus 7 as it is to the MMU 1 as a memory address.

All memory accesses other than the above are accessed by virtual addresses. In this case, TLB3 is used. As a result of searching TLB3 by VBACS2,
When there is a hit, a physical address is created from this TLB3 data. On the other hand, when there is no hit (in the case of a miss hit), the address conversion table on the MMU 1 is looked up. When the target page word is found, this data is replaced with the data in the TLB 3.

The TLB 3 has 2 levels with 2 K entries, and the update date of each level is TLB.
Controlled by Round Robin (RR) within 3. The VBACS2 has a parity check function,
When there is a parity error in either one of the levels of LB3, the enable bit of that level is turned off and the TLB3 of that level is not used.

Here, the test of VBACS2 is SVP5.
When performing from SVP5 without taking the process of address translation
To VBACS2 from a predetermined command (WRITE BCU
By executing (REG etc.), the directory of TLB3,
Data can be written in each part of word and control. At this time, since the parity bit is generated in VBACS2, if the parity circuit operates correctly, the data having the correct parity bit is written in each part of TLB3.

[0009] However, TL can be set by VBACS2.
Wrong parity data cannot be written to B3, and therefore the operation of the parity check function cannot be confirmed.

[0010]

As described above, in the conventional data processing device, the data of the wrong parity cannot be written in the TLB, so that the operation check of the parity check function cannot be performed. .. However, in the data processing device, it is desired to improve so-called RAS functions such as reliability, availability, and maintainability.

The present invention has been made in response to such a conventional situation, and it is possible to write the wrong parity data to the TLB to check the operation of the parity check function, and to improve the RAS function as compared with the conventional one. It is intended to provide a data processing device capable of achieving the above.

[0012]

That is, a data processing device of the present invention is provided with a main memory having an address conversion table for converting a virtual address into a real address, and an address conversion containing a part of the address conversion table. The buffer memory and the address translation buffer memory are configured to be able to read and write data,
A data processing device comprising an address conversion function that refers to the address conversion table, and an access control unit having a parity generation and parity check function,
The access control means includes a register capable of designating parity inversion, and when the parity inversion is designated in the register, after the parity is generated, the generated parity is inverted and data is written in the address translation buffer memory. It is characterized by being.

[0013]

In the data processing device of the present invention having the above structure, the TL
It is possible to check the operation of the parity check function by writing the wrong parity data to B.
It is possible to improve the AS function.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a data processing apparatus according to an embodiment of the present invention. In the figure, 10 is an MMU storing an address conversion table in a part thereof, 11 is a bus control and memory address. VBACS, which is a semi-custom LSI that performs translation, 12 is TLB, which is a buffer memory (cache memory) for the address translation table, and 13 is a CP which controls the entire system
U and 14 are SVPs for writing / reading data to / from the TLB 12, and 15 is an AV bus.

In the VBACS 11, 20 is a mode register, 21 is a directory part address register, 22 is a directory part data register, 23 is a word part address register, and 24 is a word part data register.

A bad parity (BadPT) bit 201 is set in the mode register 20.
By setting the adPT bit 201 to 1 and setting the PED 221 and the like to 1 as described later, the parity error data can be written to the TLB 12. In addition, the directory section address register 21
Contains a ZTBD address 210 indicating the address of the directory part of the TLB 12.

The directory portion data register 22 has ZTBD data 220, PED 221, and TLBC2.
22 and PEC223 are accommodated. ZTBD data 22
Data 0 is written in the directory portion of the TLB 12 and is written in the portion indicated by the ZTBD address 210. PED221 is TLB12
Is a bit for writing data in which a parity error has occurred to the directory section of the PAD, the BadPT bit 201 of the mode register 20 is 1 and the PED
When 221 is 1, after the parity of the data (ZTBD220 data) is generated, this parity bit is inverted and the data of the parity error is written in the directory part (TDIR) of the TLB 12.

The TLBC 222 is data written in the control unit TC of the TLB 12 having the address indicated by the ZTBD address 210. Furthermore, PEC
223 is the parity error data TC of TLB12
When the BadPT bit 201 of the mode register 20 is 1 and the PEC 221 is 1, when the parity of the data of the TLBC 222 is generated, the parity bit is inverted to convert the parity error data to the TC of the TLB 12. Is configured to write to.

The word part address register 23 accommodates a ZTBW address 230 indicating the address of the word part of the TLB 12. On the other hand, the word portion data register 24 has the ZTBW data 240 and the PEW 241.
Is housed. The ZTBW data 240 is data written in the word part of the TLB 12, and is written in the portion indicated by the ZTBW address 230. PEW
Reference numeral 241 is a bit for writing data in which a parity error has occurred to the word portion of the TLB 12, the BadPT bit 201 of the mode register 20 is 1, and P
When the EW 241 is 1, after the parity of the ZTBW data 240 is generated, this parity bit is inverted and the data of the parity error is written to the word part (TWD) of the TLB 12.

In the data processing apparatus of this embodiment having the above-mentioned configuration, the operation check of the parity check function is performed as follows.

First, the SVP 14 sets the BadPT bit 201 of the mode register 20 in the VBACS 11 to 1. Specifically, the SVP 14 outputs the command “WRITE BCU REG” to the VBACS 11. Here, since the mode register 20 in the VBACS 11 is assigned to the address “00000200” and the 9th bit from the higher order side is the BadPT bit 201,
Address “00000200” and data “00000000”
00 "is output and" 1 "is written in the BadPT bit 201 of the mode register 20.

Next, arbitrary parity error data is written in a desired portion of the TLB 12, but in the following, the TLB 12 is written.
Address of directory part (TDIR) of "5555"
A case where the data "FFFE" is written in 5 "will be described as an example.

The SVP 14 outputs the command "WRITE BCU REG" to the VBACS 11. First, Z
The TBD address 210 causes the address "55555580".
0 "is given. By this address, the level 0 address" 55 "of the directory part (TDIR) of the TLB 12 is given.
Write data to 555 ".

As for the data, the ZTBD data 220 has "FF".
Write "FF" (only 16 bits of the directory part is described below). Then, a parity bit is generated for the data and odd parity (the number of "1" in the data including the parity bit becomes an odd number. The parity bit is generated as follows.), So it becomes “FFFE”.
BadPT bit 201 of mode register 20 is "1"
And the PED 221 is “1”, ZT
The parity bit of the BD data 220 is inverted and “FF
Write "FF" to the level 0 TDIR of the TLB 12.

After that, if an attempt is made to read the contents of the TLB 12 in which the parity error data is written, if the parity check function in the VBACS 11 operates normally, the parity check in the VBACS 11 detects the parity error. It At the same time, the enable bit of the level in which the parity error has occurred is turned off, and the level 0 portion is not accessed in the subsequent TLB12 access.

In the above control, BadPT = 1 as a condition for writing parity error data.
And, when PEC = 1, VBACS11
Since two data of the directory part (ZTBD data 220) and data of the control part (TLBC222) can be simultaneously written to the directory part data register 22 inside, if only BadPT = 1 is set as the inversion condition, one of This is because it is not possible to perform control that causes a parity error only in the data of.

Although the above control is for the directory section, the parity error data can be written in the control section and the word section of the TLB 12 in the same manner as the above control.

As described above, in this embodiment, the TLB12
Directory part (TDIR), word part (TW)
D) and the control unit (TC) can write incorrect parity data, so VBACS1
The operation check of the parity check function by 1 can be performed. As a result, the reliability,
It is possible to improve so-called RAS functions such as availability and maintainability.

[0030]

As described above, according to the data processing device of the present invention, the operation of the parity check function can be confirmed by writing the data of the wrong parity to the TLB. It is possible to improve.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a data processing device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a conventional data processing device.

[Explanation of symbols]

 10 MMU 11 VBACS 12 TLB 13 CPU 14 SVP 15 AV Bus 20 Mode Register 21 Directory Address Register 22 Directory Data Register 23 Word Data Register

Claims (1)

[Claims] 1. A main memory having an address conversion table for converting a virtual address into a real address, an address conversion buffer memory accommodating a part of the address conversion table, and data for the address conversion buffer memory. It is configured to read and write,
A data processing device comprising an address conversion function that refers to the address conversion table, and an access control unit having a parity generation and parity check function, wherein the access control unit includes a register capable of designating parity inversion, A data processing device, characterized in that, when parity inversion is designated in a register, after the parity is generated, the generated parity is inverted and data is written in the address conversion buffer memory.