JP2716163B2 - Cache memory control method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a cache memory control system, and in particular, retains a copy of data in a main storage device in units of blocks composed of a plurality of words, and manages the validity of data in these blocks. And a control method of a cache memory having valid bits for each word.

2. Description of the Related Art As a control method of a cache memory, there is a method of registering a block address and one valid bit corresponding to the block address in a data portion in a directory portion of a cache memory device and managing data in block units. . In such a control method, when a read request is sent to the cache memory device, if a cache miss occurs due to the determination of the block address and the valid bit, the block is read from the main storage device. It has become.

On the other hand, in some types of information processing systems, a cache memory device manages the correspondence between the contents of a block and the contents of a main storage device using a plurality of valid bits. That is, there is a cache memory device in which a valid bit is provided for each word in order to manage the contents of a block in the word constituting the block.

In this method, a valid bit corresponding to a word which is a partial area in a block is reset and invalidated by a store operation or a store operation of another processor. Therefore, at a certain moment, a case may occur in which only one valid bit in the block indicates invalid. In such a case as well, when a cache miss occurs due to the read request, the block for which the read / read request was issued is read from the main storage device.

As described above, in the conventional method, even when there is a plurality of valid bits in the block, even when a cache miss occurs because only one valid bit in the block is invalid, the main storage device can be used. In such a case, the read block is read out, so that it takes too much time to access the memory, which leads to a decrease in operating speed.

Further, in the conventional method, there may be a case where one or more (at least one) valid bits in a block indicate invalid at a certain moment. Even in such a case, when a cache hit occurs due to the read request, the block read is not performed on the main storage device. Therefore, valid data cannot be reflected on the cache memory device until a cache miss occurs.

Here, the fact that the frequency of access to the accessed block generally becomes relatively high thereafter has the drawback that the cache hit rate decreases in the above-described case, and the processing speed also decreases. .

SUMMARY OF THE INVENTION An object of the present invention is to provide a cache memory control method which shortens the operation time of memory access and increases the processing speed.

It is another object of the present invention to provide a cache memory control method for shortening a memory access time when a cache miss occurs when the number of valid bits is one.

Still another object of the present invention is to improve the cache hit ratio by reading block data from the main storage device and reflecting the data to the cache memory as in a cache miss even when a cache hit occurs when there is one or more valid bits. It is an object of the present invention to provide an intended cache memory control method.

According to the present invention, there is provided a cache which holds a copy of data in a main storage device in units of blocks each consisting of a plurality of words, and has a valid bit in words for managing the validity of data in these blocks. A memory control method, comprising: means for determining whether a cache hit or a cache miss in response to a read request to the cache memory;
Means for detecting an invalid state of a valid bit in a word unit in a block to be read when a cache miss is determined is provided. When the detection result indicates that only one word is invalid, the invalid state is determined. The read word is read from the main memory and the other word is read from the cache memory. When the detection result indicates that a plurality of words are invalid, the read request block is read from the main memory. Thus, a cache memory control method characterized by the above is obtained.

Further, according to the present invention, a cache memory which holds a copy of data in a main storage device in units of blocks each composed of a plurality of words and has valid bits for managing the validity of data in these blocks in units of words. Means for determining whether a cache hit or cache miss occurs in response to a read request to the cache memory, and when a cache hit is determined, invalidation of a word unit valid bit in a block to be read. Means for detecting an activation state, and when this detection result indicates that at least one word is invalid, the corresponding block is read out from the cache memory to the read request source and sent out, and the read request is sent to the main storage device. A cache memory control method characterized in that corresponding blocks are read out. It is.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
The figure is a detailed diagram of a comparison gate group 8 for comparing a read request address with an address registered in an address array (AA) 5. Here, one set of associative cache will be described, and it is assumed that a valid bit exists for each word.

First, an operation related to a read request from a higher-level device (not shown) will be described. The read request and its address are sent via signal lines 51 and 52 to the address selector (SAX).
1, selected by status selector (SSX) 2, address register (AAR) 3 and status register (SAR) 4
Respectively.

When the request is read by the SAR4 as a read request, the address array (AA) 5 and the AAR3
The output of AA5 and another part of the output of AAR3 are compared by the comparator 7.
The lower two bits of AAR1 are input to a read / write decoder (RWDEC) 6 through a signal line 60, and each output is decoded by the decoder 6 so as to represent a word position in the block. In this case, there are four 2 bits. The portions V0 to V3 of AA5 indicate the validity of each word in the block, and the gate group 8 compares the validity in V0 to V3 for the word in the block at the address held in AAR1.

The result of AA5 access by AAR3 is classified into the following three, and is stored in the status register (SBR) 10.

a. Cache hit (condition: HIT): The requested data exists in the cache storage.

b. Cache miss (Condition: MIS ・ ▲
▼); The requested data does not exist in the cache storage, because the valid bit of only one word in the block is invalid.

c. Cache miss (Condition: MIS MULTIMIS): The requested data does not exist in the cache storage, and the valid bit of two or more words in the block is invalid.

 The operation of the next cycle is determined from the state of SBR10.

a.HIT: Partial output of address register (ABR) 9 73
Thus, the data array (DA) 13 is addressed, its output is selected by the signal line 75 by the data selector (SDX) 14, stored in the data register (DCR) 15, and returned to the request source in the next cycle.

b. MIS MU MULITIMIS: A request to read data from the main memory is issued. The request address is specified by the output of ABR9. At the same time, the output 80 of the SBR 10 is decoded by the status decoder (SDEC) 16, and it is instructed through a signal line 81 that the read operation is a block read. ABR9 and SBR10
Are stored in AAR3 and SAR4 via signal lines 71 and 74 via SAX1 and SSX2, respectively. AA5 is addressed by AAR3 as in the case of the read request, but in this case, the upper part of AAR3 by signal line 57 is written to the AA section of AA5. 0 (invalid) is set in V0 to V3.

c. MIS ・ In the case of ▲ ▼: A request to read data from the main memory is issued. Request address is AB
Instructed by the output of R9. At the same time, SBR10 output 80 is SDE
It is decoded by C16, and it is instructed through the signal line 82 that one word is read.

Next, an operation of reading data from the main memory will be described. Data is sent to the data register (DAR) 1 via signal line 77.
Stored in 1. At the same time, the corresponding address is signal line 52 and S
Stored in AAR3 via AX1. Also, the fact that the data is read is stored in SAR4. Here, there are two states depending on the contents of SAR4.

a. For block read: AA5 is addressed by output 59 of AAR3. Depending on the other output 60 of AAR3 and the word position in the block read by decoder 6, V0 to V3
Is selected, and “1” (valid) is written. In the next cycle, the contents of DAR 11, that is, the read data, are moved to data register (DBR) 12. AAR3 and SAR4 are also ABR9 and SBR1
Move to 0. DA13 is addressed by ABR9 and S13
Data of DBR12 is written according to the instruction of BR10. The data reading is performed four times in this example. The order in which data arrives from the main memory starts from the address where a cache miss has occurred, and is sent so as to circulate through the addresses in the block. In the first load operation, when writing the contents of DBR12 to DA13, the input of DCR15 is SDX1
4, the output 79 of the DBR 12 is selected by the signal line 76, and the read data is returned to the host device in the next cycle.

b. In the case of one-word reading: the next cycle is entered, and the contents (read data) of DAR11 are moved to DBR12. At the same time AAR3,
SAR4 also moves to ABR9 and SBR10 and SDR15 to SDR in the next cycle.
In X14, the data selected by the signal line 76 is stored in the DCR15. Thereafter, the read data is returned to the host device.

FIG. 2 shows a specific example of the gate group 8 of the block shown in FIG. 1. The output 70 of the comparator 7 for judging a cache hit or a miss, the outputs 61 to 64 of the read / write decoder 6, and the validity are furthermore shown. Using the bit outputs 66 to 69 of bits V0 to V3, HIT, MIS
And a gate circuit for determining MIS.

As described above, when there is one valid hit indicating invalidity at the time of a cache miss, the word corresponding to the valid bit is read from the cache memory, and only the invalid word is read from the main storage device. Since it is not necessary to re-register in the cache memory, the access time to the main storage device is shortened, and the cache memory can perform other processing accordingly (for three words).

FIG. 3 is a block diagram of another embodiment of the present invention, and the same parts as those in FIG. 1 are denoted by the same reference numerals. Also in this embodiment, one set of associative cache will be described, and it is assumed that a valid bit exists for each word.

First, an operation related to a read request from a higher-level device (not shown) will be described. Address selector (SAX) for read request and its address through signal lines 51 and 53
1, selected by status selector (SSX) 2, address register (AAR) 3 and status register (SAR) 4
Is stored in When the read request is decoded by SAR4, it is addressed by the address array (AA) 5 and a part 59 of the output of AAR3, and the output of AA5 and AAR
Another part of the output of 3 is compared by the comparator 7. AAR1
The lower two bits are decoded by a read / write decoder (RWDEC) 6 through a signal line 60 so that each output indicates a word position in the block. In this case, there are four 2 bits. Each part of V0 to V3 of AA5 indicates the validity of each word in the block, and the gate group 8 sets V0 to V3 for the word in the block at the address held in AAR1.
Effectiveness will be examined in V3.

The access result of AA5 can be classified into the following three by AAR3 and stored in the status register (SBR) 10.

a. Cache hit (condition: HIT VALID): The requested data exists in the cache storage, and no valid bit in the block has been invalidated.

b. Cache hit (Condition: HIT ・ ▲ ▼);
The requested data exists in the cache storage, and one or more of the valid bits in the block are invalid.

c. Cache miss (condition: MIS); the requested data does not exist in the cache storage.

 The operation of the next cycle is determined from the state of SBR10.

a.HIT VALID: The data array (DA) 13 is addressed by the output 73 of the address register (ABR) 9, its output is selected by the signal line 75 by the data selector (SDX) 14, and the data register (DCR) Stored in 15,
Returned to requestor in next cycle.

b. HIT • In the case of ▲ ▼: HIT • Data is returned to the request source in the same way as in the case of VALID. At the same time, a request for reading data from the main memory is issued. Request address is AB
Indicated by the output 72 of R9. The contents of ABR9 and SBR10 are connected to AAR3 via signal lines 71 and 74 via SAX and SSX, respectively.
Stored in SAR4. AA5 is addressed by AAR3 as in the case of a read request, but in this case
The upper part of AAR3 by the signal line 57 is written in the AA part of AA5. 0 is set in V0 to V3.

c. In the case of MIS: a data read request is issued to the main memory, and the following operations are performed in the same manner as in the case of HIT.

Next, an operation of reading data from the main memory will be described. Data is sent to the data register (DAR) 1 via signal line 77.
1 and the corresponding address is stored in AAR3 via signal line 102 and SAX1. The fact that the data is read is stored in the SAR. AA5 is addressed by output 59 of AAR3. AAR3 another output 60 and decoder (RWDEC)
6, V0 to V3 are selected according to the word position in the block read out, and "1" is written.

In the next cycle, the contents of the DAR 11, that is, the read data move to the data register (DBR) 12. DA13 is addressed by ABR9, and data of DBR12 is written according to the instruction of SBR10. The data reading is performed four times in this example.

The order in which data arrives from main memory is either a cache hit (HIT, ▲ ▼) or a cache miss (MI
It starts from the address where S) was performed, and is sent so that the addresses in the block are turned forward. The following operations are performed in the same manner as the cache hit (HIT • ▲) and the cache miss (MIS). However, in the case of a cache miss, the first load operation is to write the contents of DBR12 to DA13, and the input of DCR15 is output from DBR12 by SDX14.
9 is selected by the signal line 76, and the read data is returned to the host device in the next cycle.

FIG. 4 shows a specific example of the gate group 8 in the block shown in FIG. 1. As in the previous embodiment, the output 70 of the comparator 7 for judging a cache hit / miss and the outputs 61 to 61 of the read / write decoder 6 are shown. H, which is the access result of AA5, using 64, and furthermore, the respective bit outputs 66 to 69 of the valid bits V0 to V3.
It is a gate circuit for determining IT, MIS and VALID. As described above, when at least one valid bit indicates invalid at the time of a cache hit, data is read from the main memory in the same manner as a cache miss, and the data in the main memory is reflected in the cache memory. Because
An improvement in the cache hit rate can be expected.

Effect of the Invention As described above, according to the present invention, when a cache miss occurs, 1
When two valid bits indicate invalid, the invalid word is read from the main memory and reflected in the cache memory, and the valid word is read from the cache memory. Therefore, the operation time when data is reflected in the cache memory can be reduced, and the memory This has the effect of speeding up access.

Also, when at least one valid bit indicates invalid at the time of a cache hit, the corresponding block data is read from the main storage device and the invalid word is reflected in the cache memory in the same manner as in the case of a cache miss, so that the cache hit rate is reduced. Thus, there is an effect that the speed of memory access can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a circuit diagram of a specific example of a gate group of the block of FIG. 1, FIG. 3 is a block diagram of another embodiment of the present invention, and FIG. FIG. 4 is a specific example circuit diagram of a gate group of the block of FIG. 3; Explanation of Signs of Main Parts 5 ... Address Array 7 ... Comparator 8 ... Gate Group 13 ... Data Array

 ────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Shuya Hirayama 3-20-4 Nishi-Shimbashi, Minato-ku, Tokyo Japan Electric Engineering Co., Ltd. (56) References JP-A-62-133545 (JP, A) 60-83156 (JP, A) JP-A-1-321534 (JP, A)

Claims (2)

(57) [Claims] 1. A control method for a cache memory in which a copy of data in a main storage device is held in units of blocks each consisting of a plurality of words, and a valid bit for managing the validity of data in these blocks is provided in units of words. Means for determining a cache hit or a cache miss in response to a read request to the cache memory, and, when the cache miss is determined, the invalidation state of the valid bit in word units in the block to be read. Means for detecting, when the detection result indicates that only one word is invalid, the invalidated word is read from the main storage device and the other word is read from the cache memory; Reading a block of a read request from the main storage when the result indicates that a plurality of words are invalid. Cache memory control method, characterized in that the. 2. A control method for a cache memory which holds a copy of data in a main storage unit in units of blocks each consisting of a plurality of words and has valid bits for managing the validity of data in these blocks in units of words. Means for determining a cache hit or a cache miss in response to a read request to the cache memory; and, if determined to be a cache hit, invalidating the valid bit in word units in the block to be read. Means for detecting, when the result of the detection indicates that at least one word is invalid, the corresponding block is read out from the cache memory to the read request source and transmitted, and the corresponding block is transmitted to the main storage device. A cache memory control method, characterized in that the data is read from the cache memory.