JPH02204847A - Cache memory device - Google Patents

Abstract

PURPOSE:To contrive the decrease of a delay time, a hardware quantity and an electric power quantity by storing the information for specifying an entry of an address conversion buffer in an address array of a cache memory instead of an address. CONSTITUTION:An address array AA 4 is brought to addressing by the upper 6 bits of a part of an in-page address of a virtual address stored in a virtual address register VAR 2. Data of two levels selected by an address of a signal line 105 are compared with the lower 9 bits of a virtual page number which brings an address conversion buffer TLB of a signal line 103 to addressing by comparing circuits 14, 15. In the AA 4, a TLB address for specifying one of entries of the TLB, and a level of the TLB are stored. Accordingly, the comparing circuits 14, 15 input a part (signal line 103) corresponding to the TLB address, two information in the AA 4, and hit signals 115, 116 of each level of the TLB, into the given virtual address. In such a way, the reduction of a delay time of the circuit can be contrived.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device, and more particularly to a cache memory device.

Today, many information processing devices use virtual memory. This method assumes an address space (virtual address space) that is larger than the address space (real address space) of the main memory actually provided in the information processing device, and converts the virtual address and real address using the following steps: This uses an address conversion table. The correspondence between virtual addresses and real addresses is done in units called "r pages," and the most frequently accessed pages are placed in the real address space, and other pages are placed in secondary storage such as a disk.

Conversion tables are usually placed in main memory. Accessing this conversion table every time memory access improves performance.
It will fall on the edge. This is because the main memory usually takes 2 to 3 times longer than the cycle time of the arithmetic processing unit in the information processing device.
This is because the cycle time is 0 times slower. For this reason,
The arithmetic processing section is equipped with a decimal number called an address translation buffer, but the speed is about the same as the cycle time of the arithmetic processing section.

Similarly, regarding tables in main memory, many information processing devices are equipped with a high-speed buffer within the arithmetic processing unit, which is called a cache memory. Main memory is divided into units called blocks, and each block is loaded into cache memory.

Cache memory usually has a data section (data array DA) that holds a copy of the contents of main memory, and an address section (address array AA) that holds the addresses of data held in DA corresponding to each block of DA. Consisting of
Access to the cache memory is performed as follows. First, compare the address you want to access with the contents of each block in AA, and if an entry with the same address exists in AA, read out the corresponding block in DA.In most cases, the AA entry has a real address, Virtual addresses are rarely stored.

On the other hand, with the recent increase in the scale of information processing systems, the virtual addresses and real addresses of information processing devices have been significantly expanded. Therefore, the number of bits representing both addresses is 3.
It is 0 bit or more.

The address stored in the AA of the cache memory also requires at least 20 bits, excluding 3 to 4 bits representing a block and bits that can be removed by grouping by address range. Furthermore, in order to efficiently manage large address spaces, the capacity of cache memory continues to increase.

In this way, the capacity of AA tends to increase in both the width of each entry and the number of entries because of the two requests arising from the same trend. As the number of bits (width) included in an AA entry increases, the RAM (Ran
dQII Access Memory) increases, and driving them requires a large number of gates and a large amount of power. Furthermore, as the number of bits compared each time the cache memory is accessed increases, the delay time of the circuit increases, and the clock cycle that determines the processing capacity of the information processing device is determined at this portion.

1. The purpose of the present invention is to reduce the number of bits (
It is an object of the present invention to provide a cache memory device in which the delay time of a circuit is reduced by reducing the width).

According to the present invention, there is provided an address translation buffer having a plurality of entries for converting an input access virtual address to the main memory into a real address, and a copy of data stored in the main memory to a predetermined size. a data array held in block units to be managed in block units; an address array holding information specifying the addresses of the main memory corresponding to each block; and the address conversion buffer and the address array a cache hit determining means for determining the presence or absence of a cache hit based on an index result based on a virtual address, wherein the address array holds index address information for specifying an entry of the address translation buffer; Each entry of the address translation buffer and the address array holds generation information indicating the generation of the corresponding entry of the address translation buffer, and the cash hit determination means uses the index address information of the address translation buffer and the address array. There is obtained a cache memory device characterized in that it is configured to make a cache hit determination using not only the index result but also the generation information of the corresponding indexed entries.

counterfeit Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

In this embodiment, both the virtual address (VA) and real address (PA) are 32 bits, the page in virtual memory management is IK bytes (I K = 1024), and the address translation buffer (TLB) and cache memory are 2 bits. It has a set-associative structure of levels (also called compartments and ways). TLB address is 51
2, and addressing is performed using the lower 9 bits of the page number (22 bits obtained by subtracting 10 bits for the intra-page address from the 32-bit virtual address). Under this condition, each entry in the key part of the TLB (the part compared with the requested virtual address is called TLBK) has a width of 13 bits, and corresponds to the TLBK and has a real page number.
The data part (TLBD) of B is 22 bits.

The cache memory has a block size of 16 bytes, and the address array AA is addressed using the upper 6 bits of the address within the page. In other words, the number of columns is 64.0 Normally, each entry in address array AA should store 22 bits, the same as TLBD, but in the present invention, only 9 bits for addressing TLB are required. .

Next, the read operation of the cache memory will be explained.

The access request virtual address is sent to this cache memory through a signal line 101 in a virtual address register (VAR).
)2. Address translation buffer (TLB) 3 and address array (AA>4) are accessed in parallel by VAR2.First, TLB3 is addressed by the lower 9 bits of the virtual page number among the virtual addresses stored in VAR2. This is done by the signal line 103. This causes the specified key part of TLB3 (
The contents stored in the entries of each level of the data section (TLBD) of TLBK) and TLB3 are read out.

The read data of TLBK is compared with the upper 13 bits of the virtual page number of VAR2 by comparison circuits 11 and 12, and only when they match, their output signal lines 115 are compared.
and 116 have a logical value of 1.

Note that the TLB registration method is controlled so that a given virtual address matches only one of the two levels.

When the contents of the TLBK match a given virtual address, this is called a TLB hit.

Further, the logical meaning given to signals &1115 and 116 is called a hit signal.

The output of the TLBD is selected by the real address selector (PX) 18 in response to a hit signal from the corresponding TLBK and stored in the real address register (PAR) 5.

On the other hand, address array (AA) 4 is addressed by the upper 6 bits of the intra-page address portion of the virtual address stored in VAR 2 (signal line 105).
, two levels of data selected by the address on signal line 105 are compared by comparison circuits 14 and 15 with the lower 9 bits of the virtual page number addressed to the TLB on signal line 103.

AA4 stores a TLB address that specifies one of the TLB entries and the TLB level.

Therefore, the comparison circuits 14 and 15 input the portion corresponding to the TLB address (signal line 103) of the given virtual address, the two pieces of information in the AAJ described above, and the hit signals 115 and 116 of each level of the TLB. shall be.

Details of comparison circuits 14 and 15 are shown in FIG.

The TLB addresses are compared by comparator 201.

A signal line 113 is 2-bit information indicating which TLB level the TLB address stored in AA4 is at. AND circuits 202 and 203 are 'T' L
B's two hit signals 115 and 116 and signal line 11
3 (which are just two lines showing the same correspondence as signal lines 115 and 116). If either one of them matches, the output 209 of the OR circuit 204 becomes a logical value 1, and the AND circuit 205 outputs the comparison output 2 of the comparator 201.
08 validity conditions are given.

The outputs of comparison circuits 14 and 15 are stored in a 2-bit hit level register (AHR) 6.

The next cycle's operation is determined by the contents of AHR6.

■When any bit of AHR6 is logic 1.

The state at this time is called a cache hit, and the data array (DA) 8 is accessed and read data is stored in the read data register (RDR) 10. DA8 is P
Addressing is performed using the lower 10 bits of AR5, that is, the intra-page address. Data corresponding to each level is read out, and the data selector (DX) 9 selects the hit level stored in the AHR 6 and stores it in RDRIO. The data stored in RDRIO is on signal line 1
13, it is returned to the requester.

■When any bit of AHR6 is logic 0.

This state is called a cache miss, and at the same time a cache hit signal is stored in the AHR, information necessary at the time of a cache miss is stored in two other registers. The JIC Yash registered address register (CAR) 7 contains the TL of the request address that caused the cache miss.
The B address is stored in the TLB level register (TR).
17 stores the TLB hit level.

When a cache miss is recognized, the contents of CAR7 and TR17 are first written to the address array write register (AW), respectively.
R) 20 and TLB level write register (WTR) 21
It can be paid in And AHR20 and WTR21 are AA
4 is written to the corresponding part. Address array write level register (AWLR) 19 instructs which level of AA4 to write to. AWLR19
The content of is determined by an appropriate method.

On the other hand, it is necessary to load the requested data into the cache memory from the main memory. Therefore, the address of PAR5 is sent to the main memory, and the data of the corresponding block is transferred to DA8.
Herod.

After writing to AA4 and loading to DA8 is completed, the cache memory is accessed again using the requested virtual address, this time resulting in a cache hit. As mentioned above, a copy of a portion of the virtual address to real address conversion table is placed in TLB3. If there is no entry in TLB3 for the requested virtual address in cache memory 1, the conversion table in main memory is stored in TLB3.
need to be copied to. There are many ways to do that. I will not discuss the details here.

Now, suppose that TLB3 is rewritten. Then, the rewritten entry contains a different pair of virtual address and real address than before. However, the TLB addresses are the same. If AA4 contains information pointing to that entry in TLB3 before being rewritten, a contradiction will occur.

Therefore, in the cache memory of the present invention, TLB3 and A
The generations of read TLB3 and AA4, each entry of A4 having information indicating the generation, are compared, and if they are different, it is assumed that there is a cache miss.

When TLB3 and AA4 are accessed, TLB
In the 0th cycle in which the generations of 3 and AA4 are read into the TLB generation register (TGR) 13 and the AA generation register (AGR) 16, respectively, the generation run comparison circuit 26 compares them and determines whether they are different. For example, even if a cache miss can be determined from the contents of AHR6, it is treated as a cache miss. Because A
This is because the TLB entry of the generation stored in A4 has already been included in the generation of TLB3.

During AA write processing at the time of a cache miss, the contents of TGR13 are changed to the AA generation write register (AGWR).
23, and is written to the corresponding field of AA4. Information regarding generation is usually several bits of information. When an entry in TLB3 is rewritten, the generation of that entry is determined by reading the old generation into TGR13, incrementing the generation by one by +1 adder 24 when writing TLB, and writing to the TLB generation write register (TGWR). 22 can be rewritten in reverse.

If the number of generations exceeds the range that can be represented by the number of bits representing the generations prepared in advance (generation overflow), this is detected by the generation overflow detection circuit (GOC) 25. In the event of a generation overflow, either invalidate all entries in AA4 (write WTR to logic 0) or scan AA4 to find the entry in AAJ that has the same TLB address as the entry in TLB3 that caused the generation overflow. Disable an entry.

In this way, according to the present invention, information that specifies TLB entries is stored in the address array (AA) of the cache memory instead of addresses. This has the effect that the number of bits is reduced, thereby making it possible to reduce delay time, amount of hardware, and amount of power.

[Brief explanation of the drawing]

FIG. 1 is a system block diagram of an embodiment of the present invention, and FIG. 2 is a diagram showing a specific example of the comparison circuit 14 of the block in FIG. 1. Explanation of symbols of main parts 2...Virtual address register 3...Address translation buffer 4...Address array 5...Real address register 8... ...Data array 11.12, 14.1 5...Comparator

Claims (1)

[Claims] (1) Access to main memory An address conversion buffer having multiple entries for converting input virtual addresses into real addresses, and a block for managing copies of data stored in the main memory in units of blocks of a predetermined size. A data array held in units, an address array holding information specifying the address of the main memory corresponding to each block, the address translation buffer, and the address array are cache hit based on the index result using the access virtual address. cache hit determination means for determining whether or not a Each entry in the array holds generation information indicating the generation of the corresponding entry in the address translation buffer, and the cache hit determination means uses the index address information of the address translation buffer, the index result of the address array, etc. To,
A cache memory device characterized in that it is configured to further use generation information of corresponding indexed entries to determine a cache hit.