JPS62131351A - Effective address calculating device - Google Patents

Abstract

PURPOSE:To detect memory mapped I/O in a central processing unit by giving memory mapped I/O information to a page descriptor and storing it in a TLB. CONSTITUTION:MPIO information 323 is given to a page descriptor 32, and a page indicated by the page descriptor is mapped in an I/O space if this IO information is '1', and the page indicated by the page descriptor is in a memory space if IO information is '0'. This MPIO information is recorded in the TLB. A part except an intra-page offset of a VAR 11 of the effective address sent from an effective address calculating part is compared with virtual pages stored in a virtual address part of the TLB; and if a coincident virtual page number is found, the entry in a data memory part of the TLB corresponding to the virtual page number is read out to an RAR 15. The read actual page number in the RAR 15 is combined with the intra-page offset of the virtual address of the VAR 11 to generate an actual address, and this address is outputted to an address bus 110.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a central processing unit in an information processing device, and particularly to control of input and output of the central processing unit.

[Conventional technology]

Conventionally, the following two methods can be considered as methods for accessing external input/output devices from a central processing unit.

1. Access by input/output commands The central processing unit outputs to the input/output device and exchanges data with the input/output device. 2. Access by memory Mabutsu I/O memory map) I/Q is the main The input/output device is connected to a part of the address space to which the storage device is connected (hereinafter this address space is referred to as I/Q space), and the address output when executing write/read instructions and arithmetic instructions to the main memory is the input/output device. If the address is an address to which an output device is connected, this method performs data exchange with the input/output device.

This memory Mabutsu I/O has the following features and drawbacks.

〔Features〕

- It is possible to specify an input/output device in the same way that main memory can be specified as a memory operand for general arithmetic operation instructions, transfer instructions, etc.

〔Disadvantage〕

- An interleave configuration method is possible for the main storage device as a speed-up method, but such a configuration is difficult for input/output devices.

・Recovery processing when reading/writing fails is different between the main storage device and the input/output device.

- In a central processing unit that uses a paging virtual memory system and can specify operand addresses in bytes, the operands may span multiple pages, but the I/O space and memory space may span multiple pages. The central processing unit operates differently when spanning pages.

・The central processing unit that adopts the pipeline method must write the operand of the nth instruction.9. There are cases where the operand of the (n+1)th instruction is read out first, but in the case of the work/O space, if this happens, the control of the input/output device may go out of order.

・A central processing unit with an I/O configuration (memory map) cannot distinguish between memory space and I/Q space internally, so it is difficult to implement a function that specifies the level at which input/output device access should be executed. It is.

[Problem to be solved by the invention] In a central processing unit that uses a virtual memory system based on the paging method and can specify operand addresses in bytes, operands may span multiple pages. The operation of the central processing unit differs between the /O space and the memory space when the space spans multiple pages. In memory space access, the first page and second page in the virtual space are converted to completely different pages in real memory in the virtual space, so the address conversion for the first address of the operand and the next Address translation is required for the first address of a page, but since there is no concept of page in I/O space, even if it spans multiple pages in virtual space,
It is only necessary to perform address translation for the first address of the operand. However, in a central processing unit with a memory-mapped A/O configuration, there is internal memory space and I/O.

Since space cannot be distinguished, memory space and I
It is difficult to realize other operations in the /O space.

[Means for solving problems]

The above problem is due to the fact that the central processing unit cannot distinguish between memory space and I/O space.

On the other hand, a central processing unit that employs a virtual memory method uses segment descriptors, page descriptors, etc. to convert virtual addresses to real addresses.

These descriptors contain information for converting virtual addresses to real addresses as well as information for memory protection.
/ o Information indicating whether the device is connected (hereinafter referred to as MPI)
It is also possible to have information (referred to as O information).

The present invention uses this MPIO information to create a memory map)
This method solves the above-mentioned problem by making it possible to determine o.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an address translation unit (hereinafter abbreviated as TLB) in an embodiment of the present invention.

FIG. 2 is a block diagram of an effective address calculation section in an embodiment of the present invention.

FIG. 3 is a diagram showing the structure of an address translation table and a page descriptor in the embodiment of the present invention.

FIG. 4 is a block diagram showing the configuration of a central processing unit in an embodiment of the present invention.

FIG. 5 is a diagram illustrating information sent on the tag bus in an embodiment of the invention.

FIG. 6 is a diagram showing the conversion from a virtual address to a real address in an embodiment of the present invention.

FIG. 7 is a timing chart showing effective address calculation in the embodiment of the present invention.

In FIG. 1, 11 is a partial address register (MAR) for temporarily storing the effective address (or virtual memory address) t sent from the effective address calculation unit.
It is. 12 stores a plurality of virtual address numbers excluding the in-page offset part of the virtual address, and
This is an associative memory that has a comparison function with the virtual page number section of the page. Reference numeral 13 denotes an encoder for generating an entry number indicating which entry matches the comparison function of the associative memory 12. 14, associative memory 12, encoder 1
This is a data memory for storing real address information, protection information, and MPIO information corresponding to the entry number that matches No. 3. 15 is a real address register (hereinafter referred to as I(,
(abbreviated as A). Reference numeral 16 indicates accompanying information (hereinafter referred to as TAG) sent from the effective address calculation unit at the same time as the effective address.
Abbreviated as information. ) to temporarily store the register (hereinafter,
(abbreviated as TAG). 17 decodes the tag information in the TAG box 16 and generates a signal indicating the type of access (hereinafter abbreviated as access type), and a signal indicating whether it is Ilo or not.
This is a decoder for generating M/IQ (hereinafter abbreviated as M/IQ).

18 is execution level information from the instruction execution unit, decoder 1
This is a protection check mechanism for detecting protection exceptions from information such as access type information from RAR 15 and protection information from RAR 15. 19 determines whether the virtual address sent from the effective address calculation section indicates a memory space or an I/O space, based on the MPIO information from the RA processor 15 and the M/IQ signal from the decoder 17. It is a circuit.

1/O reads the virtual address from the effective address calculation unit to TL.
B is an address bus (hereinafter abbreviated as ABU8) which is sent to the memory control unit and which multiplexes and sends the real address from the TLB to the memory control unit.

Reference numeral 111 is a bus for transmitting tag information from the effective address calculation unit at the same time as the virtual address, and for transmitting tag information at the same time from the TLB at the same time as the real address.

112 is an IO access signal (
This is a signal line sent to the effective address calculation section.

In FIG. 2, 21 is a bus (hereinafter abbreviated as EBUS) for sending the values of general-purpose registers necessary for effective address calculation from the instruction execution section to the effective address calculation section. 22
is a register for temporarily storing an index value (hereinafter abbreviated as EATRl). 23 is a register for temporarily storing a pace address. (Hereinafter, EAT
It is abbreviated as 几2. ) 24 is for temporarily storing correction values such as bride increment and post increment.
This is a register for temporarily storing a displacement value (hereinafter abbreviated as EATR4).

26 is a bus for sending the displacement value from the instruction analysis unit to the effective address calculation unit (hereinafter referred to as IBU).
(abbreviated as S). 27 is an adder (hereinafter abbreviated as C8A) that adds the value of gATRl-4 in a carry save method. 28 is a multiplexer which selects the SUM part and CARR, Y part values of C8A or the NPGRO value and constant /O00H according to the NPGRQ signal. 29 is
This is an adder (hereinafter abbreviated as CPA) for adding two inputs selected by 28 multiplexers.

2/O is a register (hereinafter abbreviated as 0PAR) for storing the effective address of the memory operand among the effective addresses calculated by the 29 adders. 211 is the effective address calculated by the 29 adders,
This is a register for storing the effective address of a branch destination or prefetch destination (hereinafter abbreviated as PFA). 212
Address bus 11 in Figure 1 is the bus for sending to the control section.
Connected to 1. 213 is a page boundary detector for detecting whether a page boundary straddles from the effective address and the data type of the operand. Reference numeral 214 is a register (hereinafter abbreviated as NPGR) for storing the virtual page number (address obtained by subtracting the intra-page offset from the virtual address) of the previous page when the operand straddles a page boundary. 215 is a timing control circuit of the effective address calculation section. Reference numeral 216 is a register for storing tag information regarding the operand address sent from the instruction analysis section. A decoder 217 decodes the information in the tag register 216 and generates a signal (Ilo) indicating the data type of the operand and whether it is an I/O command. 218 is a bus for sending the tag information of 216 to the TLB and the memory control unit;
Connected to the tag bus 111 in FIG. 1 (hereinafter referred to as '1')
(abbreviated as AGBUS). 219 is a ■0 access signal (I OAC) sent from the address translation section. 220 is a signal output from the timing control circuit 215 for selecting whether to calculate the start address of the operand or to calculate the start address of the next page when the operand straddles the page boundary (hereinafter referred to as NPG8).
(abbreviated as EL). Reference numeral 221 denotes a signal group carrying the start address of the page in which the effective address calculated by the adder 29 exists.

222 is a signal output from the timing control circuit 215, and is a signal indicating the next page. Reference numeral 223 indicates a trigger signal for starting effective address calculation (hereinafter abbreviated as STEA1) issued from the instruction analysis unit 43. 224
is a signal output from the timing control circuit 215, and C
This is a signal that outputs the addition result of PA29 to 0PAR2/O (hereinafter abbreviated as ST T). 225 is a signal output from the timing control circuit 215, which outputs the addition result of the CPA 29 to the 5TEAN'l' 224 and outputs it to the OP.
This is a signal to be latched to A 2/O (hereinafter referred to as 0PARW).
). 226 is a signal output from the timing control circuit 215, and the addition result of CPA29 is sent to 5TEANT2.
24 is a signal sent to ABUS 212 (hereinafter abbreviated as MARTAB). 227 is a signal output from the timing control circuit 215;
This is a signal that latches the virtual page number issued from /O (hereinafter abbreviated as NPGRW). 228 is a page boundary detection signal output from the page boundary detector 213 (
(hereinafter abbreviated as DETECTPO). 229 is a signal group output from the decoder 217 and representing the data length of the operand. 230 is output from the decoder 217,
This signal indicates whether the operand is a memory space access or an I/O space access.

In FIG. 3(a), numeral 31 shows the entire address translation table (page table and 19).

311h, 1 entry of the address translation table (hereinafter,
page descriptor). The same figure (b) is the same figure (a
) shows the structure of the page descriptor 311 in detail. 321 indicates that the content of this descriptor is valid at 11'', and indicates that the content of this descriptor is invalid at ``O'' (hereinafter abbreviated as ■ bit).322 is, '1' indicates that the page indicated by this descriptor is mapped to the I/O space, and 'On indicates that the page indicated by this descriptor is not mapped to the memory space.
Hereinafter, MPIO is abbreviated as -t). 323 is “1n lever 17
) fk [Indicates that the page indicated by the child exists in main memory, “
This bit is 0'' and indicates that the page indicated by this descriptor does not exist in the main memory (hereinafter abbreviated as P bit).

In 324, "l" indicates that the page indicated by this descriptor has been previously referenced by the central processing unit, and /O" indicates that the page indicated by this descriptor has not been referenced by the central processing unit. (hereinafter abbreviated as A bit).32
5 is a bit M1'' indicating that the page indicated by this descriptor was previously written by the central processing unit, and 0 indicates that the page indicated by this descriptor was not written by the central processing unit ( (hereinafter abbreviated as W bit).32
6 is protection information for the page indicated by this descriptor.

327 is real address information indicating to which address in the real memory space or real I/O space the virtual page indicated by this descriptor is mapped.

Next, the operation in this embodiment will be explained.

The central processing unit in this embodiment is composed of the following units: an instruction analysis section 43, an effective address calculation section 44, an address conversion section 45, a main memory control section 46, and an instruction execution section 47, as shown in FIG. Ru. And each unit is ABUS 4
1, TAGBUS42, IBUS48, EBUS4
9.

The instruction analysis section 43 decodes the instruction read from the main memory, converts it into a format that can be directly executed by the instruction execution section 47, and sends it to the instruction execution section 47. In addition, if the instruction analyzed by the instruction analysis unit 43 has an operand for memory or I/O space, information necessary for calculating the effective address of that operand (inch value, pace value, tooth placement value, etc.) is sent to the effective address calculation unit 44.

The effective address calculation unit 44 calculates an effective address based on information necessary for effective address calculation, and sends the effective address to the address conversion unit 45. The address conversion unit 45 converts the effective address sent from the effective address calculation unit 44 into a real address and sends it to the main memory control unit 46. The main memory control unit 46 accesses the main memory or the input/output device using the real address sent from the address conversion unit 45. When reading an operand, the information read from the main memory or the input/output device is sent to the instruction execution unit 47), and when writing the operand, the information sent from the instruction execution unit 47 is written to the main memory or the input/output device. The instruction execution unit 47 executes the instruction based on the instruction decode information sent from the instruction analysis unit 43. The address bus 41 is used to transfer information addresses from the execution address calculation section 44 to the address translation section 45 and to transfer real addresses from the address translation section 45 to the main memory control section 46. The tag bus 42 is a bus used in correspondence with the address bus 41.
This bus is used to transfer various information associated with the effective address and real address above.

The information 51 transferred by this tag bus 42 includes the fifth
As shown in the figure, there is the following information.

1. Bits 2-3... Operand data length 0
0: Byte (1 byte) 01: Half word (2 bytes) /O: Word (4 bytes) 2 Bit 9...M/IO1: Indicates access to memory space.

0: Access to I/O space to show that

3. Bit/O...NPGl: Indicates the start address of the next page when the operand straddles a page boundary.

0 operand address and

4. Bits 11-12...Access type 0
0:EXECUTE 01:WRITE 1o:IAD 11:READ/WRITE 5, bit 13...V/R.

1: Effective address (virtual address) .

O: Indicates a real address.

In the central processing unit configured as described above, memory or I/
The operation when executing an instruction having an operand for O space will be described below.

When the instruction analysis unit 43 analyzes the instruction, it extracts information necessary for effective address calculation, such as general-purpose register values, index values, and displacement values, from EBUS (21 in FIG. 2, 49 in FIG. 4), IBUS (21 in FIG. 26 in Figure 4, 4 in Figure 4
8) register EATRI of the effective address calculation unit,
EAT 几2゜EATR3, EATR4 (Fig. 2 22.2
3°24.25). Then, accompanying information regarding the operand (access type, data length, information M/IO indicating whether it is memory space or I/O space), etc. is sent to the TTAG 16.

The effective address calculation unit 44 is EATRI.

The values of general-purpose registers EATR2, EATR3, EATR, EATR4, index values, displacement values, etc. are added using a carry save adder 27 and a carry groper gate adder 29.

Here, a signal 5TEAI 223 for starting effective address calculation comes from the instruction analysis section 43 (Fig. 7-72), a 5TEANT224 (Fig. 7-73) is output from the timing control circuit 215, and the addition result is output from the CPA 29. be done. When 5TEANT224 (Fig. 7-72) appears, V
A TAB (Figure 7-76) appears, and the addition result is A
bTJs 212 and sent to the address conversion section,
0PAR, W225 (Fig. 7-74) comes out and OPA 几2
/O latched. Then, the tag information in the TTAG box 16 is decoded (Fig. 2-217) to obtain the data length, and the page boundary detector determines whether the data spans a page boundary from the effective address (result of CPA29) and data length. 21
3 is detected, and if detected as straddling, DETEC
TPG 213 is sent to timing control circuit 215.

In a central processing unit that uses a page-based virtual memory system (see Figure 6-(a)), when a memory operand spans multiple pages (as shown on the left side of Figure 6-(a)), the first page Although the second page is continuous in the virtual space, it can be converted into a completely different page in the real memory (right side of FIG. 6-(a)). Therefore, the effective address calculation for the first address of the operand, virtual →
Real address conversion (611 in Figure 6-(a)), it is impossible to obtain the entire operand from the real memory space only by memory access, effective address calculation for the first address of the next page, virtual → real address conversion ( Figure 6 - (
612) of a), memory access must be performed for each row.

On the other hand, in memory Matsubutsu I/O, even if an operand spans multiple pages, the I/O space does not have the concept of a page (see Figure 6-(b), pages cannot be contiguous in virtual memory. For example, the calculation of the effective address for the start address of the operand even when it is performed continuously in the I/O space, even when it spans multiple pages, the virtual → real address conversion (621) of the figure 6), and the I/O weight. All you have to do is perform a child access, calculate the effective address for the first address of the next page, and convert from virtual to real address (Fig. 6-Φ) at 622.
), no I/O quantum access is required.

Therefore, when an operand spans multiple pages, the effective address calculation section performs the following three operations.

1. For memory space access, M/IO information (bit 19) of TAG 216 is “1”
indicates that it is a memory space access, and the 10AC signal from the address converter 45 (112 in Figure 1, 112 in Figure 2)
219) is "0" (memory map) indicating that it is not I/Q. ) (Fig. 7-79), and page boundary detector 2
13, the DETECTPG 213 (Fig. 7-75) detects the page boundary, and the timing control circuit 21 detects the page boundary.
5, the start address of the next page will be calculated, and the timing control circuit 215 will output the NP
G8EL220 (Fig. 7-77) was released, and this NPG
Virtual page number 2 latched by Npoaw227 (Figure 7-78) issued with 8EL220
14 and a value in which 0 is put in the lower bits 0 to 11 are combined and input data 221 to the CPA 29.

(In this example, since the page size is 4 bytes, the constant /O00H is added to calculate the next start address.) Then, as the addition result, the start address of the next page is output to the address bus 212 and address conversion is performed. Part 45
send to At the same time, the tag information of the TAGAR 216 is also output to the tag bus 218 and sent to the address translation section. At this time, bit 9 (NPG) 222 of the tag information is set to 1''.

2 In the case of memory Matsubuto I/O, the effective address sent to the address converter 45 is converted into a real address (Figure 1) and output to the address bus again and sent to the main memory controller 46 (see details of TLB operation). will be discussed later). At this time, maintenance information and MPIO are also selected from the data memory 14 along with the real address, and this MP
If the IO information is "1" indicating that the actual page number is mapped to the I/O space, the work/O detection unit 19 determines that the
Change the TAG information to “0” so that the gM/IO information indicates the I/O space, output it to the TAGBUS, and at the same time
/.

A signal l0AC (FIG. 1-112, FIG. 2-219) indicating access is sent to the effective address calculation section. l0AC
Since 219 indicates IO access, there is no need to calculate the top address of the next page (FIG. 7-79), so the timing control circuit 215 stops issuing instructions to calculate the top address of the next page. That is, signal 8TEA1 (seventh
Figure 72), PARW (Figure 7-74), VARTAB
(Figure 7-76) is set to "0".

3. In the case of I/O access, if the TAG information M/Io of the TAGA box 216 is “0”, the I/O
When indicating a Q access, this TAG information M/IO is sent to the timing control circuit 215, and like the memory map I/O, the timing control circuit 215 stops issuing an instruction to calculate the start address of the next page, and outputs a signal 5TEAI (
Figure 7-72), PARW (Figure y-74), VART
Set AB (Figure 7-76) to "o".

The TLB stores a virtual page number in its internal address comparison unit 12, a real page number in its data memory unit 14, protection information,
&1 Store PIO information.

An information processing device that employs a virtual storage system has a page table 31 and a page descriptor 32 on the main memory, and copies of information in these descriptors are stored in the TLB. In the present invention, the page descriptor 32 has MPIO information 323, and if this IO information is "1", it indicates that the page indicated by this page descriptor is mapped to the I/O space,
If it is “0”, it indicates that it is a memory space. This MP
IO information is also recorded in the TLB.

The effective address (virtual address) sent from the effective address calculation unit is the in-page offset (VAR
bits 1l-31) of V A RtD
12-31) (hereinafter abbreviated as virtual page number) with the virtual page number stored in the virtual address section of the TLB, and if there is a matching virtual page number, the TLB data corresponding to that virtual page number is The entry in the memory section is read out to the A box 15. In this data memory section,
Actual page numbers, protection information, and I/Q information are stored.

The real page number in the read RAR15 (bits 12-31 of RA) is the intra-page offset of the virtual address stored in VARII (VAR bit) O-3
1) to form a real address and address bus 1
11 and sent to the main memory controller.

The protection information (bit 15 of R, AR) in the RAR 15 is sent to the protection check mechanism 18. The protection check mechanism converts information in TTAGRI 6 into information such as access type decoded by decoder 17 and 1-LA.
It is checked whether the access is appropriate based on the protection information from R15 and the information such as the execution level from the instruction execution section, and if a contamination exception is detected, it is sent to the instruction execution section.

The I/Q information (AR bit 0) (hereinafter abbreviated as MPIO) in the RAR 15 is sent to the process 0 detection section. When MPIO is "1", the IO detection section sets the M/IO information of TTAGRI 6 to "0" to indicate the cI/O space and sends it to the main storage controller.

Also, when MI'IO is "1", I OAC is sent to EAU.
+=“l” to notify that it is a memory Mabutsu I/O.

The TTAG1/O information is sent at the same time as the real address is sent to the main memory controller. At this time, as mentioned above, in the case of memory Matsubuto I/O, M//Omtt& is "0"
is changed to indicate the I/O space, and the V/R information (a signal indicating whether the virtual address is a real address) is also changed to "0" to indicate the real address, and is output to the TBU8, which is then output to the main memory control unit. sent to.

The main storage controller accesses the memory space or I/O space based on the sent real address and tag information.

When the M/IQ information indicates Ilo, "O" outputs the real address as the I/O port address, and when the I/O information indicates memory space, "1" outputs the real address as the main memory address. , access memory space.

〔Effect of the invention〕

As explained above, by providing memory mapped I/O information in the page descriptor and storing it in the TLB, memory mapped I/O can be detected within the central processing unit, and the main memory The control device can access the input/output device by switching memory operand access mapped to the I/Q space to I/O access.

This solves the disadvantage of separating memory access and I/O access (an interleave configuration method is possible as a speed-up method for main storage devices, but this is difficult for input/output devices).

Also, the effective address calculation unit is mapped from TLB to memory map)
By receiving and receiving I/O information, disadvantages (in a central processing unit that uses a paging-based virtual memory system and can specify operand addresses in bytes, operands may span multiple pages; (memory map) The operation of the central processing unit differs between the I/O space and the memory space when spanning pages is solved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an address conversion section in an embodiment of the present invention, FIG. 2 is a block diagram of an effective address calculation section in an embodiment of the present invention, and FIG. FIG. 4 is a block diagram showing the configuration of the central processing unit in the embodiment of the invention, and FIG.
FIG. 6 is a diagram showing the information held by the tag bus in the embodiment of the present invention. FIG. 6 is a diagram showing the conversion from a virtual address to a real address in the embodiment of the present invention. FIG. 5 is a timing chart showing effective address calculation. 11...Virtual address register, 12.
...Associative memory, 13...Encoder,
14... Data memory, 15... Real address register, 16... Register, 17
...Decoder, 18...Protection check mechanism, 11o...Address bus, 111...
...Tag bus. Figure 3 (oL) Atlus change dust chi 7゛ru 9゜(b
) Page entry hand No. 4 Figure $ 5 Figure 77゛Bus J7 rhi' Figure 4 (a)〆 I/l〈Nζ〉

Claims (1)

[Claims] In a central processing unit that adopts a paging-based virtual memory system, an effective address calculation unit that generates an input/output control signal to switch between main memory access and I/O access and also generates an effective address, and an input/output control signal along with the real address. an address conversion indexing mechanism that stores an address and calls an input/output control signal along with a real address when converting an address using the effective address, and a main memory control device that switches between main memory access and I/O access using the input/output control signal, When calculating the effective address in the effective address calculating section, if the operand spans multiple pages and the input/output control signal read together with the real address from the address conversion indexing mechanism indicates main memory access, the start address of the next page is calculated. If the operand spans multiple pages and the input/output control signal read together with the real address from the address conversion indexing mechanism indicates an I/O access, the start address of the next page is not generated. An effective address calculation device characterized by: