JPH03142544A - Memory access system - Google Patents

Abstract

PURPOSE:To attain an access to a memory without switching the banks of a memory circuit by instructing the transfer of data covering the banks of the memory circuit to a 2nd CPU from a 1st CPU. CONSTITUTION:A CPU 101 has an access to a shared memory 104 via the switch of banks. A CPU 102 can have an access to the memory 104 as a continuous memory address space with no switch of banks. A bank switch circuit 103 inputs a command given from the CPU 101 and performs the switch of banks of the memory 104. In this case, a bank 0 is selected when '0' is written by the CPU 101 and then a bank 1 is selected with '1' written by the CPU 101 respectively. The memory 102 has a dual structure containing the memories 107 and 108 of both banks 0 and 1 and receives the accesses for each bank from the CPU 101 via the buffers 105 and 106. Then the memory 104 receives an access from the CPU 101 in a continuous space via a buffer 109.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory access method that can be accessed by a plurality of CPUs, and particularly to a memory access method that is accessed by bank switching.

[Prior Art] When a control program that is connected to a memory that is accessed by bank switching and is currently executed by a CPU is stored in one memory bank, while the control program is being executed, the other memory bank is You may want to access data in a memory bank. In such a case,
Simply switching the memory bank will make the CPU inoperable, so control is transferred to a bank switching program stored in another memory space, and that program allows you to switch memory banks and switch from other memory banks. It was operating to read data etc.

[Problems to be Solved by the Invention] However, in such a configuration, it takes a lot of time to transfer data between memory banks, and when a control program is stored in one memory bank, Since it takes a lot of time to save and restore control programs, switch control programs, etc., there is a problem that the efficiency of data transfer between memory banks decreases.

The present invention has been made in view of the above conventional example, and an object of the present invention is to provide a memory access method that allows access to data in a memory bank different from the memory bank currently being accessed without performing memory bank switching processing. purpose.

[Means for Solving the Problems] In order to achieve the above object, the memory access method of the present invention has the following configuration. That is, a memory circuit that can be accessed by at least two CPUs, a first CPU that can access the memory circuit by switching banks, a second CPU that can access the memory circuit in a continuous memory space, and a first CPU that can access the memory circuit by switching banks; 1 CPU to the second c
and instruction means for instructing the pU to transfer data across banks of the memory circuit.

[Operation] In the above configuration, the first CPU can access the memory circuit accessible by at least two CPUs by switching banks. On the other hand, the second CPU can access this memory circuit in a continuous memory space. In this way, by instructing the second CPU from the first CPU to transfer data across the banks of the memory circuit, the second CPU can normally transfer data within the memory circuit without being aware of the banks of the memory circuit. data transfer. As a result, the first CPU can move data of other memory banks into the currently accessible memory bank and access it without switching banks of the memory circuit.

[Embodiments] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[Description of Memory Circuit (FIGS. 1 and 2)] FIG. 1 is a block diagram showing the configuration of a memory circuit and its peripheral circuits in an embodiment.

In the figure, 101 is a CPU that accesses the shared memory 104 by switching banks, and 102 is a CPU that can access the shared memory 104 as a continuous memory address space without switching banks. A bank switching circuit 103 receives commands from the CPU 101 to switch banks of the shared memory 104. here,
Bank 0 is selected when "0" is written by CPU 101, and bank 1 is selected when "1" is written by CPU 101. Shared memory 104 includes memories 107 and 108 in bank O and bank 1.
It is a dual-port memory that is accessed by the CPU 101 via buffers 105 and 106 for each bank, and accessed by the CPU IO 2 via the buffer 109 in a continuous memory space.

A command board 110 latches commands from the CPU I O1 and outputs an interrupt signal IRQ205 to the CPU 102 in response to writing of the commands. 111 is the status register, the CPU
A status signal (BUSY) indicating the access state of the shared memory 104 is output to l0I. Similarly, 1
12 is a command boat from the CPU 102 to CPUl0I, and 113 is a status register, which are configured in the same manner as the command boat 110 and status register 111 described above, respectively.

121 is a ROM that stores the basic program of the CPU 10I, and 122 is a RAM used as a work area for the CPU 10I. 131 is a ROM storing a control program for the CPU 102; 132 is a CPU 102;
This RAM is used as a work area.

FIG. 2 shows a command board 110 (112) and a status register 111. (113), and FIG. 2 shows a schematic configuration of a command boat 110 and a status register 111.

In FIG. 2, 201 is a command buffer, and the CPU
A command from the CPU 10I (for example, an inter-bank data transfer command to be described later) is written by the chip select signal C31 from the CPU 101 and the write signal WRI.

In this way, when C3I and WRl are output simultaneously, the signal 20
6 becomes low level, and flip-flop 111 and flip-flop 202 are set at the same time. As a result, both the interrupt signal IRQ 205 and the busy signal 211 to the CPU 102 are set.

This causes an interrupt to the CPU 102, causing the CPU 10
The command stored in the command buffer 201 is read by the interrupt processing in step 2. By reading data from the buffer 201 by the CPU 102, the OR circuit 209
The output of the interrupt circuit 202 becomes low level, the interrupt circuit 202 is reset, and the signal IRQ205 becomes low level. Also,
At the end of the CPU 102 interrupt handling routine, the CPU
As O2 performs dummy write processing to the command buffer 201, the output of the OR circuit 210 becomes low level, the status register 208 is reset, and the busy signal 211 is turned off.

CS1. shown in FIG. WRI and RDI are both C
With the law-true control signal from PUl0I, CS2. W
R2 and RD2 are row active control signals from the CPU 102. Here, the CS signal is a chip select signal for selecting a command boat and status register, WR is a write signal, and RD is a read signal.

[Operation Description (Figs. 1 to 4)] Fig. 3 is a flowchart showing a data transfer processing instruction by the CPUl0I, and a control program for executing this processing is stored in the ROM 121 or the shared memory, for example, the bank O memory 107. has been done.

Now, considering the case where CPUl0I wants to transfer the data of bank 1 to bank O, it is checked in step S1 whether the busy signal 211 from the status register 111 is low level (ready), and if it is ready, the process advances to step S2 and the current Selected shared memory 10
4, write the transfer source and transfer destination memory addresses, the number of data to be transferred (for example, the number of bytes), etc. to a predetermined address in bank O, for example. Then, in step S3, an inter-bank transfer command is written to the command boat 110.

As a result, the interrupt circuit 202 is set, and the interrupt signal IRQ205 becomes high level to interrupt the CPU 102.

The flowchart in FIG. 4 shows the interrupt processing by the CPU 102 at this time.

When an interrupt occurs in the CPU 102, the process advances to step S11, where the command board 110 is read and a command from the CPU 10I is input. In step S12, this command is interpreted to see if it is an inter-bank data transfer command. If it is not an inter-bank data transfer command, the process advances to step S13, and processing corresponding to the command is executed.

If it is an inter-bank data transfer command, the process advances to step S14, and the transfer source,
Read the destination address and the number of data to be transferred.

Then, in step S15, data transfer processing between banks instructed by the command is executed. Note that for the CPU 102, this process is the same as normal data transfer process between memory addresses. When the data transfer process instructed in this way is completed, step S16
In step S17, it is checked whether the status register 113 is ready, and if it is ready, the CPU 101
Writes a response command to the command register 112. As a result, the C output from the command boat 112
The interrupt signal IRQ to PUl0I becomes high level.

In this way, when a response from the CPU 102 is detected in step S4 of FIG.
BUSY). At this time, also in step S18 in FIG.
is turned off. In addition, in step S4 of FIG. 3, an interrupt signal from the command boat 112 causes the CPU to
An interrupt may be generated in CPU 101, or CPU 1
01 detects this IRQ signal by a sense command and
A response from the PU 102 may also be detected.

As described above, according to this embodiment, the CPU 10I can also access data in memory banks other than the memory bank currently being accessed, without having to switch memory banks. This is particularly effective when the CPU 101 is currently executing the control program for memory bank 0 and wants to read data from memory bank 1.

[Effects of the Invention] As explained above, according to the present invention, even in a CPU that can be accessed by switching the memory circuit bank, a memory different from the memory bank currently being accessed can be accessed without performing memory bank switching processing. It also has the effect of allowing you to access bank data.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the schematic configuration of the memory circuit of the embodiment, FIG. 2 is a block diagram showing the configuration of the command boat and status register of the embodiment, and FIG. 3 is the output of inter-bank data transfer commands by the CPU 101. FIG. 4 is a flowchart showing command reception and inter-bank data transfer processing by the CPU 102. In the figure, 101, 102... CPU, 103... Bank switching circuit, 104... Shared memory, 105, 106
．． 109...Buffer, 110,112...Command register, 111,113...Status register, 121,131...ROM, 122,132...
RAM, 201... Command buffer, 202...
Interrupt circuit, 205... Interrupt signal (IRQ), 20
7 to 210: OR circuit, 211: busy signal. l・'4 Spear 3 Figure 4

Claims (2)

[Claims] (1) a memory circuit accessible by at least two CPUs, and a first memory circuit accessible by bank switching;
a second CPU that can access the memory circuit in a continuous memory space; and instruction means for instructing the first CPU to transfer data across banks of the memory circuit to the second CPU. A memory access method comprising: and (2) The instructions from the first CPU to the second CPU include the shared memory shared by the first and second CPUs and the memory access state by the first and second CPUs. 2. The memory access method according to claim 1, wherein the signal is transmitted via the shared memory based on a signal from a status register indicating the shared memory.