JPH04236631A - Information processor incorporatted with multiport random access memory - Google Patents

Abstract

PURPOSE:To improve the information processing capability and to reduce a failure of data transfer by accessing a multiport RAM to interrupt it by read or write and read to plural interrupt generation object addresses. CONSTITUTION:Selecting bits to select plural interrupt generation object addresses of a memory cell part based on input/output ports are stored in selecting registers 8, 9, and 10. Status bits to hold the states of respective interrupts are stored in status registers 11, 12, and 13 in accordance with contents of selecting registers 8, 9, and 10. Or selecting bits to select plural interrupt generation object addresses of the memory cell part of both of interrupt generation based on write from input/output ports and that based on read from them are stored in selecting registers 8, 9, 10, and 19. Consequently, an interrupt control circuit part controls interrupt generation in accordance with contents of these registers.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus incorporating a multi-port random access memory for temporarily storing data.

0002

[Prior Art] FIG. 7 shows this type of multi-port RAM (
1 is a block diagram showing a main part configuration of an information processing device incorporating a dual-port RAM as a multi-port random access memory; FIG. This information processing device 71 includes a CPU (central processing unit) 72 that performs calculations and controls for processing data, and a dual-port RAM 7 that temporarily stores data necessary for data processing by the CPU 72.
3. The CPU 72 is connected to the A port side which is the input/output port of the dual port type RAM 73, and the external information processing device 77 is connected to the B port side which is the input/output port of the dual port type RAM 73. The dual-port RAM 73 includes a memory cell section 76 having a plurality of memory cells for storing data, a memory control section 75 that controls the memory cell section 76, and a memory cell section 76.
The CPU 72 includes an interrupt control circuit section 74 that performs control to generate an interrupt to the CPU 72 upon access to the CPU 72 .

FIG. 8 is a diagram showing a conventional register configuration provided in the interrupt control circuit section 74, and 19 in the figure
, 20 and 21 are selection registers 22 for selecting the generation of an interrupt (selection of the target address for interrupt generation) by writing to addresses a, b, and c, respectively.
, 23, and 24 are status registers that hold the occurrence status of each interrupt. Status register 22
, 23, 24 are selection registers 19, 20, 21, respectively.
Holds the interrupt generation status corresponding to the interrupt generation target address.

FIG. 9 is a circuit diagram showing a conventional circuit configuration of the interrupt control circuit section 74. As shown in FIG. In FIG. 9, WR(B
) is the write signal from the B port, DB4 (A) is the 4th bit data bus signal of the A port data bus,
DB0(A) is the 0th bit data bus signal of the A port data bus, WRMODE is the write mode signal for writing, RDMODE is the read mode signal for reading, and IRQDPRAM indicates the occurrence of an interrupt. It's a signal. Other DB5(A),
DB1(A) and the like are also similar data bus signals. 19 corresponds to the selection register 19 in FIG. 8, and 22 corresponds to the status register 22 in FIG.

Next, the operation of the conventional example will be explained with reference to FIGS. 7 to 9. The information processing device 71 generates an interrupt to the CPU 72 upon access from the external information processing device 77 connected to the B port. The interrupt control circuit 74 controls the generation of this interrupt. First, this interrupt control circuit section 74
The interrupt generation conditions are determined by the write selection bits set in the selection registers 19, 20, and 21. An interrupt is generated when the IRQDPRAM signal becomes active. When an interrupt occurs, by reading the states of the status registers 22, 23, and 24, it is possible to know which interrupt has occurred, and based on this, processing is performed in accordance with the generated interrupt.

For example, in the circuit shown in the top dotted line block in FIG. 9, the decode signal 14 at address a and WR(
B) If the selection register 19 is set by the DB0 signal of logic 1, the status register 22 receives the set signal 16 based on the decode signal 25 and the set signal of the selection register 19.
is set by the IRQDPRAM signal to generate the IRQDPRAM signal. Note that the status register 22 is reset by a reset signal 29.

[0007]

[Problems to be Solved by the Invention] In an information processing device incorporating a conventional multi-port RAM having the above-described configuration, interrupts caused by access to the multi-port RAM for interrupting the central processing unit are This is performed only by writing to a plurality of interrupt generation addresses, which limits the complexity of processing caused by the generation of interrupts, making it difficult to improve information processing performance.

The present invention has been made to solve the above-mentioned problems, and by performing reading or writing and reading to multiple interrupt generation target addresses as an interrupt caused by accessing a multi-port RAM. An object of the present invention is to provide an information processing device with a built-in multi-port RAM that can improve information processing ability.

[0009]

[Means for Solving the Problems] A multi-port RAM built-in information processing device according to the present invention has a selection bit for selecting each of a plurality of interrupt generation target addresses of a memory cell section 76 by reading from an input/output port. Selection registers 8, 9, and 10 to store and status registers 11, 12, and 13 that store status bits to hold the status of each interrupt occurrence, or generation of an interrupt by writing from an input/output port and interrupt by reading. occurs in both memory cell sections 76
selection registers 8, 9, and 10 that store selection bits for selecting each of the plurality of interrupt generation target addresses;
, 19, 20, 21 in the interrupt control circuit section 74,
Interrupt generation is controlled according to the contents of each of the above registers.

0010

[Operation] The selection registers 8, 9, and 10 store selection bits for respectively selecting a plurality of interrupt generation target addresses of the memory cell section 76 by reading from the input/output ports. Status registers 11, 12, and 13 store status bits for holding respective interrupt generation states according to the contents of selection registers 8, 9, and 10. Or selection register 8, 9, 10, 19, 20
, 21 store selection bits for respectively selecting a plurality of interrupt generation target addresses of the memory cell section 76 for both generation of interrupts due to writing from input/output ports and generation of interrupts due to reading. Therefore, the interrupt control circuit section 74 controls the generation of interrupts according to the contents of each register.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing a register structure provided in an interrupt control circuit section in a dual-port RAM as a multi-port RAM according to an embodiment of the present invention. In FIG. 1, 8, 9, 10 are input/output ports B
Selection registers 11, 12, and 13 are selection registers 8, 11, 12, and 13, which store selection bits for selecting interrupt generation by reading from addresses a, b, and c, which are the interrupt generation target addresses of the memory cell unit 76 by ports, respectively. This is a status register that stores status bits for holding the occurrence states of interrupts corresponding to selection bits 9 and 10, respectively. In the case of FIG. 1, the selection bits are represented as selection 0, selection 1, and selection 2, and the status bits are represented as status 0, status 1, and status 2.

FIG. 2 is a circuit diagram showing the circuit configuration of this embodiment of the interrupt control circuit section 74 in FIG. In FIG. 2, components corresponding to those shown in FIG. 9 are designated by the same reference numerals, and their explanations will be omitted. In Figure 2, RD(B
) indicates a read signal from the B port, 8 indicates the selection register 8 in FIG. 1, and 11 indicates the status register 11 in FIG.

Next, the operation of this embodiment will be explained with reference to FIGS. 1, 2, and 7. When reading from address a in the memory cell section 76 by port B occurs,
First, the decode signal 14 of address a and the decode signal 15 of the RD(B) signal become active, and if the selection register 8 is set by the DB0 signal at this time,
The status register 11 is set by the set signal 16, which causes the IRQDPRAM signal to become active and generate an interrupt to the CPU 72. In this way, an interrupt is selected using the selection registers 8, 9, and 10, and when an interrupt occurs, the CPU 72 recognizes the interrupt occurrence state by reading the contents of the status registers 11, 12, and 13. , perform processing corresponding to each interrupt.

FIG. 3 shows an example of use in which interrupts are read from a plurality of interrupt generation addresses. One way to transfer data from the A port side to the B port side using the dual port type RAM 73 is to transfer data from the A port side to the address A (starting address of the dual port RAM 73) to the address C (dual port type RAM 73). There is a method in which data is written toward the final address of the port type RAM 73, and data is read from address a toward address c from the B port side. In this case, address b (dual port type RAM7
An interrupt is generated when the intermediate address of 3) is read from the B port side, and based on that signal, the area from address a to address b is used again and the remaining transfer data is written. address c from port
In response to the occurrence of an interrupt due to reading, the area from address (b+1) to address c is used again and the remaining data is written. Then, data is sequentially read from the B port. In this way, even when transferring data that exceeds the RAM capacity of the dual-port RAM 73, efficient data transfer can be performed without accidentally destroying the transferred data, and the information processing capacity can be improved.

FIG. 4 is a diagram showing a register configuration according to another embodiment. In FIG. 4, 19, 20, and 21 are input/output ports, for example, addresses a, b, and c to which interrupts are generated in the memory cell section 76 by writing from the B port.
Selection bits (selection 0, selection 1
, selection 2). That is, the selection registers 19, 20, and 21 are used to select whether or not to generate an interrupt by writing data to addresses a, b, and c. 8, 9, and 10 are, for example, addresses a and b where interrupts are generated in the memory cell section 76 by reading from the B port.
, c is a selection register that stores selection bits (selection 3, selection 4, selection 5) for selecting respectively. That is, the selection registers 8, 9, and 10 are used to select whether or not to generate an interrupt by reading data from addresses a, b, and c. 22, 23, 24 are selection registers 19, 20, 2
This is a status register that stores status bits (status 0, status 1, status 2) for holding the status of each interrupt occurrence based on the contents of 1. 11
, 12, and 13 are status bits (status 3, status 4, and status 5) for holding the state of each interrupt occurrence based on the contents of the selection registers 8, 9, and 10.

FIG. 5 is a circuit diagram of an interrupt control circuit section according to another embodiment. In FIG. 5, components corresponding to those shown in FIG. 2 or FIG. 9 are designated by the same reference numerals, and their explanations will be omitted. In FIG. 5, 19 corresponds to the selection register 19 in FIG. 4, and 22 corresponds to the status register 22 in FIG.

The operation of the interrupt control circuit shown in FIG. 5 is that the selection of interrupt generation due to data reading is the same as the operation explained in FIG. 2, and the selection of interrupt generation due to data writing is the same as the operation explained in FIG. , will be omitted here.

FIG. 6 shows an example of data transfer from the B port side to the A port side. First, from the B port side, data is written from address a (first address of dual-port RAM 73) to address c (last address of dual-port RAM 73), and an interrupt occurs due to writing to address b. At times, data in the area from address a to address b is read from the A port side. Further, in accordance with the occurrence of an interrupt due to writing to address c, data in the area from address (b+1) to address c is read from the A port side. When data is transferred in this way, the data before being rewritten will not be read out by mistake, the transfer can be performed with less load on the software, and the information processing capacity can be improved.

In the case of the other embodiment described above, in the data transfer using the dual port type RAM 73 from the A port side to the B port side shown in the above embodiment, efficient data transfer with few data transfer errors is possible. In addition to being able to transfer data, it is also possible to transfer data from the B port side to the A port side without accidentally reading data before it is rewritten.

In each of the above embodiments, the dual port RAM 73 may be incorporated into the information processing device 71 in a one-chip configuration. In addition, dual port type RAM
73 and the CPU 72 may also be incorporated into the information processing device 71 in a one-chip configuration.

[0021]

As described above, according to the present invention, there is a selection register storing selection bits for selecting each of a plurality of interrupt generation target addresses in a memory cell section by reading from an input/output port, and a selection register for each of the interrupt generation targets. Select a status register that stores status bits to maintain the state of the input/output port, or select multiple interrupt generation addresses in the memory cell section for both interrupt generation due to writing from the input/output port and interrupt generation due to reading. Since the interrupt control circuit is configured with a selection register that stores the selection bit for the interrupt, it is possible to have multiple addresses for which interrupts are generated by reading, or it is possible to generate interrupts for both writing and reading. It is possible to have multiple addresses as interrupt generation targets for both writing and reading, which makes it possible to control complex interrupts, thereby improving information processing ability. The effect is that efficient data transfer with fewer data transfer errors can be achieved during data transfer.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a register configuration according to an embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of an interrupt control circuit section according to an embodiment.

FIG. 3 is a diagram illustrating an example of use when interrupts are read from a plurality of interrupt generation target addresses in one embodiment.

FIG. 4 is a diagram showing a register configuration according to another embodiment of the invention.

FIG. 5 is a circuit configuration diagram of an interrupt control circuit section according to another embodiment.

FIG. 6 is a diagram illustrating an example of use in a case where interrupts caused by writing from a plurality of interrupt generation target addresses are used in another embodiment.

FIG. 7 is a block diagram showing the configuration of main parts of an information processing apparatus according to each of the above embodiments and a conventional example.

FIG. 8 is a diagram showing a register configuration according to a conventional example.

FIG. 9 is a circuit configuration diagram of an interrupt control circuit section according to a conventional example.

[Explanation of symbols]

8, 9, 10, 19, 20, 21 Selection register 11
, 12, 13 Status register 71 Information processing device 72 CPU (Central Processing Unit) 73 Dual-port RAM (Multi-port RAM
M) 74 Interrupt control circuit section 75 Memory control section 76 Memory cell section

Claims (1)

[Claims] 1. A memory cell section having a plurality of memory cells for storing data, a memory control section for controlling the memory cell section, and a memory cell section for generating an interrupt to a central processing unit upon access to the memory cell section. In an information processing device that includes a built-in multi-port random access memory that has an interrupt control circuit section that controls the input/output of data, and a plurality of input/output ports that input/output data, the above memory cell section is processed by reading from the input/output ports. A selection register that stores selection bits for selecting each of multiple interrupt generation target addresses, and a status register that stores status bits for holding the status of each interrupt generation, or interrupts written from input/output ports. The interrupt control circuit section is provided with a selection register that stores selection bits for selecting each of the plurality of interrupt generation target addresses in the memory cell section for both the generation of interrupts due to reading and the generation of interrupts due to reading, and according to the contents of each of the above registers. An information processing device with a built-in multi-port random access memory characterized by controlling interrupt generation.