KR950020095A - DMA controller improves data transfer capacity - Google Patents

DMA controller improves data transfer capacity Download PDF

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Publication number
KR950020095A
KR950020095A KR1019930027857A KR930027857A KR950020095A KR 950020095 A KR950020095 A KR 950020095A KR 1019930027857 A KR1019930027857 A KR 1019930027857A KR 930027857 A KR930027857 A KR 930027857A KR 950020095 A KR950020095 A KR 950020095A
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South Korea
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dma controller
register
data transfer
data
data buffer
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KR1019930027857A
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Korean (ko)
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KR950014186B1 (en
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김중배
이상민
김성국
한순섭
안희일
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양승택
재단법인 한국전자통신연구소
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

본 발명은 DMA 컨트롤러에 관한 것으로, 어드레스 통로를 분리하여 DMA 컨트롤러가 양쪽 메모리에 동시에 접근하게 하므로써 데이타의 전송능력을 개선시킨 DMA 컨트롤러에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA controller, and more particularly, to a DMA controller that improves data transfer capability by separating an address path and allowing a DMA controller to access both memories simultaneously.

상기 DMA 컨트롤러는 시스템 메모리 어드레스를 카운트하는 레지스터(14)와 데이타 버퍼 메모리 어드레스 카운트 레지스터(15)가 각각 공통의 버스에 연결되어 있다. 그리고 DMA 컨트를러의 동작을 제어하는 제어 레지스터(11)와, 에러 상태등을 저장하는 상태 레지스터(10)와, 데이타 전송도중 오류발생시 DMA 컨트롤러가 독립적으로 재시도를 행하기 위하여 초기값을 저장하는 임시 레지스터들(7, 8, 9)이 스텍구조를 이루고 워드를 카운트 하는 레지스터(13)가 공통의 버스에 연결되어 있고, 프로세서(I)와 정합되어 있고 데이타 버퍼(5)를 제어하고 내부상태 천이 제어및 필요한 신호를 생성하는 제어로직이 있다.In the DMA controller, a register 14 for counting system memory addresses and a data buffer memory address count register 15 are connected to a common bus. And a control register 11 for controlling the operation of the DMA controller, a status register 10 for storing an error state, and the like, and an initial value for the DMA controller to retry independently when an error occurs during data transfer. Temporary registers 7, 8, and 9 form a stack structure, and a register 13 for counting words is connected to a common bus, is matched with the processor I, controls the data buffer 5, and is internal. There is state transition control and control logic to generate the required signal.

상기한 구성에 의한 본 발명은 DMA 컨트롤러가 양쪽 메모리에 동시에 접근하여 많은 양의 정보의 데이타를 짧은 시간에 전송하고, 에러발생시 독자적으로 재시도를 할 수 있고, 데이타 버퍼를 DMA 컨트롤러와 분리하여 데이타 전송 쪽을 가변적이 되도록 하였다.According to the present invention, the DMA controller accesses both memories at the same time, transfers a large amount of information data in a short time, and can retry independently when an error occurs, and separates the data buffer from the DMA controller. The transmission side is made variable.

Description

데이타 전송능력을 개선한 디.엠.에이(DMA) 컨트롤러DMA controller improves data transfer capacity

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 구성을 나타내는 블럭도.2 is a block diagram showing a configuration of the present invention.

Claims (4)

중앙처리장치(1), 데이타를 저장하는 메모리(2), 상기 메모리(2)에 직접 데이타를 전송하는 DMA 컨트롤러(3), 데이타를 입력시키고 출력시키는 입출력 프로세서(3)가 시스템 버스에 공통으로 연결되는 컴퓨터 시스템에 있어서, 상기 시스템 버스에 접근하기 위하여 어드레스를 저장하고 카운트하는 시스템 메모리 어드레스 카운트 레지스터(14)와, 상기 테이타 버퍼 메모리에 접근하기 위하여 어드레스를 저장하고 카운트하는 데이타 버퍼 메모리 어드레스 카운트 레지스터(15)와, 상기 메모리(2)에 전송할 데이타량을 제어하기 위하여 워드를 저장하고 카운트하는 워드 카운트 레지스터(13)와, 상기 DMA 컨트롤러의 동작을 제어하는 제어 레지스터(11)와, 상기 DMA 컨트롤러가 데이타 전송시 발생하는 에러 상태를 저장하는 상태 레지스터(10)와, 상기 에러가 발생시 상기 프로세서(1)의 간섭없이 재시도를 하기 위한 임시 레지스터인 워드 레지스터(7), 데이타 버퍼 메모리 어드레스 레지스터(8), 시스템 메모리 어드레스 레지스터(9)와, 상기 프로세서(1)와 정합되어 있는 제어로직(12)으로 구성되어 있는 것을 특징으로 하는 데이타 전송능력을 개선한 DMA 컨트롤러.The central processing unit 1, the memory 2 for storing data, the DMA controller 3 for directly transferring data to the memory 2, and the input / output processor 3 for inputting and outputting data are common to the system bus. A connected computer system, comprising: a system memory address count register 14 for storing and counting an address for accessing the system bus, and a data buffer memory address count register for storing and counting an address for accessing the data buffer memory (15), a word count register (13) for storing and counting words to control the amount of data to be transferred to the memory (2), a control register (11) for controlling the operation of the DMA controller, and the DMA controller Register 10, which stores an error state that occurs during data transfer, and when the error occurs. Word register 7, data buffer memory address register 8, system memory address register 9, which are temporary registers for retrying without interfering with the processor 1, and control matched with the processor 1 A DMA controller with improved data transfer capability, comprising a logic (12). 제1항에 있어서, 데이타 전송도중 에러가 발생하여 재시도를 할 때, 상기 제어 레지스터(11)에 카운트레지스터를 구비하여 테이타 전송을 처음부터 다시 재시도하는 것을 특징으로 하는 데이타 전송능력을 개선한 DMA 컨트롤러.The data transfer capability of claim 1, wherein a count register is provided in the control register 11 to retry the data transfer from the beginning when an error occurs during data transfer and retrying. DMA controller. 제2항에 있어서, 상기 재시도를 위한 초기값은 어드레스와 워드 카운터의 임시 레지스터를 이용하는 것을 특징으로 하는 데이타 전송능력을 개선한 DMA 컨트롤러.3. The DMA controller of claim 2, wherein the initial value for retrying uses a temporary register of an address and a word counter. 제1항에 있어서, 데이타 버퍼(5)를 DMA 컨트롤러와 분리하여 데이타 전송폭이 가변적이 되는 것을 특징으로 하는 데이타 전송능력을 개선한 DMA 컨트롤러.The DMA controller according to claim 1, wherein the data transfer width is variable by separating the data buffer (5) from the DMA controller. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930027857A 1993-12-15 1993-12-15 Dma controller KR950014186B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100375816B1 (en) * 2000-10-10 2003-03-15 조용범 PCI bus controller having DMA interface and HPI of DSP

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100963140B1 (en) * 2008-11-27 2010-06-16 한국과학기술원 Direct memory access device and direct memory access method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100375816B1 (en) * 2000-10-10 2003-03-15 조용범 PCI bus controller having DMA interface and HPI of DSP

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