KR100375816B1 - PCI bus controller having DMA interface and HPI of DSP - Google Patents

PCI bus controller having DMA interface and HPI of DSP Download PDF

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KR100375816B1
KR100375816B1 KR10-2000-0059574A KR20000059574A KR100375816B1 KR 100375816 B1 KR100375816 B1 KR 100375816B1 KR 20000059574 A KR20000059574 A KR 20000059574A KR 100375816 B1 KR100375816 B1 KR 100375816B1
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dsp
hpi
controller
interface
dma
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KR20020028534A (en
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조용범
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조용범
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0024—Peripheral component interconnect [PCI]

Abstract

본 발명은 디지털신호 처리 프로세서(DSP)와 퍼스널컴퓨터의 인터페이스에 사용되는 PCI(PeripheralComponent Interconnect) 버스 컨트롤러에 있어서, HPI기능은 물론, DSP의 DMA(Direct Memory Acess) 기능을 제공하도록 하는 DSP의 HPI와 DMA 인터페이스를 가진 PCI 버스 컨트롤러를 개시한다. 본 발명은 DSP 프로세서와 퍼스널컴퓨터의 인터페이스로 사용되는 PCI 버스 컨트롤러에 있어서, 시스템 보드 측의 리소스 사용이나 플러그 및 플레이(Plug Play) 관련 명령을 처리하고 호스트에서 DSP로의 HPI 컨트롤을 담당하는 타겟 컨트롤러, 상기 타겟 컨트롤러 가 DSP의 HPI와 통신하도록 하는 타겟 백엔드 컨트롤러, DSP의 외부 메모리 인터페이스(External Memory Interface)로부터 오는 DMA 데이터를 호스트로 전송하는 마스너 컨트롤러, 데이터 전송 중에 에러가 발생했는지 검출하기 위해 짝수 패리티 비트를 생성하는 패리티 생성기로 구성되어 DSP의 HPI와 DMA 인터페이스를 가진 PCI 버스 컨트롤러를 제공한다. 본 발명에 따르면, DSP 프로세서와 PC의 인터페이스에 사용되는 PCI 버스 컨트롤러에 있어서, HPI기능은 물론, DSP의 EMIF 중 1개의 채널을 PCI 컨트롤러(FPGA)에 할당하여 데이터를 고속으로 전송할 수 있다.The present invention relates to a peripheral component interconnect (PCI) bus controller used for an interface between a digital signal processing processor (DSP) and a personal computer, and provides an HPI function of a DSP to provide a DSP direct memory access (DMA) function as well as an HPI function. Initiates a PCI bus controller with a DMA interface. The present invention relates to a PCI bus controller used as an interface between a DSP processor and a personal computer, comprising: a target controller that handles resource use or plug and play related commands on the system board side, and is in charge of controlling the HPI from the host to the DSP; A target backend controller that allows the target controller to communicate with the HPI of the DSP, a master controller that transfers DMA data from the DSP's external memory interface to the host, and even parity to detect if an error occurred during data transfer It consists of a parity generator that generates bits to provide a PCI bus controller with the DSP's HPI and DMA interface. According to the present invention, in the PCI bus controller used for the interface between the DSP processor and the PC, not only the HPI function but also one channel of the EMIF of the DSP can be allocated to the PCI controller (FPGA) to transmit data at high speed.

Description

디지털신호 처리 프로세서의 ＨＰＩ와 ＤＭＡ 인터페이스를 가진 ＰＣＩ 버스 컨트롤러{PCI bus controller having DMA interface and HPI of DSP}PCI bus controller having HPI and DMA interface of digital signal processing processor {PCI bus controller having DMA interface and HPI of DSP}

본 발명은 DSP(Digital Signal Processing) 프로세서와 퍼스널컴퓨터의 인터페이스에 사용되는 PCI(Peripheral Component Interconnect) 버스 컨트롤러에 관한 것으로, 특히 HPI기능은 물론, DSP의 EMIF(External Memory Interface) 중 1개의 채널을 PCI 컨트롤러(FPGA: Field Programmable Gate Array)에 할당하여 데이터를 고속으로 전송할 수 있는 DMA(Direct Memory Access) 기능을 제공하도록 하는 DSP의 HPI와 DMA 인터페이스를 가진 PCI 버스 컨트롤러에 관한 것이다.The present invention relates to a Peripheral Component Interconnect (PCI) bus controller used to interface a DSP (Digital Signal Processing) processor and a personal computer. In particular, one channel of the EMIF (External Memory Interface) of the DSP as well as the HPI function The present invention relates to a PCI bus controller having an HPI and a DMA interface of a DSP that is assigned to a field programmable gate array (FPGA) to provide a direct memory access (DMA) function to transfer data at high speed.

일반적으로 현재 사용중인 DSP용 PCI 컨트롤러는 DSP의 HPI 기능만을 제공하고, EMIF의 데이터 전송(DMA)을 지원하지 않기 때문에 데이터의 전송량이 현저히 낮았다. 또한, HPI를 인터페이스 하는데 있어서, 스트로부(STROBE#)신호가 너무 길어서(60ns), 데이터 전송 속도의 성능을 저하시키기도 한다.In general, the PCI controller for DSP currently provides only the HPI function of the DSP and does not support the data transfer (DMA) of the EMIF. In addition, when interfacing with HPI, the STROBE # signal is too long (60 ns), which may degrade the performance of the data transfer rate.

도 1에 있어서, 기존의 DSP용 PCI 버스 컨트롤러는 시스템 보드 측의 리소스 사용이나 플러그 및 플레이(Plug Play) 관련 명령을 처리하고 호스트에서 DSP로의 HPI 컨트롤을 담당하는 타겟 컨트롤러(Target Controller), 상기 타겟 컨트롤러가 DSP의 HPI와 통신하도록 하는 타겟 백엔드 컨트롤러(Target Backend Controller)로 구성되어 있다. 이러한 PCI 버스 컨트롤러는 DSP의 DMA 기능이 없으므로 고속의 데이터 전송이 불가능한 단점이 있다.In FIG. 1, a conventional PCI bus controller for a DSP is a target controller that processes resource usage or a Plug and Play related command on a system board side and is in charge of controlling an HPI from a host to a DSP. It consists of a Target Backend Controller that allows the controller to communicate with the DSP's HPI. These PCI bus controllers do not have the DSP's DMA capability, which makes them impossible to transmit data at high speeds.

본 발명은 HPI기능은 물론, DSP의 EMIF 중 1개의 채널을 PCI 컨트롤러(FPGA)에 할당해 데이터를 고속으로 전송할 수 있는 DMA 기능을 제공하도록 하는 것을 그 목적으로 한다.An object of the present invention is to provide a DMA function capable of transferring data at high speed by allocating one channel of DSP EMIF to a PCI controller (FPGA) as well as the HPI function.

상기 목적을 달성하기 위한 본 발명은 DSP 프로세서와 PC의 인터페이스로 사용되는 PCI 버스 컨트롤러에 있어서, 시스템 보드 측의 리소스 사용이나 플러그 및 플레이(Plug Play) 관련 명령을 처리하고 호스트에서 DSP로의 HPI 컨트롤을 담당하는 타겟 컨트롤러; 상기 타겟 컨트롤러가 DSP의 HPI와 통신하도록 하는 타겟 백엔드 컨트롤러; DSP의 EMIF로부터 전송되는 DMA 데이터를 고속으로 호스트에 전송하는 마스터 컨트롤러; 데이터 전송 중에 에러가 발생했는지 검출하기 위해 짝수 패리티 비트를 생성하는 패리티 생성기로 구성되어 DSP의 HPI와 DMA 인터페이스를 가진 PCI 버스 컨트롤러로 구성된 것을 특징으로 한다.In order to achieve the above object, the present invention provides a PCI bus controller that is used as an interface between a DSP processor and a PC, and handles resource use or plug and play related commands on the system board side, and controls HPI from the host to the DSP. A target controller in charge; A target back end controller for causing the target controller to communicate with the HPI of a DSP; A master controller which transmits DMA data transmitted from the EMIF of the DSP to the host at high speed; It consists of a parity generator that generates an even parity bit to detect whether an error has occurred during data transmission, and consists of a PCI bus controller having a DSP HPI and a DMA interface.

본 발명은 HPI기능은 물론, DSP의 EMIF 중 1개의 채널을 PCI 컨트롤러(FPGA)에 할당해 데이터를 고속으로 전송할 수 있는 DMA 기능을 제공하도록 하는 DSP의 HPI와 DMA 인터페이스를 가진 PCI 버스 컨트롤러를 제공한다.The present invention provides a PCI bus controller having the HPI and DMA interfaces of the DSP to provide a DMA function capable of transferring data at high speed by allocating one channel of the DSP's EMIF to the PCI controller (FPGA) as well as the HPI function. do.

도 1은 종래의 DSP용 PCI 버스 컨트롤러의 블록도.1 is a block diagram of a conventional PCI bus controller for DSP.

도 2는 본 발명에 따른 DSP의 HPI와 DMA 인터페이스를 가진 PCI 버스 컨트롤러의 블록도.2 is a block diagram of a PCI bus controller with the HPI and DMA interfaces of a DSP in accordance with the present invention.

도 3은 본 발명에 따른 PCI 버스 컨트롤러를 이용한 DSP와 호스트간의 데이터 전송 블록도.3 is a block diagram of data transmission between a DSP and a host using a PCI bus controller according to the present invention.

이하, 첨부한 도면을 참조하여 본 발명을 보다 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described the present invention in more detail.

도 2는 본 발명에 따른 DSP의 HPI와 DMA 인터페이스를 가진 PCI 버스 컨트롤러의 블록도이다.2 is a block diagram of a PCI bus controller with the HPI and DMA interfaces of a DSP in accordance with the present invention.

도 2에 있어서, 타겟 컨트롤러(Target Controller)(10)는 시스템 보드 측의 리소스 사용이나 Plug Play 관련 명령을 처리하기도 하고, 호스트에서 DSP로의 HPI 컨트롤을 담당하게 되는데 타겟 백엔드 컨트롤러(Target Backend Controller)(20)를 통해서 DSP의 HPI와 통신을 하게 된다. 마스터 컨트롤러(Master Controller)(30)는 DSP의 EMIF로부터 오는 DMA 데이터를 호스트로 전송하게 되는데, 전송할 호스트의 어드레스를 PCI 배열 컨트롤러(40)에서 가져와서 데이터를 전송하게 된다. 패리티 생성기(Parity Generator)(50)는 데이터 전송 중에 에러가 발생했는지 검출하기 위해 짝수 패리티 방식을 사용해서 데이터를 전송한다. PAR 핀으로 패리티의 값을 보내는데, 그 패리티는 어드레스 혹은 데이터가 전송되고 난 다음 클럭에서 보내지도록 설계해야 한다.In FIG. 2, the target controller 10 also handles resource use or Plug Play related commands on the system board side, and is in charge of controlling the HPI from the host to the DSP. The target backend controller ( 20) to communicate with HPI of DSP. The master controller 30 transmits DMA data coming from the EMIF of the DSP to the host. The master controller 30 receives the address of the host to be transmitted from the PCI array controller 40 and transmits the data. The parity generator 50 transmits data using an even parity scheme to detect whether an error has occurred during data transmission. The parity value is sent to the PAR pin, which should be designed to be sent at the next clock after the address or data is sent.

도 3은 본 발명에 따른 PCI 버스 컨트롤러를 이용한 DSP와 호스트간의 데이터 전송 블록도이다.3 is a block diagram of data transmission between a DSP and a host using a PCI bus controller according to the present invention.

도 3에 있어서, HPI를 통한 DSP의 컨트롤은 호스트가 원할 때만 행해지는 타겟(Slave)방식 전송이고, EMIF를 통한 대용량의 데이터 전송은 마스터(DMA)방식 전송이다. DSP 프로세서는 HPI기능은 물론, DSP의 EMIF중 1개의 채널을 PCI 컨트롤러(FPGA)에 할당하여 데이터를 고속으로 전송할 수 있는 DMA 기능을 제공한다. 또한, 읽기 및 쓰기의 양방향성 데이터 전송을 모두 지원하며, DMA의 소오스(Source) 및 데스티네이션(Destination) 메모리 장치는 DSP의 환경 설정에 따라 어느 장치든지 사용할 수 있다.In FIG. 3, the control of the DSP through HPI is a slave transmission performed only when the host desires, and the large data transmission through the EMIF is a master (DMA) transmission. In addition to the HPI function, the DSP processor provides one channel of the DSP's EMIF to the PCI controller (FPGA) to provide high-speed data transfer. In addition, it supports both read and write bidirectional data transfer, and DMA source and destination memory devices can be used by any device depending on the DSP configuration.

이러한 DSP의 HPI와 DMA 인터페이스를 가진 PCI 버스 컨트롤러를 제공함으로써 DSP 프로세서를 사용한 시스템에서 호스트와의 전송속도를 획기적으로 높힐수 있도록 할 수 있다.By providing a PCI bus controller with the DSP's HPI and DMA interface, it is possible to dramatically increase the transfer rate with a host in a system using a DSP processor.

본 발명은 상기 실시예에 한정되지 않으며, 많은 변형이 본 발명의 기술적 사상 내에서 당 분야의 통상적 지식을 가진 자에 의하여 가능함은 명백하다.The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit of the present invention.

상술한 바와 같이 본 발명에 따르면, DSP 프로세서와 PC의 인터페이스에 사용되는 PCI 버스 컨트롤러에 있어서, HPI기능은 물론, DSP의 DMA 기능을 제공할 수 있는 이점이 있다.As described above, according to the present invention, there is an advantage in that the PCI bus controller used for the interface between the DSP processor and the PC can provide not only the HPI function but also the DMA function of the DSP.

Claims (2)

DSP(Digital Signal Processing) 프로세서와 퍼스널컴퓨터의 인터페이스로 사용되는 PCI(Peripheral Component Interconnect) 버스 컨트롤러에 있어서,In the Peripheral Component Interconnect (PCI) bus controller used as an interface between a DSP (Digital Signal Processing) processor and a personal computer, 시스템 보드 측의 리소스 사용이나 플러그 및 플레이(Plug Play) 관련 명령을 처리하고 호스트에서 DSP로의 HPI 컨트롤을 담당하는 타겟 컨트롤러(Target Controller); 상기 타겟 컨트롤러가 DSP의 HPI와 통신하도록 하는 타겟 백엔드 컨트롤러(Target Backend Controller); DSP의 EMIF(External Memory Interface)로부터 전송되는 DMA(Direct Memory Access)데이터를 고속으로 호스트에 전송하는 마스터 컨트롤러(Master Controller); 데이터 전송 중에 에러가 발생했는지 검출하기 위해 짝수 패리티 비트를 생성하는 패리티 생성기(Parity Generator)로 구성된 것을 특징으로 하는 DSP 프로세서의 HPI와 DMA 인터페이스를 가진 PCI 버스 컨트롤러.A target controller that handles resource use or plug and play related commands on the system board side, and is responsible for controlling HPI from the host to the DSP; A target backend controller for allowing the target controller to communicate with the HPI of a DSP; A master controller which transfers direct memory access (DMA) data transmitted from an external memory interface (EMIF) of a DSP to a host at a high speed; A PCI bus controller with an HPI and DMA interface of a DSP processor comprising a parity generator that generates even parity bits to detect if an error occurred during data transmission. 삭제delete
KR10-2000-0059574A 2000-10-10 2000-10-10 PCI bus controller having DMA interface and HPI of DSP KR100375816B1 (en)

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