KR100427169B1 - Communication system and data transmission method thereof - Google Patents

Abstract

The present invention discloses a communication system and a data transmission method of the system. The system includes a source unit for storing first input data and generating a first interrupt signal when the data is pulled, a target unit for storing second input data and generating a second interrupt signal when the data is pulled, and a first interrupt signal. When the data is generated, the data stored in the source is directly transmitted to the target through the direct access bus. When the second interrupt signal is generated, the data stored in the target is transmitted directly to the source. When the data is completed, the third interrupt signal is generated. A direct access control unit and a control unit for enabling the operation of the direct access control unit when the first and second interrupt signals are generated from the source and target units, and disabling the operation of the direct access control unit when the third interrupt signal is generated. have. Accordingly, when data is transferred between the source (target) unit such as the general purpose serial bus unit and the target (source) unit such as the baseband unit, the burden on the controller is reduced because the data is transmitted directly without passing through the memory. This is improved.

Description

Communication system and data transmission method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication system, and more particularly, to a communication system capable of directly transmitting data between a source unit and a target unit without passing through a memory when transmitting and receiving data, and a data transmission method thereof.

In general, a communication system has been designed to directly exchange data with neighboring blocks and internal memory using a direct memory access (DMA) method to improve the performance of the system.

However, in order to implement the direct memory access method, the circuit configuration of the communication system becomes complicated, and there is a problem in that it is not easy to reduce the chip area at the time of integration.

Fig. 1 is a block diagram showing the configuration of a communication system using a conventional direct memory access method, and is composed of a radio unit 10, a control unit 20, and a host 30. The control means 10 includes a control unit 40, a memory 42 having an arbiter, a direct memory access control unit 44, a baseband unit 46, and a universal serial bus (USB) unit 48. Consists of.

The function of each of the blocks shown in FIG. 1 will be described below.

The radio unit 10 transmits and receives radio waves. The control unit 40 controls the overall operation of the memory 42, the direct memory access control unit 44, the baseband unit 46, and the universal serial bus unit 48. When generated, the operation of the direct memory access control unit 44 is enabled, and when the interrupt signal is generated from the direct memory access control unit 44, the operation of the direct memory access control unit 44 is disabled. The memory 42 reads / writes data to / from the system bus SB / direct memory access bus DB under the control of the control unit 40 / direct memory access control unit 44. The arbiter mediates the operation between the control unit 40 and the direct memory access control unit 44 when there is an access request from the control unit 40 while transmitting data with the direct memory access control unit 44. The direct memory access control section 44 is enabled under the control of the control section 40 when an interrupt signal is generated from the general purpose serial bus section 48 to directly access the data from the universal serial bus section 48 to the memory access bus DB. Directly transfer to the memory 42, and when the transfer of data from the universal serial bus unit 48 to the memory 42 is completed, generates an interrupt signal to the control unit 40. The baseband unit 46 stores and signals digital data input from the radio unit 10 and outputs the signal to the system bus SB. The baseband unit 46 stores and signals the digital data transmitted from the system bus SB. Output to 10). The universal serial bus unit 48 stores data input from the host 30 in a first-in first-out memory (not shown) and generates an interrupt signal to the controller 40 when the first-in first-out memory is full.

FIG. 2 is an operation flowchart showing a data transmission method from a host to a radio unit of the system shown in FIG.

First, data is transmitted from the host 30 to the universal serial bus unit 48 (step 100). That is, data from the host 30 is stored in a first-in first-out (FIFO) memory (not shown) in the universal serial bus section 48.

When data is extracted to the first-in, first-out memory in the universal serial bus unit 48, the universal serial bus unit 48 generates an interrupt signal to the controller 40 (step 110).

The controller 40 directly enables the memory access controller 44 (step 120). That is, the controller 40 sets the enable bit of the direct memory enable register (not shown) of the direct memory access controller 44 to an enabled state.

Data of the universal serial bus unit 48 is directly transmitted to the memory 42 through the memory access control unit 44 (step 130). In other words, the data of the universal serial bus unit 48 is not directly transmitted through the system bus SB under the control of the memory access control unit 44 but directly to the memory 42 through the direct memory access bus DB.

During the operation 130, when the read command is applied from the controller 40 to the memory 42, the arbiter 42 mediates the operation between the controller 40 and the direct memory access controller 44. For example, while the arbiter 42 first performs a read command from the controller 40, the direct memory access controller 44 stops the operation, and when the operation of the controller 40 is completed, the direct memory access controller Let 44 perform the operation.

When all the data of the universal serial bus unit 48 are transferred to the memory 42, the direct memory access control unit 44 generates an interrupt signal to the control unit 40 (step 140).

The controller 40 directly disables the memory access controller 44 (step 150). That is, the controller 40 sets the enable bit of the direct memory enable register (not shown) of the direct memory access controller 44 to the disabled state.

The controller 40 reads and stores the data of the memory 42 through the system bus SB (step 160).

The controller 40 transmits the stored data to the baseband unit 46 via the system bus SB (step 170). The data transmitted to the baseband section 46 is stored in a buffer (not shown) in the baseband section 46.

The data stored in the buffer of the baseband unit 46 is signal-processed and transmitted to the radio unit 10 (operation 180).

In the conventional communication system as described above, when the steps 120, 150, 160, and 170 are performed, intervention of the controller 40 is required. That is, the control unit 40 intervenes to transmit the data of the universal serial bus unit 30 to the memory 42 in steps 120 and 150, and the memory 42 of steps 42 and 170. Intervention is performed to transmit data to the baseband unit 46.

Similarly, even when data of the baseband unit 46 is transmitted to the universal serial bus unit 48, the intervention of the control unit 40 is required in step 4.

Therefore, the communication system using the conventional direct memory access method is a burden on the controller because data must be transmitted through the memory when data is transmitted from the universal serial bus unit to the baseband unit or data is transmitted from the baseband unit to the universal serial bus unit. There is a problem that the larger, and therefore, the system performance is lowered.

Of course, a high-performance control unit may be used for this purpose, but there is a problem in that the cost of the system is increased.

An object of the present invention is to provide a communication system and a data transmission method of the system that can reduce the burden on the control unit to improve the performance of the system.

A communication system of the present invention for achieving the above object is a source means for storing first input data and generating a first interrupt signal when the data is pulled, and generating a second interrupt signal when the second input data is stored and data is pulled Target means for transmitting the data stored in the source means directly to the target means through a direct access bus when the first interrupt signal is generated; and storing the data stored in the target means when the second interrupt signal is generated. Direct access control means for generating a third interrupt signal when data transmission is completed, and operation of the direct access control means when the first and second interrupt signals are generated from the source means and the target means. Enable the operation of the direct access control means when the third interrupt signal is generated; It characterized in that it comprises a control means for disabling.

In the data transmission method of the communication system of the present invention for achieving the above object, storing the input data in the source (target) means and generating a first interrupt signal when the data is pulled, direct access when the first interrupt signal is generated Enabling the operation of the control means, and directly transmitting the data stored in the source (target) means to the target (source) means, wherein the data stored in the source (target) means is transferred to the second (first interface) means Generating a second interrupt signal when all are transmitted, disabling the operation of the direct access control means when the second interrupt signal is generated, and transmitting data of the target (source) means to the target (source) means Characterized in that it comprises a step.

1 is a block diagram showing the configuration of a communication system using a conventional direct memory access method.

FIG. 2 is an operation flowchart showing a data transmission method from a host to a radio unit of the system shown in FIG.

3 is a block diagram of an embodiment showing a configuration of a communication system of the present invention.

FIG. 4 is an operation flowchart showing a data transmission method from the host to the radio section of the system shown in FIG.

Hereinafter, a communication system and a data transmission method of the present invention will be described with reference to the accompanying drawings.

Fig. 3 is a block diagram of an embodiment showing the construction of the communication system of the present invention, which is composed of a radio section 10, control means 20 ', and a host 30.

The control means 20 'is a control unit 60, a memory 62, a direct block access unit 64, a baseband unit 66 having an arbiter, and a universal serial bus unit 68 having an arbiter. Consists of.

The function of each of the blocks shown in FIG. 3 will be described below.

The radio unit 10 transmits and receives radio waves. The control unit 60 controls the overall operation of the memory 62, the direct block access control unit 64, the baseband unit 66, and the universal serial bus unit 68, and the interrupt signal from the universal serial bus unit 68 is controlled. When generated, the operation of the direct block access control unit 64 is enabled. When the interrupt signal is generated from the direct block access control unit 64, the operation of the direct block access control unit 64 is disabled. The memory 62 reads / writes data to / from the system bus SB under the control of the control unit 60. The direct block access control unit 64 transmits the data of the universal serial bus unit 68 to the baseband unit 66 through the direct block access bus DBB when enabled by the control unit 60, and interrupts when the transmission is completed. Generate a signal. The baseband unit 66 stores and signals data input through the direct block access bus DBB or system bus SB, and stores and signals data input through the radio unit 10. The arbiter of the baseband unit 66 mediates the operation between the control unit 60 and the direct block access control unit 64 when there is an access request from the control unit 60 while transmitting data with the direct block access control unit 64. The general-purpose serial bus unit 68 stores data transmitted from the host 30 in an internal first-in first-out memory (not shown), and generates an interrupt signal when data is pulled into the first-in first-out memory (not shown). The arbiter of the universal serial bus unit 68 arbitrates the operation between the control unit 60 and the direct block access control unit 64 when there is an access request from the control unit 60 while transmitting data with the direct block access control unit 64. do. For example, the arbiter of the baseband section 66 and the arbiter of the universal serial bus section 68 stop the operation by the request of the direct block access control section 64 while performing the operation by the access request of the control section 60. When the operation by the access request of the control unit 60 is completed, the operation by the request of the direct block access control unit 64 is resumed.

FIG. 4 is an operation flowchart showing a data transmission method from the host to the radio section of the system shown in FIG.

First, data is transmitted from the host 30 to the universal serial bus unit 68 (step 200). That is, data from the host 30 is stored in a first-in first-out (FIFO) memory (not shown) in the universal serial bus portion 68.

When data is extracted to the first-in, first-out memory in the universal serial bus unit 64, the universal serial bus unit 68 generates an interrupt signal to the controller 60 (step 210).

The controller 60 directly enables the block access controller 64 (operation 220). That is, the controller 60 sets the enable bit of the direct block enable register (not shown) of the direct block access controller 64 to the enabled state.

Data of the universal serial bus unit 68 is directly transmitted to the baseband unit 66 through the block access control unit 64 (step 230). In other words, the data of the general-purpose serial bus unit 68 is not directly transmitted through the system bus SB under the control of the block access control unit 64 but directly to the memory 62 through the block access bus DBB.

During the operation 230, if there is an access request from the controller 60 to the universal serial bus unit 68, the arbiter mediates the operation between the controller 60 and the direct block access controller 64.

When all data of the universal serial bus unit 68 are transferred to the memory 62, the direct block access control unit 64 generates an interrupt signal to the control unit 60 (step 240).

The controller 60 directly disables the block access controller 64 (operation 250). That is, the controller 60 sets the enable bit of the direct block enable register (not shown) of the direct block access controller 64 to the disabled state.

The data stored in the buffer (not shown) of the baseband unit 66 is transmitted to the radio unit (step 260).

In the case of performing the step 220 and the step 250 in the conventional communication system as described above, the intervention of the controller 60 is required.

Similarly, even when data is transmitted from the baseband unit 66 to the universal serial bus unit 68, two interventions of the control unit 60 are required.

In the communication system using the direct block access method of the present invention, since the data is transmitted from the universal serial bus unit to the baseband unit or the data is transmitted from the baseband unit to the universal serial bus unit without passing through the memory 62, the controller 60 ) Intervention is reduced compared to a communication system using a conventional direct memory access method.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

The communication system of the present invention and the data transmission method of the system are directly transmitted without passing through memory when data is transferred between a source (target) unit such as a universal serial bus unit and a target (source) unit such as a baseband unit. The burden is reduced, thereby improving the performance of the system.

Claims (5)

Source means for storing first input data and generating a first interrupt signal when the data is full; Target means for storing second input data and generating a second interrupt signal when the data is full; When the first interrupt signal is generated, the data stored in the source means is directly transmitted to the target means through a direct access bus.When the second interrupt signal is generated, the data stored in the target means is directly transmitted to the source means. Direct access control means for generating a third interrupt signal when data transmission is completed; And Control of enabling the operation of the direct access control means when the first and second interrupt signals are generated from the source means and the target means, and disabling the operation of the direct access control means when the third interrupt signal is generated. A communication system comprising means. The method of claim 1 wherein the source means And a first mediation means for arbitrating an operation by said direct access control means and an operation by said control means if there is an access request from said control means while storing said first input data. The method of claim 1, wherein the target means And second mediation means for arbitrating an operation by said direct access control means and an operation by said control means if there is an access request from said control means while storing said second input data. Storing the input data in the source (target) means and generating a first interrupt signal when the data is full; Enabling the operation of the direct access control means when the first interrupt signal is generated, and directly transmitting data stored in the source (target) means to the target (source) means; Generating a second interrupt signal when all data stored in the source (target) means are transmitted to the target (source) means; Disabling the operation of the direct access control means when the second interrupt signal is generated; And And transmitting the data of the target (source) means to the target (source) means. 5. The method of claim 4, further comprising: transmitting data from said source (target) means to said target (source) means And mediating the operation by the direct access control means and the operation by the control means if there is an access request from the control means.