JP2007140858A - Method for accessing memory, and device for accessing memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce power consumption in an operation for accessing a memory by suppressing bit variation which varies with time. <P>SOLUTION: A master device 100, which is provided with a memory-access reordering part 102 which reorders data-writing order so that a humming distance between transmission data and next transmission data may become minimum, accesses a memory 200 according to the data which are sorted so that a humming distance between transmission data and the next transmission data may become minimum. Instantly, when memory access which the master device requires is generated, sequential access is not made. Before accessing the memory 200, data to be accessed are once buffered in the memory-access order reordering part 102. The memory-access order reordering part 102 changes access order, so that a humming distance between data after/before access may become small, from among accumulated several access data. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a memory access method and a memory access device, and more particularly to improvements such as external memory access, internal memory access, and CPU access that can reduce power consumption.

  In recent years, the amount of data to be processed has increased due to the increase in the transmission rate of portable devices and the increase in the number of functions of terminals, and the demand for high-speed access to a large amount of data with a large-capacity external memory has increased.

  On the other hand, with the miniaturization of the LSI process that supports higher functionality of the terminal, the load capacity inside the LSI becomes smaller, the difference from the external load capacity widens, and the proportion of IO power in the power consumption of the entire LSI increases. It is coming.

Patent Document 1 describes a program conversion method that rearranges the order of instructions so that addressing from an ALU is performed at a Hamming's distance. Further, Patent Document 2 describes a program conversion device that reduces the instruction code toggle and reduces power consumption by determining the next code with a small Hamming distance by exclusive OR with the previous instruction. A signal processing device is described in which a conversion circuit that minimizes the Hamming distance is provided to reduce power consumption. Further, Patent Document 4 describes a semiconductor memory device that is accessed according to a code sequence in which the hamming distance between adjacent addresses is 1.
JP-A-9-114676 JP 2002-229802 A JP-A-5-135187 JP-A-8-63969

  However, in such conventional memory access operations, there is no concept of suppressing bit changes that change over time, and when the master device needs to access the memory, it is performed by a sequential access method. It has been broken. For this reason, as described below, there is a problem that the effect of reducing the power consumption of the memory access operation is not sufficient.

  FIG. 17 is a diagram for explaining a difference between an internal load capacity and an external load capacity of an LSI in recent years.

In FIG. 17, 10 is a master device in the LSI, 20 is an external memory externally connected to the master device 10, and the master device 10 and the external memory 20 are connected by a data line 30. The master device 10 includes an internal buffer 11 and an IO buffer 12. The internal buffer 11 is an example of an internal circuit for expressing the load capacity inside the LSI, and the IO buffer 12 is an example of an external memory IF (interface) -IO for expressing the external load capacity. The external memory 20 has an IO buffer 21 that receives data from the master device 10. The load capacitance C _IN inside the LSI symbolically indicated by the internal buffer 11 is several tens [fF], whereas the load capacitance C _OUT outside the LSI (in this case, the data line 30) is several tens [pF]. It is. In recent fine processes, the internal load capacity of an LSI is about 1/1000 of the external load capacity of the LSI. Here, since the current consumption of the CMOS circuit is proportional to the load capacity to drive, the current consumption of one IO buffer 12 is about 1000 times larger than the current consumption of one internal buffer 11.

  In addition, due to the recent increase in data processing amount, high speed is required for access to the external memory 20, and the data line 30 has an operating frequency exceeding 200 MHz, and the number of lines is 32 bits or more. . Since the consumption current of the CMOS circuit is proportional to the frequency, the IO consumption current increases even when the frequency becomes high, and the IO consumption current also increases as the number of terminals increases.

  At present, the reduction in current consumption of portable devices for realizing portability of portable devices is largely due to miniaturization of semiconductor processes.

  To summarize the above, in recent years, the consumption current of IO has reached half of the consumption current of the entire LSI, and how to suppress the consumption current of IF-IO with the external memory is an important issue to be solved. It has become.

  FIG. 18 is a conceptual diagram illustrating a write operation in conventional memory access. In FIG. 18, a master block 40 such as a master device or a CPU accesses a memory device or memory block 42 via a write data bus and an address data bus 41.

  The conventional memory access operation is performed by a method of performing sequential access when the master device 40 needs to access the memory.

  FIG. 19 is a diagram showing the change over time of write data in the data bus 41. In FIG. 19, 51 is the first data in the transfer order in the data buffer section, 52 is the second data in the transfer order in the data buffer section, 53 is the third data in the transfer order in the data buffer section, and 54 is the fourth transfer order in the data buffer section. It is data. The transfer order No. 1 data 51 “01101101” changes to transfer order No. 2 data 52 “10000010”, further changes to transfer order No. 3 data 53 “01001100”, and finally changes to transfer order No. 4 data 54 “11001010”. Change. The shaded bits shown in FIG. 19 are bits that have changed from the previous state. In the example of FIG. 19, a total of 15 bits change between the write data 51 to 54. Bit changes in the bus line between memories lead to an increase in power consumption of the bus line. As described above, in the conventional memory access method, only the memory access required by the master device 40 is sequentially performed, and there is no concept of suppressing the bit change that changes with time.

  The present invention has been made in view of the above points, and provides a memory access method and a memory access device capable of reducing power consumption of a memory access operation by suppressing bit changes that change with time. The purpose is to provide.

  The memory access method of the present invention includes a step of rearranging the data writing order so that the Hamming distance between the transfer data and the next transfer data is minimized, and a step of accessing the memory by the rearranged data.

  The memory access method of the present invention includes a step of rearranging the address order so that the Hamming distance between the first address and the second address is minimized, and a step of accessing the memory by the rearranged address. .

  The memory access method of the present invention includes a step of rearranging the order of the memory output data so that a Hamming distance in the time series of read data output from the memory is minimized, and the read data returned from the memory Rearranging to the read order before rearrangement.

  The memory access method of the present invention includes a step of rearranging the order of the memory output data so that a hamming distance in time series of read data output from the memory is minimized, and the information rearranged on the memory side is a memory interface. And transferring the read data returned from the memory to the read order before the rearrangement using the information transferred to the function and rearranged on the memory side.

  The memory access method of the present invention includes a step of rearranging the read address order so that a hamming distance in the time series of addresses for read control is minimized, and read data returned from the memory before Rearranging to the reading order.

  A memory access device according to the present invention is a memory access device that controls writing to a memory, and includes a rearranging unit that rearranges the data writing order so that a hamming distance between transfer data and next transfer data is minimized. Take the configuration.

  The memory access device according to the present invention includes a rearrangement unit that rearranges the read order of the read data of the memory side output so as to minimize the time-series Hamming distance of the read data of the memory side output, and returns from the memory. The read data order restoring means for rearranging the read data thus read back to the read order before rearrangement in the rearranging means is adopted.

  The memory access device according to the present invention includes a rearrangement unit that rearranges the order of the memory output data so that a Hamming distance in time series of read data output from the memory is minimized, and information rearranged on the memory side And a rearrangement information transmitting means for transmitting the read data to the memory read data receiving side, and using the information rearranged on the memory side, read data returned from the memory is converted to the data before the rearrangement. A configuration is provided that includes read data order restoring means for rearranging the data in the read order.

  The memory access device according to the present invention includes: a reordering unit that reorders read addresses so that a hamming distance in a time series of addresses for read control is minimized; and the read data returned from the memory The read data order restoring means for rearranging to the read order before rearrangement in the means is adopted.

  The memory access device of the present invention includes a determination unit that determines whether all or part of the data array of the transfer data and the next transfer data match, and a transmission unit that performs data transfer by transmitting the match information to the memory side The structure provided with.

  The memory access device according to the present invention includes reservation data storage means for storing in advance, as reservation data, all or a part of bit changes of the bit array of transfer data and next transfer data, and the bit change coincides with the reservation data. And a transmission unit for transferring data by transmitting the coincidence information to the memory side.

  According to the present invention, the number of bit changes of access data can be reduced, and the power consumption of the memory access operation can be reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram showing a memory access method according to Embodiment 1 of the present invention. This embodiment will be described by taking memory access of write data as an example.

  In FIG. 1, a master device 100 such as a CPU includes a data buffer 101 that stores generated memory access data, and a memory access order rearranging unit 102 that rearranges the writing order of the generated memory access data. The master device 100 controls writing to a memory device or memory block (hereinafter referred to as a memory) 200 by the write data bus and the address data bus 103.

  The memory access order rearrangement unit 102 rearranges the data write order so that the hamming distance between the transfer data and the next transfer data is minimized.

  Hereinafter, a memory access operation of the memory access method configured as described above will be described.

  FIG. 2 is a diagram showing a time change of write data in the data bus 103. FIG. 2 corresponds to the time change diagram of the write data of FIG. 19 of the conventional example.

  In FIG. 2, 301 is the first data in the transfer order in the data buffer section, 302 is the second data in the transfer order in the data buffer section, 303 is the third data in the transfer order in the data buffer section, and 304 is the fourth transfer order in the data buffer section. Both are data after rearrangement of the data write order by the memory access order rearrangement unit 102.

  Focus on the write data during the write operation. The transfer order data 301 to 304 are referred to as write data 301 to 304 during a write operation. When access to the memory 200 generated by the master device 100 is necessary, the write data 301 is once stored in the memory access order rearrangement unit 102. In the memory access order rearrangement unit 102, the data writing order is rearranged so that the Hamming distance between the transfer data and the next transfer data is minimized, and the rearranged data is output to the memory 200. Similarly, the write data 302 to 304 are also stored once in the memory access order rearrangement unit 102, and the memory access order rearrangement unit 102 stores the data so that the hamming distance between the transfer data and the next transfer data is minimized. Are rearranged, and the rearranged data is output to the memory 200.

  Specifically, the rearrangement of the data write order in which the hamming distance between the transfer data and the next transfer data becomes the smallest is specifically, when the transfer data and the next transfer data are compared, each bit change ( The memory access transfer order is rearranged so that “0” → “1” / “1” → “0”) is minimized. For example, in FIG. 2, the transfer order data “10000010” that was originally located after the transfer order first data “01101101” is rearranged to the position of the transfer order fourth data. Further, the transfer order third data “01001100” and the transfer order fourth data “11001010” before rearrangement are respectively moved forward. By this rearrangement, the transfer order first data 301 “01101101” changes to transfer order second data 302 “01001100”, changes to transfer order third data 303 “11001010”, and finally transfer order fourth data 304. It changes to “10000010”.

  As a result, as shown in the shaded area in FIG. 2, the changed bits from the previous state are 7 bits in total between the write data 21 to 24. Compared with a total of 15 change bits of the conventional example shown in FIG. 19, the number of bit changes of the access data can be reduced by 8 bits from 15 to 7. By reducing the number of bit changes in access data, the power consumption of the memory access operation can be reduced.

  As described above, according to the first embodiment, the master device 100 includes the memory access order rearrangement unit 102 that rearranges the data writing order so that the hamming distance between the transfer data and the next transfer data is minimized. The memory 200 is accessed by data rearranged so that the Hamming distance between the transfer data and the next transfer data is minimized. That is, first, when a memory access required by the master device occurs, data to be accessed is temporarily buffered in the memory access order rearrangement unit 102 before accessing the memory 200 without performing sequential access. The memory access order rearrangement unit 102 rearranges the access order so that the Hamming distance of the data before and after accessing is reduced from the accumulated access data for several times. As is clear from comparison between FIG. 2 and FIG. 19, in this embodiment, the total number of bit changes generated between the write data 301 to 304 is 7 bits. In the case of FIG. In comparison, the total number of changed bits can be reduced by 8 bits. Reduction of the bit change of the bus line between the memories leads to reduction of power consumption of the bus line.

  FIG. 3 is a diagram for explaining the low power consumption effect of the present embodiment. As shown in FIG. 3, conventionally, the consumption current of IO occupies half of the consumption current of the entire LSI, and the consumption current of IO has tended to increase. On the other hand, in this embodiment, the order of data writing is rearranged in advance in an LSI that requires only low current consumption that is not comparable to IO (about 1000 minutes). For large IOs, IO consumption current is greatly reduced by avoiding bit changes as much as possible. As a result, the power consumption of the memory access operation of the entire LSI can be reduced.

(Embodiment 2)
In the second embodiment, attention is paid to the bit change amount of the address in addition to the bit change amount of the write data of the first embodiment. The hardware configuration is the same as in FIG. However, the memory access order rearrangement unit 102 according to the second embodiment rearranges the write order so that the Hamming distance is minimized by combining the write data and the address.

  FIG. 4 is a diagram showing a time change of the data bus including the data line and the address line, and is based on the conventional memory access method shown in FIG.

  As shown in FIG. 4, in the conventional example, the time change of the data bus 41 is a combination of the data lines and the address lines arranged in the order of access generated from the master device 40 to the memory 42 in FIG. As described in the first embodiment, for the write data, 15 bits change between the address and the write data 61 to 64 in total. For the same reason, the address changes in total 8 bits, and the total of the change bits is 23 bits.

  FIG. 5 is a diagram showing a time change of the data bus combining the data line and the address line in the memory access method according to the second embodiment of the present invention, and the access order is changed so that the Hamming distance becomes small. This shows how the data bus changes over time.

  As shown in FIG. 5, in the second embodiment, the access order is changed so that the Hamming distance of the data including the data line and the address line before and after the access is reduced. The rearranged transfer order addresses and write data 401, 402, 403, and 404 in FIG. 5 are rearranged in the order of the write data 61, 63, 62, and 64 in the forward order before rearrangement in FIG. .

  In the case of FIG. 4, the total number of bit changes generated between the address and the write data 61 to 64 is 23 bits, but in the case of FIG. 5 after the order change, the total number of changed bits is It is 13 bits, and the bit change for 10 bits can be reduced.

  As described above, according to the second embodiment, the memory access order rearrangement unit 102 includes not only the data but also the address, including the address line, by setting the bit change amount including the address as the determination target of the access order rearrangement. Thus, the power consumption of the memory access operation can be reduced.

(Embodiment 3)
In the third embodiment, attention is paid to the selection of the low power consumption effect and the transfer wait time by selecting the data buffer amount. The third embodiment is a memory access method with a selection function for processing time. The hardware configuration is the same as in FIG.

  The address and write data shown in FIG. 5 indicate the state of data temporarily stored in the data buffer unit, and each data buffer constituting the data buffer unit includes the address and write data 401 to 404 shown in FIG. It can describe using the same code | symbol.

  FIG. 6 is a diagram showing a data buffer unit of the memory access method according to the third embodiment of the present invention. In FIG. 6, the data buffer unit includes data buffers 501 to 504. The data buffer 504 in the data buffer unit is not used.

  In FIG. 5, after the memory accesses generated in the master device are accumulated four times, the data that minimizes the Hamming distance from the previous transfer data is selected from the four data buffers 401 to 404 in the data buffer unit. It was. As a result, bit changes can be reduced, and the power consumption of the bus line can be reduced. However, since data is moved on the data buffer, the processing time (transfer wait time) slightly increases. The low power consumption effect and the transfer wait time are in a trade-off relationship. Therefore, in the third embodiment, the mode can be selected depending on which of the low power consumption effect and the transfer wait time is more important. Specifically, it has a mode selection function for selecting the number of data candidates whose rearrangement of the writing order is considered so as to minimize the Hamming distance and the overhead of the transfer time required to secure the rearrangement candidate data. . This mode selection function increases the number of data buffers used in the present memory access method when increasing the low power consumption effect, and decreases the number of data buffers used when the processing speed is important. This mode selection can be adaptively changed by user designation or data amount.

  In the example of FIG. 6, the data buffer 504 is not used. By making the data buffer 504 unused, the memory access that can be accumulated is three times, and data that minimizes the Hamming distance from the previous transfer data is selected from the three data buffers 501 to 503 in the data buffer unit.

  Therefore, compared with the case of FIG. 5, the number of data selection candidates that minimizes the Hamming distance from the previous transfer data is reduced, so the effect of low power consumption is reduced, but the amount of data to be accumulated is reduced to the memory. The transfer can be completed quickly. This will be described in more detail with reference to FIG.

  FIG. 7 is a diagram showing a time change of the data bus in which the data line and the address line are combined without using the data buffer 504.

  As the data bank area (in this case, the data buffer) is expanded, the choice of the next transfer data increases and the change bits of the transfer data can be suppressed, but the transfer weight increases in proportion to this. Therefore, the third embodiment has a function of specifying a data bank area to be used. For example, as shown in FIG. 7, the bit arrangement closest to the previous transfer data is selected in the three-stage bank. As a result, high-speed transfer can be performed for one stage bank with less transfer time overhead.

  As described above, according to the third embodiment, by changing the number of times that memory accesses can be accumulated, the effect of low power consumption and the wait time for transfer to the memory can be selected as necessary. .

(Embodiment 4)
In the fourth embodiment, part or all of the data to be accessed to the memory is provided in advance on both the master device side and the memory side.

  FIG. 8 is a block diagram showing a memory access method according to Embodiment 4 of the present invention. In the description of the present embodiment, the same components as those in FIG.

  In FIG. 8, a master device 600 such as a CPU further includes a reservation data storage unit 601 that stores reservation data for which bit changes are reserved in advance, and a coincidence detection unit 602 that detects coincidence between the reservation data and the bit arrangement.

  The reserved data reserves all or part of the bit arrangement of the transfer data and the next transfer data in advance. The reservation data 601 is preferably a reservation for a data string having a high appearance frequency. As an example of the reservation data, there is reservation data 601A of the lower 4 bits “1100” of the write data as shown in FIG.

  The coincidence detection unit 602 detects whether all or part of the bit arrangement of the transfer data and the next transfer data matches the reserved data. When the bit change matches the reserved data, the next transfer data Is the reserved data, it is notified to the memory 200 side by the coincidence detection signal 603. Therefore, when the bit change matches the reserved data, the match detection signal 603 is output to the memory 200, so that the bit arrangement from the transfer data to the next transfer data is not changed.

  Hereinafter, a memory access operation of the memory access method configured as described above will be described.

  The case of the address and write data 401 to 404 after the processing of the second embodiment shown in FIG. 5 is taken as an example. The lower 4 bits “1100” of the address and write data 402 match the reserved data 601A “1100” (FIG. 9). At this time, in the next access of the address and write data 401, a normal access operation is performed except for the lower 4 bits of the address and write data 402. The coincidence detection signal 603 is transmitted from the coincidence detection unit 602 to the memory 200 instead of the lower 4 bits “1100” of the address and write data 402 remaining in the state of the address and write data 401. The coincidence detection signal 603 is a signal output when the bit arrangement from the transfer data to the next transfer data matches the reserved bits.

  On the memory 200 side, it is identified that the lower 4 bits of the data are the contents “1100” of the reserved data 601A reserved in advance.

  Here, when dealing with a plurality of reservation data, for example, by providing an ID number for each reservation data and transmitting the ID number as the coincidence detection signal 603, it is possible to deal with a plurality of reservation data.

  As described above, according to the fourth embodiment, it is possible to suppress the bit change rate between the memories and to realize further lower power.

(Embodiment 5)
The fifth embodiment is an example for explaining the data writing order rearranging method described in the first embodiment in more detail together with the following sixth embodiment. The hardware configuration is the same as in FIG. However, the memory access order rearrangement unit 102 according to the fifth embodiment compares the previous transfer data with all the next transfer candidate data, and selects the next transfer data having the shortest Hamming distance from the previous transfer data.

  The time change of the data bus combining the data line and the address line in FIG. 4 will be described as an example.

  In the memory access order rearrangement unit 102 according to the fifth embodiment, the data for which the next transfer becomes the minimum hamming distance is selected from all the transfer candidate data with respect to the previous transfer data. In the example of FIG. 4, data having the shortest Hamming distance is selected from the data 62 to 64 with respect to the previous access data 61 that has already been accessed.

  As described above, according to the fifth embodiment, the specific rearrangement function for comparing the previous transfer data with all the next transfer candidate data and selecting the next transfer data having the shortest Hamming distance from the previous transfer data is provided. Provided.

(Embodiment 6)
The sixth embodiment is also an example for explaining the data writing order rearranging method described in the first embodiment in more detail. The hardware configuration is the same as in FIG. However, the memory access order rearrangement unit 102 according to the sixth embodiment determines the transfer order with the smallest bit change through the combination of all the transfer candidate data transfer orders, and outputs it to the memory 200.

  The time change of the data bus combining the data line and the address line in FIG. 4 will be described as an example.

  The memory access order rearrangement unit 102 according to the sixth embodiment determines the transfer order that minimizes the amount of bit change through all the transfer data remaining in the data buffer, including the selection of the next transfer data for the previous transfer data. . In the example of FIG. 4, through all combinations of data transfer orders of transfer candidates, the transfer order with the smallest bit change is determined, and through the access for four times of data 61 to 64 including the previous access data 61 that has already been accessed, The order of accesses with the smallest total bit change is determined, and the next access data is determined from the data 62-64.

  Thus, according to the sixth embodiment, a specific rearrangement function for determining the transfer order with the smallest bit change is provided through all combinations of the data transfer orders of the transfer candidates.

(Embodiment 7)
The seventh embodiment is an example for specifically explaining the initial processing method together with the following eighth embodiment.

  In the seventh embodiment, paying attention to the processing in the initial state when the data buffer is empty, the first memory access that occurs in the master device with the data buffer being empty is immediately output to the memory. After the next memory access occurs, it is stored in the data buffer.

That is,
1. A step of outputting the first memory access in the master device to the memory from the state where the next transfer candidate data buffer is empty;
2. Next, the memory access method includes the steps of accumulating in the next transfer candidate data buffer section from the memory access occurring in the master device.

  When the data buffer becomes full by the above process, memory access with the smallest bit change is performed by the fifth embodiment, the sixth embodiment, or another method.

  As described above, according to the seventh embodiment, the processing method at the initial stage is specifically provided, and when implemented together with the first to sixth embodiments, the number of data bit changes can be reduced. The power consumption of the memory access operation can be reduced.

(Embodiment 8)
The eighth embodiment is also an example for specifically explaining the initial processing method.

  In the eighth embodiment, attention is paid to the processing of the initial state when the data buffer different from that of the seventh embodiment is empty, and the data buffer unit starts from the memory access that occurs first in the master device when the data buffer is empty. To accumulate. In other words, this is a memory access method in which the next transfer candidate data buffer unit is stored in the next transfer candidate data buffer unit from the memory access that occurs first in the master device while the next transfer candidate data buffer unit is empty.

  When the data buffer becomes full, memory access with the smallest bit change is performed by the fifth embodiment, the sixth embodiment, or other methods.

  Preferably, the effect of the sixth embodiment can be increased by combining the eighth embodiment with the sixth embodiment.

(Embodiment 9)
The ninth embodiment is an example for specifically explaining a processing method at the end of a series of memory accesses together with the following tenth embodiment.

  In the ninth embodiment, focusing on processing at the end of continuous memory access batches, when the end of continuous memory access batches is detected, such as when a certain time is available, until the accumulated data in the data buffer becomes empty The output to the memory is performed by the fifth embodiment, the sixth embodiment, or other methods. That is, after a certain free time is detected after the access to the memory is stopped, the memory access method of the first to eighth embodiments is repeated to transfer all the remaining data in the next transfer candidate data buffer to the memory. Output. For example, the rearrangement method of the fifth embodiment or the sixth embodiment is repeated to output all the remaining data in the data buffer to the memory.

  As described above, according to the ninth embodiment, a processing method at the end of a series of memory accesses is specifically provided, and when implemented together with the above-described first to eighth embodiments, the number of data bit changes is reduced. Therefore, the power consumption of the memory access operation can be reduced.

(Embodiment 10)
The tenth embodiment is also an example for specifically explaining a processing method at the end of a series of memory accesses.

  In the tenth embodiment, attention is paid to the processing at the end of the continuous memory access batch, which is different from the ninth embodiment, and the next memory access is performed in the master device regardless of the end of the continuous memory access batch. Until it occurs, the data in the data buffer that has been stored up to that point remains stored.

  Then, when data is read from the master device or another device and the desired read data is still data remaining in the data buffer, the read control information to the memory can also be received by the data buffer unit. Keep it like that.

That is,
1. Regardless of the time since the access to the memory is stopped, the remaining data in the next transfer candidate data buffer is left, and
2. Next, when reading occurs and the desired read data is data remaining in the next transfer candidate data buffer, the read control signal is pulled into the next transfer candidate data buffer unit.

  The read control side can read the desired data by performing a read access operation to the memory without being aware that the desired data remains in the next transfer candidate data buffer unit.

  As a result, only the size of the required data buffer part can be used as a data storage area, and the operation that is not actually accessed by the memory does not need to cause a bit change of the data bus between the memories, and is low. The effect of power consumption can be obtained.

(Embodiment 11)
The eleventh embodiment is an example for specifically explaining the determination method of the minimum Hamming distance.

  The present inventor has found that, in the two data, when both of the two data have a small number of “1”, the Hamming distance is likely to be small. First, the number of “1” s in the previous transfer data and all the next transfer candidate data in the data buffer is counted, and the hamming distance between those having a small “1” and those having a large “1” is determined. Specifically, when there are two pieces of data whose number of “1” is less than a certain number, the Hamming distance between the two pieces of data is determined first. The data having a difference in the number of “1” s in the data beyond the Hamming distance determined here obviously has a larger Hamming distance than the determined Hamming distance, so there is no need to determine the Hamming distance. . This will be described in more detail with reference to FIG.

  FIG. 10 is a diagram illustrating data in the data buffer unit for explaining the method of determining the Hamming distance according to the eleventh embodiment.

  FIG. 10 shows the state of the data buffer, and the data with the shortest Hamming distance is selected from the access data 702 to 704 with respect to the previous access data 701 already accessed.

  Considering that the total address width and data width are 12 bits, data with a small number of “1” is defined. Here, an example in which a certain number is set to “4” will be described.

  In FIG. 10, the number of “1” s in the access data 701 is 3, which corresponds to data with a small number of “1” s. At this time, when data having a small number of “1” s among the data of the access data 702 to 704 is confirmed, the access data 702 corresponds, and if the hamming distance between the access data 701 and the access data 702 is determined, 3 It is.

  The access data 703 has nine “1” s, and the difference in the number of “1” s between the access data 701 and the access data 703 is larger than the Hamming distance obtained as described above. Needless to say, the Hamming distance between the access data 701 and the access data 703 is larger than the Hamming distance between the access data 701 and the access data 702. Actually, the Hamming distance between the access data 701 and the access data 703 is 8.

  In the access data 704, the number of “1” is six, and the difference in the number of “1” between the access data 701 and the access data 704 is equal to the Hamming distance obtained as described above. The Hamming distance between the access data 704 is not necessarily larger than the Hamming distance between the access data 701 and the access data 702. Actually, the Hamming distance is 3 in the Hamming distance between the access data 701 and the access data 704.

  By determining the hamming distance in this manner, an effect of shortening the processing time for determining the hamming distance can be obtained.

  Further, even when the number of “1” s is larger than a certain number, the processing can be performed in the same manner as when the number of data “1” is small, and the number of data “1” is small, which is large. Case processing can be performed simultaneously.

(Embodiment 12)
In the first to eleventh embodiments, writing to the memory has been described as an example. The present invention can also be applied to memory read control.

  The twelfth embodiment is an example for specifically explaining a memory read method together with the following thirteenth embodiment.

  FIG. 11 is a block diagram illustrating a memory read method according to the twelfth embodiment.

  In FIG. 11, a master device 800 such as a CPU includes a read control unit 801 that controls the read operation of the memory 900, and a transfer order restoration unit 802 that rearranges read data returned from the memory 900 in the read order before the rearrangement. With.

  Further, the memory 900 includes a transfer order rearrangement unit 901 that rearranges the order of the memory output data so that the hamming distance in the time series of the read data output from the memory becomes the smallest in the memory read operation.

  Hereinafter, a memory access operation of the memory access method configured as described above will be described.

  In response to a read request 803 to the memory 900 generated by the master device 800, the memory 900 does not output predetermined data immediately, but temporarily stores it in the transfer order rearrangement unit 901.

  The transfer order rearrangement unit 901 rearranges the data write order so that the hamming distance between the transfer data and the next transfer data is minimized by a method similar to the method described in detail in the first to eleventh embodiments. The data is output to the master device 800 via the bus 804.

  Further, the information rearranged by the transfer order rearrangement unit 901 is transmitted to the master device 800 through the read data rearrangement information transmission line 805. In response to this, the master device 800 restores the transfer order to the original order by the transfer order restoring unit 802 in the order in which the read control unit 801 requested to read.

  As described above, according to the twelfth embodiment, the order of the memory output data is rearranged and returned from the memory 900 so that the Hamming distance in the time series of the read data output from the memory 900 is minimized. Since the read data is rearranged in the read order before the rearrangement, the number of bit changes in the read data line can be reduced during read control, and the power consumption of the memory access operation can be reduced.

(Embodiment 13)
In the thirteenth embodiment, in addition to the read control method described in the twelfth embodiment, attention is also paid to a bit change amount of address data for read control.

  FIG. 12 is a block diagram for explaining a memory read method according to the thirteenth embodiment. In the description of the present embodiment, the same components as those in FIG.

  In FIG. 12, the read control unit 1001 of the master device 1000 further includes a read address rearranging unit 1002. The read address rearrangement unit 1002 rearranges the read address order so that the hamming distance in the time series of addresses for read control is minimized.

  Hereinafter, a memory access operation of the memory access method configured as described above will be described.

  A read request to the memory 900 generated by the master device 1000 is not immediately output to the memory 900 but temporarily stored in the read address rearranging unit 1002 in the read control unit 1001.

  The read address rearrangement unit 1002 rearranges the data write order so as to minimize the Hamming distance between the transfer address data and the next transfer address data by the method described in detail in the first to eleventh embodiments, and performs memory read control. The data is output to the memory 900 by the use address 1003.

  Next, data is transferred from the memory 900 to the master device 1000 by the method of the twelfth embodiment described above.

  By doing so, in addition to the effects of the twelfth embodiment, the bit change amount of the address line designated for reading from the master device 1000 to the memory 900 can be reduced, and the power consumption of the memory access operation can be further reduced. .

  Needless to say, the first to thirteenth embodiments described above may be combined. For example, writing to the memory may be performed using the methods of Embodiments 1 to 11, and reading from the memory may be performed using the methods of Embodiments 12 and 13. As an example, a memory access method that outputs an address by the method of the thirteenth embodiment, outputs data from the memory side by the method of the twelfth embodiment, and rearranges the data in the read order before the rearrangement by the memory interface function. Can be adopted. If combined in this way, the write operation and the read operation, and the read operation for rearranging the control addresses can coexist, and the respective effects can be obtained as they are.

  Further, the master device may be a device other than the CPU, and the memory may be either an external device or an internal memory.

(Embodiment 14)
The fourteenth embodiment is a specific configuration example of an apparatus when applied to a write operation to a memory.

  FIG. 13 is a block diagram showing a memory access method according to Embodiment 14 of the present invention. In the description of the present embodiment, the same components as those in FIG.

  In FIG. 13, a master device 1100 such as a CPU stores a data buffer 1101 for storing generated memory access data, a next transfer candidate data buffer unit 1102 for storing next transfer candidate data, a selector 1103, and previously accessed data that has already been accessed. The transfer data storage unit 1104 and the comparator 1105 are configured.

  The next transfer candidate data buffer unit 1102 primarily stores target data to be rearranged.

  The comparator 1105 is a minimum hamming distance detector between the transfer data and the next transfer candidate data, which compares all the data in the next transfer candidate data buffer unit 1102 with the previous transfer data.

  Specifically, the comparator 1105 includes a bit arithmetic unit that determines a transfer order with the smallest bit change through a combination of all the data transfer orders in the next transfer candidate data buffer unit 1102, and a bit change determiner. More specifically, it is stored in a bit counter that counts the number of bit data “1” in the data array, a bit 1 register that stores the number of bit data “1” of the previous transfer data, and the bit 1 register. This is composed of a bit 1 comparator that compares the value with the number of bit data “1” of each data in the next transfer candidate data buffer unit 1102.

  The selector 1103 extracts data from the next transfer candidate data buffer unit 1102 in the order of data determined by the bit change determiner and outputs the data to the memory 200.

  Hereinafter, a memory access method and a memory access operation of the memory access device configured as described above will be described.

  Write data to the memory 200 generated by the master device 1100 is read from the data buffer 1101 and temporarily stored in the next transfer candidate data buffer unit 1102.

Next, the comparator 1105 compares the previously accessed previous access data stored in the transfer data storage unit 1104 with all the data in the next transfer candidate data buffer unit 1102, and uses the comparison result as a selection signal as a selector 1103. Output to. The selector 1103 selects the next transfer data having the smallest Hamming distance from the previous access data from the data in the next transfer candidate data buffer unit 1102 and outputs the selected data to the transfer data storage unit 1104.
(Embodiment 15)
The fifteenth embodiment is a specific configuration example of an apparatus when applied to serial interface memory access.

  In the case of the parallel interface, if the data of the previous transfer data and the next transfer data match, the Hamming distance is the shortest, and even if the same data is transferred twice in succession, the bit change of the bus line between the memories is There is no power consumption on the bus line.

  However, in the case of the serial interface, even if the data of the previous transfer data and the next transfer data match, since the data is transferred bit by bit, the bit line of the bus line between the memories is changed, and the same data is continuously generated twice. Even for the transfer, the power for one transfer is consumed twice as it is.

  Therefore, in the fifteenth embodiment, when applied to memory access of the serial interface, a part or all of the next transfer data generated in the master device is compared with the previous transfer data, and a part or all of the next transfer data is If it matches the previous transfer data, the bit corresponding to the serial interface is not changed.

  Instead, by issuing a match detection signal to the memory side, the memory side can complete transfer normally by quoting part or all of the next transfer data from part or all of the previous transfer data. can do.

  As a specific example described above, a case where the above processing is performed when the lower 4 bits of the write data match will be described with reference to FIG.

  FIG. 14 is a block diagram showing a memory access method according to Embodiment 15 of the present invention. In the description of the present embodiment, the same components as those in FIG.

  In FIG. 14, a master device 1200 such as a CPU includes a data buffer 1201 that stores generated memory access data, a transfer data storage unit 1202 that stores already accessed previous access data, and a comparator 1203. The output of the transfer data storage unit 1202 is passed to the memory 200 via the write data serial line 1204, and the comparison result by the comparator 1203 is passed to the memory 200 via the coincidence detection information transmission line 1205. That is, the master device 1200 is configured to output the matching information to the memory 200 instead of removing the next transfer candidate data buffer unit 1102 and the selector 1103 from the master device 1100 of FIG. As described above, an example of using the write data serial line 1204 will be described in order to reduce power consumption in the case of a serial interface, but it is needless to say that the present invention can be applied to a parallel interface.

  Hereinafter, a memory access operation of the memory access method configured as described above will be described.

  The master device 1200 and the memory 200 are connected by a serial data line 1204. Data to be written is data 1301 and data 1302 in this order.

  First, data 1301 is written from the transfer data storage unit 1202 to the memory 200 via the serial data line 1204.

  Next, the lower 4 bits of the already transferred write data stored in the transfer data storage unit 1202 and the lower 4 bits of the next transfer data stored in the data buffer 1201 are compared by the comparator 1203.

  At this time, since the lower 4 bits of the write data 1301 and the write data 1302 match, the lower 4 bits do not change the bit of the serial data line 1204 when the write data 1302 is transferred.

  Instead, the coincidence information is transmitted from the comparator 1203 to the memory 200 via the coincidence detection information line 1205, so that the lower 4 bits of the transfer data are the same as the lower 4 bits of the previous transfer data. And complete the transfer successfully.

  Thereby, the amount of bit change between memories can be suppressed, and low power can be realized.

  Here, when there are a plurality of reservation data, an ID number is provided for each reservation data, and the ID number is transmitted through the coincidence detection information line 1205, so that a plurality of reservation data can be handled.

(Embodiment 16)
The sixteenth embodiment is an example when applied to a logic LSI memory access device of a mobile phone terminal.

  FIG. 15 is a block diagram showing a memory access device according to the sixteenth embodiment of the present invention, which is a configuration example when applied to a write operation to a memory. This corresponds to a specific example of the apparatus of FIG.

  In FIG. 15, a mobile terminal device 2000 such as a mobile phone includes a CPU 2100 for controlling the entire device, a logic LSI 2200 for controlling an external memory, and a plurality of external memories 2301 to 2303 (external memories <1> to <3>).

  The logic LSI 2200 controls the memory control units 2211 to 2213 (memory control units <1> to <3>) based on the memory control request from the CPU 2100, and the memory control units 2211 to 2211 to control the external memories 2301 to 2303. 2213 (memory control units <1> to <3>). Since the memory control units 2211 to 2213 (memory control units <1> to <3>) have the same configuration, the memory control unit 2211 (memory control unit <1>) will be described as a representative.

  The memory control unit 2211 (memory control unit <1>) includes a data buffer 2221 for storing the generated memory access data, a comparison stage number control unit 2222 for performing comparison stage number control, and a next transfer candidate data buffer unit for storing next transfer candidate data. 2223, a selector 2224, a transfer data storage unit 2225 that stores previously accessed data that has already been accessed, and a comparator 2226.

  The comparison stage number control unit 2222 sets the number of used data buffers in accordance with an instruction from the CPUIF 2210, increases the number of data buffers to be used when importance is attached to the low power consumption effect, and uses data when importance is attached to the processing speed. Control to reduce the number of buffers. The above setting is set by the CPUIF 2210 that has received an instruction from the CPU 2100. Note that the CPU 2100 can separately execute the power saving mode setting process, and can adaptively change the number of data buffers depending on the user designation or the amount of data performed during the setting process.

  The next transfer candidate data buffer unit 2223 primarily stores target data to be rearranged.

  The comparator 2226 is a minimum Hamming distance detector between the transfer data and the next transfer candidate data, which compares all the data in the next transfer candidate data buffer unit 2223 with the previous transfer data.

  Specifically, the comparator 2226 includes a bit arithmetic unit that determines a transfer order with the smallest bit change through a combination of all the data transfer orders in the next transfer candidate data buffer unit 2223, and a bit change determiner. More specifically, it is stored in a bit counter that counts the number of bit data “1” in the data array, a bit 1 register that stores the number of bit data “1” of the previous transfer data, and the bit 1 register. This is composed of a bit 1 comparator that compares the value with the number of bit data “1” of each data in the next transfer candidate data buffer unit 2223.

  The selector 2224 extracts data from the next transfer candidate data storage unit 2223 in the order of data determined by the bit change determiner and outputs the data to the memory 2301 (external memory <1>).

  Hereinafter, a memory access method and a memory access operation of the memory access device configured as described above will be described.

  The comparison stage number control unit 2222 controls the comparison stage numbers of the next transfer candidate data buffer unit 2223 and the comparator 2226 so that the data writing order is rearranged by the set number of data buffers.

  Write data to the memory 2301 (memory <1>) generated by the memory control unit 2211 (memory control unit <1>) is read from the data buffer 2221 and temporarily stored in the next transfer candidate data buffer unit 2223.

  Next, the comparator 2226 compares the previously accessed previous access data stored in the transfer data storage unit 2225 with all the data in the next transfer candidate data buffer unit 2223, and uses the comparison result as a selection signal as a selector 2224. Output to. The selector 2224 selects the next transfer data having the shortest Hamming distance from the previous access data from the data in the next transfer candidate data buffer unit 2223 and outputs the selected data to the transfer data storage unit 2225.

  The above is an example of the memory <1> write operation of the memory control unit 2211 (memory control unit <1>), but the memory <2> of the memory control units 2212 and 2213 (memory control units <2> and <3>). , <3>) is the same.

  As described above, according to the sixteenth embodiment, the memory access method and apparatus can be applied to the mobile terminal device 2000 such as a mobile phone, and the IO current consumption during the memory access operation of the mobile terminal device 2000 is greatly increased. By reducing the power consumption, it is possible to reduce the power consumption of the logic LSI 2200 and the mobile terminal device 2000 in which the logic LSI 2200 is mounted.

  Further, by controlling the number of data buffers that can store memory accesses, the low power consumption effect and the operation speed can be selected appropriately.

(Embodiment 17)
The seventeenth embodiment is an example in which the present invention is applied to a logic LSI memory access device of a mobile phone terminal, as in the case of the mobile phone 16.

  FIG. 16 is a block diagram showing a memory access device according to the seventeenth embodiment of the present invention, which is a configuration example when applied to a read operation from a memory. This corresponds to a specific example of the apparatus of FIG.

  The present embodiment is an example applied to the mobile terminal device 2000 of FIG. 15, and the same components as those of FIG. However, it is needless to say that the memory access method and apparatus according to the present embodiment can be applied to other terminal apparatuses other than FIG.

  In FIG. 16, a mobile terminal device 2000 includes a CPU 2100 that controls the entire device, a logic LSI 2400 that controls an external memory, and a plurality of external memories 2501 to 2503 (external memories <1> to <3>) that are read and controlled by the logic LSI 2400. Is provided.

  The logic LSI 2400 controls the transfer order restoration units 2411 to 2413 (transfer order restoration units <1> to <3>) based on the memory control request from the CPU 2100, and read data returned from the external memories 2501 to 2503. Are configured to include transfer order restoration units 2411 to 2413 (transfer order restoration units <1> to <3>) that perform control to rearrange them in the reading order before rearrangement. Since the transfer order restoration units 2411 to 2413 (transfer order restoration units <1> to <3>) adopt the same configuration, the transfer order restoration unit 2411 (transfer order restoration unit <1>) will be described as a representative.

  The transfer order restoration unit 2411 (transfer order restoration unit <1>) includes a transfer data buffer unit 2421 for storing transfer data, and a comparison stage number control unit 2422 for performing comparison stage number control.

  On the other hand, the memories 2501 to 2503 (external memories <1> to <3>) read data that rearranges the order of the memory output data so that the Hamming distance in the time series of the read data to be output becomes the smallest in the read operation. Output units 2511 to 2513 are provided. Since the memories 2501 to 2503 (external memories <1> to <3>) have the same configuration, the memory 2501 (external memory <1>) will be described as a representative.

  The read output unit 2511 of the memory 2501 (external memory <1>) performs comparison stage number control corresponding to the comparison stage number control of the comparison stage number control unit 2422 of the transfer order restoration unit 2411 (transfer order restoration unit <1>). A stage number control unit 2522, a next transfer candidate data buffer unit 2523 for storing read data 2521, a selector 2524, a transfer data storage unit 2525 for storing previously accessed data that has already been accessed, and a comparator 2526 are provided.

  The comparison stage number control unit 2522 sets the number of used data buffers in accordance with an instruction from the logic LSI 2400, increases the number of data buffers to be used when importance is attached to the low power consumption effect, and is used when importance is attached to the processing speed. Control to reduce the number of data buffers. The above setting is set by the CPUIF 2410 that has received an instruction from the CPU 2100.

  The next transfer candidate data buffer unit 2523 primarily stores target data to be rearranged.

  The comparator 2526 is a minimum hamming distance detector between the transfer data and the next transfer candidate data, which compares all the data in the next transfer candidate data buffer unit 2523 with the previous transfer data.

  Specifically, the comparator 2526 includes a bit calculator that determines the transfer order with the smallest bit change and a bit change determiner through all combinations of the data transfer orders in the next transfer candidate data buffer unit 2523. More specifically, it is stored in a bit counter that counts the number of bit data “1” in the data array, a bit 1 register that stores the number of bit data “1” of the previous transfer data, and the bit 1 register. It is composed of a bit 1 comparator that compares the value and the number of bit data “1” of each data in the next transfer candidate data buffer unit 2523.

  The selector 2524 extracts data from the next transfer candidate data storage unit 2523 in the order of data determined by the bit change determination unit and outputs the data to the transfer data storage unit 2525.

  Hereinafter, a memory access method and a memory access operation of the memory access device configured as described above will be described.

  Both the comparison stage number control unit 2422 of the transfer order restoration unit 2411 (transfer order restoration unit <1>) of the logic LSI 2400 and the comparison stage number control unit 2522 of the read output unit 2511 of the memory 2501 (external memory <1>) are set. The number of comparison stages of the transfer data buffer unit 2421 or the next transfer candidate data buffer unit 2523 and the comparator 2526 is controlled so that the data writing order is rearranged by the number of data buffers.

  First, on the memory 2501 (external memory <1>) side, the read output unit 2511 reads the data 2521 and temporarily stores it in the next transfer candidate data buffer unit 2523.

  Next, the comparator 2526 compares the previously accessed previous access data stored in the transfer data storage unit 2525 with all the data in the next transfer candidate data buffer unit 2523, and uses the comparison result as a selection signal as a selector 2524. Output to. The selector 2524 selects the next transfer data having the shortest Hamming distance from the previous access data from the data in the next transfer candidate data buffer unit 22523 and outputs the selected data to the transfer data storage unit 2525. The rearranged data stored in the transfer data storage unit 2525 is sent to the transfer order restoration unit 2411 (transfer order restoration unit <1>) of the logic LSI 2400.

  On the logic LSI 2400 side, the transfer data buffer unit 2421 of the transfer order restoring unit 2411 (transfer order restoring unit <1>) uses the comparison result of the comparator 2526 of the read output unit 2511 of the memory 2501 (external memory <1>). In addition, the data from the transfer data storage unit 2525 is rearranged in the reading order before the rearrangement.

  The above is an example of the read operation of the transfer order restoring unit 2411 (transfer order restoring unit <1>) of the logic LSI 2400 that reads data from the memory 2501 (external memory <1>). The transfer order restoring units 2412 and 2413 (transfer) The same applies to the data read operation of the sequential restoration units <2>, <3>) and the memories 2502, 2503 (external memories <2>, <3>).

  Thus, according to the seventeenth embodiment, the memory access method and apparatus can be applied to the mobile terminal device 2000 such as a mobile phone, and the number of bit changes in the read data line can be reduced during read control. The power consumption of the memory access operation can be reduced.

  The above description is an illustration of a preferred embodiment of the present invention, and the scope of the present invention is not limited to this.

  In the above embodiments, the names “memory access method” and “memory access device” are used. However, this is for convenience of explanation, and it goes without saying that a processor, a semiconductor memory device, or the like may be used.

  Needless to say, the illustrated address, access data, and bit change are examples of the bit width, the number of data transfers, and the like, and may be other examples.

  Further, the type, number, connection method, and the like of each circuit unit constituting the memory access method and the memory access device are not limited to the above-described embodiments.

  The memory access method and the memory access device according to the present invention are useful as a memory access device mounted on an electronic circuit system having a semiconductor memory device, for example, a communication terminal device such as a mobile phone. The present invention can be preferably used for external memory access, internal memory access, CPU access, etc., but is not limited thereto.

1 is a block diagram showing a memory access method according to a first embodiment of the present invention. The figure which shows the time change of the write data in the data bus of the memory access method which concerns on the said Embodiment 1. FIG. The figure explaining the low power consumption effect of the memory access method according to the first embodiment The figure which shows the time change of the data bus which match | combined the data line and the address line before rearrangement of the memory access method which concerns on Embodiment 2 of this invention. The figure which shows the time change of the data bus which match | combined the data line and address line of the memory access method based on the said Embodiment 2. FIG. The figure which shows the data buffer part of the memory access method which concerns on Embodiment 3 of this invention. The figure which shows the time change of the data bus which combined the data line and the address line, without using the data buffer of the memory access method concerning the said Embodiment 3. Block diagram showing a memory access method according to Embodiment 4 of the present invention The figure which shows an example of the reservation data of the memory access method which concerns on the said Embodiment 4. The figure which shows the data of the data buffer part of the memory access method which concerns on Embodiment 11 of this invention. Block diagram for explaining a memory read method of the memory access method according to the twelfth embodiment of the present invention Block diagram for explaining a memory read method of a memory access method according to a thirteenth embodiment of the present invention Block diagram showing a memory access method according to Embodiment 14 of the present invention Block diagram showing a memory access method according to Embodiment 15 of the present invention Block diagram showing a memory access apparatus according to a sixteenth embodiment of the present invention. Block diagram showing a memory access apparatus according to a seventeenth embodiment of the present invention The figure explaining the difference between the internal load capacity and the external load capacity of a conventional LSI Conceptual diagram for explaining write operation in conventional memory access The figure which shows the time change of the write data in the data bus of the conventional memory access method

Explanation of symbols

100, 600, 800, 1000, 1100, 1200 Master device 101, 1101, 1201 Data buffer 102 Memory access order rearrangement unit 103 Write data bus and address data bus 200, 900, 2301, 2302, 2303, 2501, 2502, 2503 Memory 601 Reserved data storage unit 602 Match detection unit 801, 1001 Read control unit 802, 2411, 2412, 2413 Transfer order restoration unit 901 Transfer order rearrangement unit 1002 Read address rearrangement unit 1102, 2223, 2523 Next transfer candidate data buffer unit 1103 , 2224, 2524 selector 1104, 1202, 2225, 2525 transfer data storage unit 1105, 1203, 2226, 2526 comparator 2000 portable terminal device 2100 CPU
2200 Logic LSI
2211, 2122, 2213 Memory control unit 2421 Transfer data buffer unit 2511, 2512, 2513 Read output unit 2222, 2422, 2522 Comparison stage number control unit

Claims (22)

Rearranging the data writing order so that the Hamming distance between the transfer data and the next transfer data is minimized;
And a step of accessing the memory by the rearranged data. Rearranging the address order so that the Hamming distance between the first address and the second address is minimized;
And a step of accessing the memory by the rearranged address.   The method further comprises a step of selecting the number of data candidates whose rearrangement of the writing order is considered so as to minimize the Hamming distance and an overhead of a transfer time required for securing the rearrangement candidate data. The memory access method according to claim 1 or 2. Storing all or part of bit changes of the transfer data and the next transfer data in advance as reserved data;
Determining that the bit change matches the reserved data;
Prohibiting a change from the transfer data to the next transfer data when the bit change matches the reserved data;
4. The memory access method according to claim 1, further comprising a step of transferring data by transmitting the coincidence information to a memory side. Comparing the previous transfer data with all the next transfer candidate data;
5. The memory access method according to claim 1, further comprising: selecting next transfer data having the shortest Hamming distance from the previous transfer data.   6. The memory access method according to claim 1, further comprising a step of determining a transfer order having the smallest bit change through a combination of all transfer candidate data transfer orders. Outputting to the memory the memory access that occurred first when the next transfer candidate data buffer is empty;
The memory access method according to claim 1, further comprising: storing next transfer candidate data in the buffer unit after the next memory access occurs.   8. The memory according to claim 1, further comprising a step of accumulating in the buffer unit from a memory access that occurs first in a state where the next transfer candidate data buffer unit is empty. how to access. Detecting the end of successive memory accesses;
A step of outputting all the remaining data of the next transfer candidate data buffer unit to the memory by repeating the memory access method according to claim 1 when the end of the continuous memory access is detected. 9. The memory access method according to claim 1, further comprising: Detecting occurrence of memory access;
10. The memory access method according to claim 1, further comprising a step of storing data in a next transfer candidate data buffer unit until the memory access occurs.   First, determine the minimum hamming distance by comparing the hamming distance between the data with a small number of bit data “1” or the data with a large number of bit data “1”. 11. The memory access method according to claim 1, further comprising the step of: Rearranging the order of the memory output data so that the Hamming distance on the time series of read data output from the memory is minimized;
Rearranging the read data returned from the memory to the read order before the rearrangement. Rearranging the order of the memory output data so that the Hamming distance on the time series of read data output from the memory is minimized;
The information rearranged on the memory side is transferred to the memory interface function, and the read data returned from the memory is rearranged in the reading order before the rearrangement using the information rearranged on the memory side. And a returning step. A memory access method comprising: Rearranging the read address order so that the Hamming distance on the time series of read control addresses is minimized;
Rearranging the read data returned from the memory to the read order prior to the rearrangement. A memory access device for controlling writing to a memory,
A memory access device comprising rearrangement means for rearranging a data writing order so that a Hamming distance between transfer data and next transfer data is minimized. The rearranging means includes a next transfer candidate data storage unit that primarily stores target data to be rearranged;
Selecting means for comparing all data in the next transfer candidate data storage unit with the previous transfer data, and selecting the next transfer data having the smallest hamming distance from the previous transfer data from the next transfer candidate data storage unit; The memory access device according to claim 15.   It is characterized by comprising mode selection means for selecting the number of data candidates whose rearrangement of the writing order is considered so as to minimize the Hamming distance and the overhead of the transfer time required for securing the rearrangement candidate data. The memory access device according to claim 16. Rearrangement means for rearranging the reading order of the read data of the memory side output so that the Hamming distance on the time series of the read data of the memory side output is minimized;
A memory access device comprising: read data order restoring means for rearranging read data returned from the memory to a read order before rearrangement in the rearrangement means. Rearrangement means for rearranging the order of the memory output data so that the Hamming distance on the time series of read data output from the memory is minimized;
The memory side is provided with rearrangement information transmitting means for transmitting the information rearranged on the memory side to the memory read data receiving side,
A memory access device comprising: read data order restoring means for rearranging read data returned from the memory to the read order before the rearrangement using the information rearranged on the memory side. Reordering means for reordering the read address order so that the Hamming distance in the time series of addresses for read control is minimized;
A memory access device comprising: read data order restoring means for rearranging read data returned from the memory to a read order before rearrangement in the rearrangement means. Determining means for determining whether all or part of the data array of the transfer data and the next transfer data match;
A memory access device comprising: a transmission means for transferring data by transmitting the coincidence information to the memory side. Reservation data storage means for storing all or part of bit changes of transfer data and next transfer data as reservation data in advance,
Determining means for determining that the bit change matches the reserved data;
A memory access device comprising: a transmission means for transferring data by transmitting the coincidence information to the memory side.

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