JPS61138352A - Data transfer control system - Google Patents

Abstract

PURPOSE:To execute the simultaneous operation of plural channels efficiently even by a memory having low transfer capacity by dynamically changing the contents of priority registers formed in plural channels. CONSTITUTION:Priority information (PI) is always inputted from the priority registers (Prio R) to decoders 100-102 and decoded. If data transfer requests RQ0-RQ2 are outputted from respective channels under said status, the decoded outputs are excited. When a decoded output (a) is generated from any one of the channels CH0-CH2, the output ENa of a NOR circuit 103 is turned to '0' and the decoded outputs lower than the priority of the decoded output (a) are suppressed. The decoded outputs (b), (c) are also functioned similarly. The priority is automatically determined by setting up any value of the PI having the priority of a>b>c.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention provides data processing in an integrated channel device comprising a plurality of channels and a control circuit for controlling data transfer between the channels and a main memory. Regarding transfer control method.

As the amount of data processed by modern data processing devices has increased, high-speed input/output interface methods have been introduced for the input/output interface between the channels of the data processing devices and the input/output devices. , the data transfer capability of the channel has been dramatically improved.

On the other hand, with the remarkable progress of semiconductor technology, the degree of integration of memory elements has improved, and the capacity of memory devices has been increased.However, as the above-mentioned high-speed input/output interface conditions cannot be met, there is a problem in efficiency. There is a growing need for a data transfer system between a channel and main memory with good performance.

[Conventional technology]

FIG. 3 is a block diagram showing an outline of a conventional integrated channel device, in which 1 is a main memory (hereinafter referred to as MEM), 2 is a memory control unit (hereinafter referred to as MCU), 3
is the central processing unit (hereinafter referred to as CPII) + 4 is M[
! 5 is a CPU bus, 6 is a channel control device (hereinafter referred to as CHC), 7 is a CH bus, 9 is a channel,
90 to 92 are each CHO-CI2.

Now, when an input/output command is issued in CPU 3,
The input/output command is sent to the CHC 6 through the CPU bus 5, and when the CPU interface control unit 61 in the CHC 6 recognizes the input/output command, the MEME
Start the interface control unit 62 and connect the ME bus 4M.
The command address word (CAN) for the relevant input/output instruction is read from the MEM 1 through the CII 2, and the
The CI bus control section 63 reads the channel command word (C(J)) from W, and according to the contents of the channel command word (CCII), the CI bus control section 63 reads the channel command word (C(J)) from the channel command word (CCII) through the CI bus 7, and sends the CIo 90 to C
By selecting a specific channel in H292 and executing input/output processing with a specific input/output device through the input/output interface, data transfer for the above input/output command is executed.

[Problem that the invention seeks to solve]

At this time, in the conventional method, each CI090 to CI (2
The data transfer request signals RQO to RQ2, which are determined by the position where the 92 is mounted, are subjected to known priority selection in the priority selection circuit 8.

In this example, as is clear from the contents of the priority selection circuit 8, the priority order is RQO > RQI > R port 2, so the data transfer ability on the MEM I side is compared to the transfer ability on the channel side. If the number of channels is low, there is a problem in that the transfer capacity of the plurality of channels cannot be fully utilized.

In other words, if RQO from Cll090 is issued continuously due to the slow data transfer ability on the MEM l side, the priority selection circuit 8 always selects RQO, and other In the old version of C, there was a problem in that the input/output device (Ilo) connected to the channel was likely to overrun because the data transfer request RQI and R02 from CI2 could not be selected.

In view of the above-mentioned conventional drawbacks, the present invention changes the priority of data transfer depending on the data transfer speed of the input/output device (Ilo) connected to each channel and the content of input/output processing in the channel. The object of the present invention is to provide a method that allows simultaneous operations to be performed efficiently even with a memory having a low transfer capacity.

[Means for solving problems]

The purpose of this is to provide a priority register for setting the priority of a plurality of channels constituting the integrated channel device, and to determine the priority of data transfer according to the contents of the priority register outside the channel. A priority determination circuit (C) is provided to determine the contents of the priority register according to the type of input/output bag device (Ilo) connected to the channel and the content of input/output processing.
external device.

Alternatively, this can be achieved by the data transfer control method of the present invention, which controls to determine the priority of data transfer in the integrated channel device by setting it in the channel.

[Effect]

That is, according to the present invention, C41O-CH2 is configured to control each channel CI (O to C) depending on the type of input/output device (Ilo) connected to each channel and the content of input/output processing in each channel. By dynamically changing the contents of the priority register provided in +2, each channel C)
Since the priority between CI10 and CI2 can be changed, data transfer of a plurality of channels can be carried out efficiently.

〔Example〕 Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing a portion of the integrated channel device related to the present invention, and FIG. 2 is a logic circuit showing the details of the priority determining circuit (C) 10, which is the main focus of the present invention. The same symbols indicate the same objects throughout the figures, and the priority determination circuit (C) 10 and the priority register A provided in each channel are used to implement the present invention. It is a functional block.

In Figure 1, each CHO9O-CH292 is MEM
1, and a priority register 8 indicating the priority of each channel.

When the CHC 6 receives MEM access requests from two or more channels, the priority determination circuit (C) 10
Compare the priorities, decide which channel's MUM access should be prioritized, and set the MEM access of that channel to
Processing is performed by register D in the CI+bus control unit 63.

The priority information set in priority register A is
At the time of initialization, such as when power is turned on, a value determined by the transfer speed of the input/output device (■10) connected to each channel, overrun conditions, etc. is assigned to the subchannel (not shown) provided in the channel, etc. Service processor (
SVP) (not shown) is stored, and each channel (C) 10-CH2) 9 refers to it when performing input/output processing and writes it to the priority register A, thereby performing priority control. be exposed.

Also, depending on the state of input/output processing in each channel (CHO-Cl2) 9, the priority can be dynamically changed by setting the contents of the priority register ^ to, for example, the upper bits of "0"#'1'. can do.

The state of the input/output processing for dynamically changing the priority of each channel (CFIO to cH2) 9 will be described in more detail. That is, each channel (CIIO to C)+2) 9 has a different required transfer capacity depending on the connected input/output device (Ilo), or has different command overrun and data overrun conditions.

Also, while a write command (memory → ■10) is being executed,
When there is a data request from the input/output device (Ilo), data from MEM 1 needs to be prepared in the channel.

Conversely, while a read command (I10→memory) is being executed, if the data transferred from the input/output device (Ilo) is delayed in being transferred to MEM'□1, the data and remains and causes an overrun.

In addition, even if it looks like one command is being executed from the input/output device (■10) side, as with chain data, multiple channel command words (CCW) are chained on each channel side. and input/output devices (Il).
Since data is transferred next from the o) side, Ml!
It is necessary to urgently transfer the data to M1.

In the above case, it is necessary to expedite the input/output processing, but if, for example, the write data is sufficiently prefetched on the channel side, access to MEM 1 may be delayed.

In such a case, each channel (CH0-CH2) 9 dynamically adjusts the priority of memory access (read/write) according to the type of input/output device (Ilo) and the content of input/output processing. When there is no need to rush the memory access, it gives priority to other channels, and conversely, when it is necessary to rush the memory access, it gives priority to memory access over other channels. The feature of the present invention is that the data transfer of the channels is controlled to be executed efficiently. □ Fig. 2 shows a specific example of the priority determination circuit (C) 10 shown in Fig. 1, and each channel (CHO-CH2)
From priority register 8 provided in 9,
Priority information (for example, 2-bit information@) PI is always input and is decoded by decoders (DEC) 100 to 102.

In this state, each channel (CHO to CI+2) 9
When data transfer request RQO-RQ2 from
The decode output is activated.

At this time, for example, any channel (CHO to CH2)
9, when the decode output a is output, the output BNa of the NOR circuit 103 becomes "O", and functions to suppress decode outputs having a lower priority than the decode output a.

Similarly, when a decode output is output, the output ENb of the NOR circuit 104 becomes 0', and functions to suppress decode outputs having a lower priority than the decode output.

Hereinafter, the decode outputs C~ are also configured to function in the same manner.

Therefore, in each channel (CHO to CH2) 9,
The priority of each channel is automatically determined depending on which value of the priority information PI having the priority such as a>b>C- is set in the priority register 8.

That is, unlike the conventional system, the priority of the own channel can be freely determined regardless of the R old signal determined by the mounting position.

If two channels, for example Cll0. In CHI, when the decode output a is output, the decoder (DEC
) At 100.101, the decode output a is activated, and according to the same logic as above, the output ENa of the NOR circuit 103 becomes O1, but the normal priority circuit 9106 operates so that, for example, CIO is preferentially selected. do.

By providing the priority determination circuit (C) 10 of the present invention with such a logical configuration, for example, each channel (CI
In IO-cH2)9, the contents of the priority register in the own channel are set to, for example, the upper bits as "1" or 0, depending on the state of the input/output processing being executed in the own channel. This shows that the priority order of the channels can be dynamically changed.

〔Effect of the invention〕

As described above in detail, the data transfer control method of the present invention allows CIs (0-CHI2) to be used depending on the type of input/output device (Ilo) connected to each channel.

Each channel C
By dynamically changing the contents of the priority register A provided in HO to CI+2, each channel CI (O-C
Since the priority level between H2 can be changed, data transfer of multiple channels can be carried out efficiently.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a logic circuit diagram showing details of the priority circuit of the present invention. FIG. 3 is a block diagram of a general integrated channel device. It is. In the drawing, 1 is the main memory device (liver rib), 2 is the memory control unit (MCU)
. 3 is the central processing unit (CPU), 4 is MEM. 5ba CPU bus. 6 Badge channel control device (CIJ (:). 7 is CH bus bus, 8 is priority selection circuit (C)
. 10 is a priority determination circuit (C). 9 is a channel (CIIO to CI+2). A is a priority register. B is a register for MEM interface. D is a register for MUM access. PI is priority information. Select C old is a channel selection signal. are shown respectively. N

Claims (1)

[Claims] In an integrated channel device comprising a plurality of channels and a control circuit that controls data transfer between the channels and a main storage device, a priority register for setting the priority of the channel within the plurality of channels; In addition to the channel, there is a priority determination circuit (C) that determines the priority of data transfer according to the contents of the priority register.
and input/output devices (I/O) connected to the channel.
/O) and the contents of input/output processing, the contents of the priority register are set in the external device or the channel concerned, thereby controlling the priority of data transfer in the integrated channel device. A data transfer control method featuring: