JPH01142955A - Information processor - Google Patents

Abstract

PURPOSE:To control memory allocation by providing a comparator which compares the contents of an address register with an address bus and plural floating arrangement storage parts which includes one group of memory blocks which can be accessed when the contents of the address register coincide with the address bus. CONSTITUTION:A floating arrangement storage part 7 is stored with a value of 10 in its address register 71 and addresses from 100000 to 11FFFF can be accessed. In this state, a value of 8012 is stored in an address register 71 of the floating arrangement storage part 7 and a memory area which can be accessed from an address of 100000 becomes accessible from 80120000 to 8013FFFF and the memory capacity in the system space can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention uses a plurality of memory blocks and dynamically rearranges and uses the addresses of each memory block, thereby improving the system space of the storage device and applications. The present invention relates to an information processing device that can control the allocation of cage program space.

2. Prior Art As a conventional information processing device, for example, Japanese Patent Application Laid-Open No. 59-14
This is shown in Japanese Patent No. 4965. FIG. 4 is a block diagram showing the configuration of this conventional information processing device.
is memory segment 0°1.2. 4 is a segment register that holds the segment number of the memory to be accessed, 6 is a boundary register that holds the boundary address between the common area and non-common area of each memory segment, and 6 is a comparison that compares the value of the boundary register 6 and the address bus. It is a vessel. 7
is a gate that sends the contents of the segment register 4 to the segment bus when the signal 61 from the comparator 6 is on, and sends Ot when the signal 61 is off.

In the conventional information processing device configured as described above,
Compare the contents of the address bus and the contents of boundary register 6,
If it is smaller, the contents of the segment register 4 are sent to the segment bus by turning on the output of the comparator 6.

As a result, the memory segment selected by segment register 4 becomes accessible. The content of the address bus is compared with the content of the boundary register 5, and if the content is larger, the output of the comparator 6 is turned off to set the segment bus to zero.
Memory segment 0 is always accessible.

Problems to be Solved by the Invention However, in the above configuration, by changing the contents of the boundary register 5, areas that can be accessed in common according to the value of the address bus and areas that are accessed for each memory segment can be separated. Although division can be made variable, it has the disadvantage that memory mapped to a common area other than segment 0 cannot be accessed and is wasted.

In view of this, the present invention uses a plurality of memory blocks and dynamically rearranges and uses the address arrangement of each memory block to control memory allocation between the system space and application program space of the storage device. The purpose is to provide an information processing device that can.

Means for Solving the Problems The present invention includes an address register that holds a memory address, a comparator that compares the contents of the address register with an address bus, and access becomes possible when the contents of the address register match the address bus. The information processing device includes a plurality of floating storage units each including a memory block.

According to the above-described configuration, the present invention sets the address of the system space and application program space in the address register of each floating storage section, so that the capacity of the floating storage section is allocated to the system space or the application space. It will be decided whether it will be placed in

Embodiment FIG. 1 is a block diagram showing the configuration of an information processing apparatus in an embodiment of the present invention. In FIG. 1, 7 is a floating memory section, 71 is an address register that holds the start address of the floating memory section, and 72 is a comparison between the contents of the address bus and the address register, and when they match, a signal 721 is turned on. The comparator 73 is a memory block of, for example, 128K that can be accessed when the signal 721 is turned on.
It has a capacity of B. Reference numeral 8 is a fixed location storage section, and 82 is a memory block having a capacity of, for example, 1 MB. A decoder 81 decodes the address bus signal and permanently determines the address arrangement of the memory block 82. 9 is another floating storage unit having the same configuration as 7. 1o is another fixed storage unit having the same configuration as 8. FIG. 2 is a diagram showing the distribution of storage space in an embodiment of the present invention. The area from address 0 to address 77FFFFFFFF is the application program space, and
It is assumed that the area up to address yyy is the system space, and the system space cannot be accessed from a program running in the application space. The third factor is a diagram showing changes in storage space allocation in one embodiment of the present invention.

The operation of the information processing apparatus of this embodiment configured as described above will be described below. Fixed location storage unit 8 is 800
Assume that it is possible to access from address 00000 to address 80OFFFFFF. Fixed location storage unit 1o is from address 0 to FF
It is assumed that up to address FFF can be accessed. In the floating memory unit γ, the value 8010 is stored so that the memory block 73 can be accessed, and the value 801ooO
It is assumed that the area from address o to address 8017FFFF can be accessed. Similarly, in the floating memory section 9, the address register stores the value 10, and 1oooOo
It is assumed that the area from address to address 117FFF can be accessed. This state is shown in FIG. 3 (&). In such information processing devices, it may be necessary to change memory allocation at startup or during operation. For example, when the memory currently allocated in the system space is insufficient, such as when expanding the functions of the operating system in the system area or when wanting to load an optional device driver. In such a case, by storing the value 8012 in the address register of the floating memory section 9, the memory area that could previously be accessed from address 110000 will be reduced to 8.
The memory capacity allocated to the system space is increased by changing the address so that it can be accessed from address 0120000 to address 8013FFFF. This state is shown in FIG. 3(b).

On the other hand, there are cases where a plurality of application programs are placed in the application program space and run simultaneously in multiple processes. In such a case, by storing a value of 12 in the address register 71 of the floating arrangement storage section 7 and a value of 10 in the address register of the floating arrangement storage section e, the memory capacity arranged in the application program space can be increased. increases. This state is shown in Figure 3 (c
).

As described above, according to this embodiment, there is an address register that holds a memory address, a comparator that compares the contents of the address register with the memory address bus, and an access is possible when the contents of the address register match the address bus. By providing multiple floating storage units each consisting of a set of memory blocks, the allocation of memory between the system space, application cage, and program space can be freely changed, eliminating the need to waste part of the storage unit. It disappears.

As described in detail, according to the present invention, it is possible to freely allocate memory between the system space and the general program space depending on the size of the system program such as the operating system or the general program. It can be changed and set, and its practical effects are great.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an information processing device according to an embodiment of the present invention, FIG. 2 is a storage space distribution diagram according to an embodiment of the present invention, and FIG. 3 is a storage space diagram according to an embodiment of the present invention. FIG. 4, which is an explanatory diagram showing changes in space allocation, is a block diagram showing the configuration of a conventional information processing device. 7...Floating arrangement storage unit, 71...Address register, 72...Comparator, 73...
-・Memory block. Name of agent Toshio Nakao and 1 other person
Figure No. 253 Address

Claims (1)

[Claims] A set includes an address register that holds a memory address, a comparator that compares the contents of the address register with a memory address bus, and a memory block that becomes accessible when the contents of the address register match the address bus. It is equipped with a plurality of floating memory units and at least one fixed memory unit that is addressed in a fixed manner, and it is possible to rearrange the floating memory units in the system/application program space depending on the system configuration. information processing equipment.