JPH01183750A - Cache memory residence system - Google Patents

Abstract

PURPOSE:To realize the mixed use of a cache memory and a high-speed memory in an optional area with a simple constitution by providing a comparator as well as a register which stores the permission information on the use of the cache memory. CONSTITUTION:A register 8 stores the information on the permission for the use of a cache memory 7 as it is, i.e., a way number. In case a way 7-2, for example, of the memory 7 is stored in the register 8 in an effective form. Thus a comparator 3 compares the address of the corresponding way 2-2 of an address memory 2 with a part of the address pointed by an MPU1. Thus an access is given to an area 7-2 of the memory 7. While an area 7-1 of the memory 7 is defined as an access enable area of a high-speed memory not as a cache memory. This access enable are receives accesses from a part of each of those addresses pointed by the register 8, a decoder 9 and the MPU1 respectively. In such a way, an access is possible to a mixed area of the memory 7 and the high-speed memory through a simple constitution.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a cache memory resident method in a cache memory that can be accessed at high speed. In a system that is composed of a processor, an address memory that stores address information, and a cache memory, and uses the cache memory as a high-speed memory that can be accessed at high speed, part or all of the cache memory a register that stores information that permits the use of the address memory as a cache memory, and a comparator that compares an address output from the address memory with a part of the address specified by the processor, If they match, the cache memory is accessed when the comparison is made by the comparator, and if the disallowance conditions of the register are matched, the memory is accessed as a high-speed memory and is made resident as a result.

[Industrial application field]

The present invention relates to a cache memory resident system in a cache memory that can be accessed at high speed.

In the field of information processing, many cache memories are used around processors. This cache memory is used not as a cache memory but as a high-speed memory capable of high-speed access.

Therefore, there is a need for a cache memory resident system that has a simple configuration and allows mixed use of cache memory and high-speed memory.

[Conventional technology]

Conventionally, when using cache memory as high-speed memory, it was necessary to disable the cache memory and use it as high-speed memory after powering on the system and before operating the system, such as diagnosing the system. It is being said. In other words, use it as a cache memory,
Cache memory can be used as high-speed memory, or can be used in two different operating modes.

Furthermore, the fixed area is divided into cache memory and high-speed memory.

The above method is inconvenient because it is impossible to arbitrarily mix and use areas with cache memory/high-speed memory.

To deal with this situation, the control unit that controls the cache memory has the resident bit of each entry added to the address, and the resident bit is turned on as the cache memory.
A method has been adopted in which the memory is registered as a high-speed memory. However, this method requires a complicated control circuit for controlling the resident bits in the control section.

[Problem that the invention seeks to solve]

As mentioned above, in the conventional method, the area is fixed and the control unit becomes complicated when handling two modes, that is, cache memory and high-speed memory, or when using cache memory and high-speed memory together. There is a problem.

SUMMARY OF THE INVENTION In view of the above-mentioned conventional situation, it is an object of the present invention to provide a cache memory resident system that has a simple configuration and can be used as both a cache memory and a high-speed memory in any area.

[Means for solving problems]

As shown in the principle diagram of FIG. 1, this invention consists of a processor 1, an address memory 2 that stores address information, and a cache memory 7 that can be accessed at high speed, and the cache memory 7 is permitted to be used as a cache memory. a register 8 that stores information, a comparator 3 that compares part a of the address specified by the processor with permission information of the register 8 and an address of the address memory specified by part of the address specified by the processor; A decoder 9 and a gate 6 are provided to operate as a high-speed memory.

[For production]

For example, if the way 7-2 of the cache memory is stored as valid in the register 8, the address of 2-2 of the corresponding way 8 of the address memory 2 and the CPU
The comparator 3 compares the part of the address indicated by 1, and if it matches, the cache memory 7-2
access the area.

Further, areas 7 to 1 are areas that can be accessed not as a cache memory but as a high speed memory, and are accessed by the register 8, the decoder 9, and part a of the address specified by the processor.

With a simple configuration provided with registers and comparators, it is possible to access a mixed area of cache memory and high-speed memory.

〔Example〕

FIG. 2 is a block diagram showing an embodiment of the present invention. 1 is a processor (MPU), and 2 is an address memory, for example, 4-way memories 2-1 to 2-4. 3 and 5
are comparators 3-1 to 3-4 and 5-1 to 5-4 corresponding to 4-way. A register 4 specifies an address for each way when used as a high-speed memory, and is composed of registers 4-1 to 4-4. 6 is a gate circuit, 7 is a cache memory that can be used as a high-speed memory, and is composed of 7-1 to 7-4 corresponding to 4 ways. Reference numeral 8 denotes a register that stores information that allows the cache memory 7 to be used as a cache memory, that is, a way number.

For the sake of clarity, FIG. 2 shows the wiring of only the #1 way, and the other ways #2 to #4 are similarly connected between the same subscripts.

For example, if ways 2-1 to 2-3 are registered in register 8, register 8 registers 2-1 to 2-3 in address memory 2 and ways 2-1 to 2-3 in comparator 3 when access is not to a high-speed memory area. Allow operation of 3-1 to 3-3・MPU 1
The address signal a from the way 2-1 to 2-3 is compared with the addresses of the ways 2-1 to 2-3 by the comparator 3. The comparator 3 uses the cache memory 7 as a cache memory to access the corresponding area via the gate circuit 6 together with the matched way number.

In the case of access to the high-speed memory area, the address memory 2 and comparator 3 are disabled because the permission signal is not input, and the areas 2-1 to 2-3 that use the high-speed memory area as cache memory access is prohibited.

At this time, the address signal a from the MpU 1 is compared by the comparator 5 5-4 with the contents, ie, the address, of the register 4 4-4 storing the address of the high-speed memory for each way. If a match is made, the corresponding area is accessed via the gate circuit 6 using the corresponding cache memory 7-4 as a high-speed memory.

FIG. 3 is a block diagram showing another embodiment of the present invention,
The difference from the embodiment shown in FIG. 2 is the register 4 for specifying the start address when used as high-speed memory.
The number of ways in the area used as a cache memory is registered in the register 8.

For example, register the number of ways 3 in register 8, register 4
rloooJ is registered in 0. The comparator 5 compares and detects that there is an address from the address registered in the register 40 to the address for the remaining 1 way to be used as high-speed memory, and if 2 matches, the fourth way 7-4 is used as high-speed memory. accessed as an area.

Although the above explanation has been made using a 4-way address memory, it goes without saying that this number may be arbitrary without any problem.

〔Effect of the invention〕

As is clear from the above explanation, according to the present invention, it is possible to mix cache memory and high-speed memory with a simple configuration of registers and comparators without controlling the resident bits of cache memory. It is extremely effective in effectively utilizing cache memory.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a block diagram showing an embodiment of the invention, and FIG. 3 is a block diagram showing another embodiment of the invention. In the figure, 1 is the MPU, 2 is the address register,
3 and 5 are comparators, 7 is a cache memory, and 8 is a register. Tosai 41 Ukeguchi 1st Shinobi Figure 2

Claims (1)

[Scope of Claims] A system comprising a processor (1), an address memory (2) for storing address information, and a cache memory (7), and using the cache memory (7) as a high-speed memory capable of high-speed access. , a register (8) for storing information that allows part or all of the cache memory (7) to be used as a cache memory, and an address to be output from the address memo (2) and a designation of the processor (1). a comparator (3) that compares a part of the address with a part of the address to be accessed; A cache memory resident method characterized in that when a disallowing condition of a register (8) is met, the cache memory can be accessed as a high-speed memory and can be made resident as a result.