JPH0535598A - Paging monitor mechanism of integrated circuit microprocessor - Google Patents

Abstract

PURPOSE:To debug associative storing operation efficiently by the integrated circuit microprocessor which has a paging system memory controller using an associative storage device. CONSTITUTION:The integrated circuit microprocessor 1 has the paging system memory controller 5 which has the associative memory and a memory control debugging device 8 which debugs the operation of the memory controller 5. The memory control debugging device 8 has a register device 81 for specifying a debugging mode, a controller 82 which inhibits normal operation when the debugging mode is specified, and a controller 83 which initiates a debugging interruption on receiving a discrepancy signal from the side of the memory controller 5 in the debugging mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit microprocessor incorporating a memory management unit for implementing virtual memory by paging. More particularly, the present invention relates to a paging monitor mechanism that assists in debugging system software and hardware that controls virtual memory in this type of integrated circuit microprocessor.

[0002]

2. Description of the Related Art As an address generation method for accessing a main storage device, a paging method has been used for a long time as a method for realizing a virtual storage system, and this method is also the most general virtual storage management method. .. In this paging method, the address space is managed for each unit of a uniform size called a page. Although there are various page sizes, 1 Kbyte, 2 Kbyte, 4 Kbyte, 8 Kbyte, 16 Kbyte, etc. are common sizes.

In general address generation by the paging method, a logical address generated by a program is divided into two, an upper address of the division is set as a page number, and a lower address is a line number indicating a position within a page. Is used as. On the page number side, a conversion table for converting a logical address into a physical address is prepared by virtual memory system software, and the page number that is the logical address generated by the program is It is converted into a physical address by the conversion table. On the other hand, the line number, which is the lower address, is used as it is as physical address information indicating the position within each page. Access to the main storage device is executed based on this line number and the page number converted into a physical address. Usually, in the conversion table, a flag indicating whether or not the corresponding page exists in the main storage device is prepared along with the address correspondence. If it is confirmed based on this flag that the corresponding page exists, address conversion is performed, and if not, "page fault" processing or "page miss" processing is performed. During the "page miss" process, the low speed and large capacity auxiliary or absent page placed on the external storage device is read into the main storage device and the conversion table is updated. When the main memory capacity for reading the page is insufficient, an appropriate page in the main memory is written to the external memory. The virtual storage system is configured in this way, and it is possible to execute a program that requires a storage capacity larger than the capacity of the main storage device.

Here, page reading (page-in)
The writing of pages and the writing of pages (page out) hold the key to the efficiency of the virtual memory system, and various efficient algorithms for deciding which page to page out have been devised. The conversion table is called a "page table" and is prepared in the main storage device. However, the conversion operation that needs to search the main storage device takes a very long time in comparison with the instruction processing speed. For this reason, it is usually a "page table".
Information in use is placed in a high-speed temporary storage device to speed up conversion. An associative memory (TLB) is often used as a temporary storage device for this purpose. Further, various algorithms and the like have been devised for efficiently maintaining and managing a temporary storage device that holds information in use with a small capacity.

The paging system is excellent in realizing virtual memory, and various complicated algorithms for improving efficiency have been devised. However, in the past, computer systems realizing virtual memory were limited to large-scale and expensive systems, and only limited specialists were engaged in the system software and hardware for realizing virtual memory. ing. Under such an environment, it is possible to use large-scale support software / hardware for developing a virtual memory system.
Alternatively, support software / hardware itself can be newly developed separately from the target computer system. Therefore, even if a complicated algorithm is used, a sufficient debugging work can be performed.
In this case, efficient development and debugging work depends on dedicated support software / hardware according to the specifications of the development target. However, since the dedicated support software / hardware is dedicated, the development cost and the operation cost are very high.

[0006]

With the development of integrated circuit microprocessor systems, computer systems using microprocessors capable of realizing virtual memory have been supplied at low cost. When considering this computer system using a microprocessor as an object, if a dedicated development support device such as the conventional one is to be prepared, the development or introduction of the support device costs much more than the target computer system. It gets bulky. Therefore, it is not practical to use the conventional expensive dedicated development support device as it is for the development of the virtual memory system using the integrated circuit microprocessor.

In view of this point, an object of the present invention is to realize a mechanism capable of inexpensively constructing a development support device for a virtual memory system in a computer system using an integrated circuit microprocessor.

[0008]

In order to solve the above problems, in the present invention, a debugging support function of a virtual memory system is incorporated in an integrated circuit microprocessor itself, and a computer system itself using this integrated circuit microprocessor. Is used as a development support device for a virtual memory system.

That is, the present invention incorporates a paging monitor mechanism into an integrated circuit microprocessor having a paging-type memory management mechanism including an associative memory device and debugs this mechanism to debug page fault handling operations. A debug mode designating unit for designating a mode and an interrupt generating unit for inhibiting a page fault processing operation and generating a debug interrupt when the debug mode is designated are provided.

[0010]

When the debug mode is not designated by the debug mode designating means, when a page fault occurs, page fault processing is performed according to a preset procedure, a page table update operation, and a physical address conversion operation. And so on.

On the other hand, when the debug mode is designated, when a page fault occurs, a debug interrupt is generated by the interrupt generation means after the logical address is held in the register. After this, debug
Software-like processing in a routine is performed, and page fault processing and physical address conversion operation similar to normal operation are performed.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a schematic configuration of an integrated circuit microprocessor to which the present invention is applied. The microprocessor of this example is a 32-bit general-purpose microprocessor manufactured using a CMOS process. As shown in the figure, the integrated circuit microprocessor MPU of this example includes an external address bus interface device 1, a control signal input / output device 2, an external data bus interface device 3, a bus control device 4, and a memory management device 5. , Event reception device 6, instruction decoding device 7, memory management debug device 8, and instruction execution device 9. The functions of each of these parts are listed below.

External address bus interface device
A device for driving a 32-bit external address bus 10. This device includes a temporary storage circuit section for holding an address during an address output period, and a tri-state output drive circuit section for setting an address output to a floating state as necessary.

The 32-bit external address bus 10
Is composed of 31 signal lines used for designating an address for connecting a main memory device and an input / output device (not shown) and designating a specific one of the main memory device and the input / output device. .. In this example, since an external data bus having a 16-bit width is used as a byte address, the least significant 1 bit is not output, and the address is discriminated by the control output for controlling the upper and lower sides of the bus.

Control signal input / output device 2 is provided with an input drive circuit and an output drive circuit for inputting / outputting various control signals, and a control circuit portion attached to these circuit portions. A signal indicating the output timing of an address, a signal for externally transmitting the end of the bus cycle to the microprocessor, an encoded signal group for transmitting the type of the bus cycle to the outside, and a data bus via the device 2. A decoded signal group for controlling the upper and lower bits of each of them in units of 8 bits, a signal requesting the right to use the bus from outside, a signal returning an acknowledge thereto, a plurality of interrupt request signals and the like are input and output.

[0017] Internal External Data bus interface unit 3 includes a data bus drive and data ports and fetch unit, 16-bit external data bus 1
Connected to 3. The external data bus 13 is shared by both a machine language instruction code fetch operation from a main memory device (not shown) and a data read / write operation. The data bus driving device of the external data bus interface device 3 is a device for driving the 16-bit external data bus 13 for output and also for input operation.
The data bus driver includes a trastate output driver circuit for output and an input buffer circuit for converting a TTL level input to an internal CMOS level for input. Next, the fetch unit fetches the machine language instruction code via the external data bus 13 and transfers it to the instruction decoding unit 7. Data to be read and written is transmitted and received between the external side and each of the memory management device 5, the memory management debug device 8 and the instruction execution device 9 via the data port and the internal data bus 14.

In response to a request for a bus operation from the bus control device 4 instruction execution device 9 and the memory management device 5, the bus control device 4 receives the bus operations in descending order of priority.
The operations of the external address bus interface device 1, the external data bus interface device 3, and the control signal input / output device 2 are integrated to control these three devices in order to perform a meaningful bus operation.

The memory management unit 5 receives the upper 20 bits (indicated as signal 17 in the figure) of the 32-bit logical address generated by the instruction execution unit 9 and uses the associative memory inside to receive the logic. Attempt to translate address to physical address. When this conversion is performed, the converted address (shown as signal 16 in the figure) is transferred to the external address bus interface device 1. If the conversion cannot be performed, a logical address-to-physical address conversion table called a "page table" built in advance by the system software in the main memory is searched,
Try to convert again. The detailed configuration of this memory management device will be described later with reference to FIG.

The event accepting device 6 receives the interrupt signals 4S4, 9S1, 5S2, 8S1 and transmits them to the instruction decoding device 7 as the signal 6S1 from the highest priority.

Instruction decode unit 7 A pipelined decode section centered on a control unit using PLA, and a next instruction register for storing the finally decoded instruction and showing it to the instruction execution unit 9 are provided. ing. The decode section includes a controller section and a number of pipeline temporary storage sections. In this example, the PLA which is the center of the instruction decoding device uses two pre-charge type AND-OR PLAs.
The next instruction register includes a temporary storage device capable of storing two decoded instructions and a driving device.
When the interrupt is transmitted from the event receiving device 6, the instruction decoding device 7 generates an internal instruction indicating the interrupt,
This is delivered to the instruction execution device 9.

[0022] If the conversion to the physical address could not be from the memory management debug equipment 8 logical address memory management device 5 perform, "page table"
Is temporarily disabled, and instead, a debug interrupt signal 8S1 and a debug operation enable signal 8S2 are generated in order to cause a search operation, a substitute operation, etc. by software. The detailed configuration of this device will be described later with reference to FIG.

The instruction execution unit 9 receives the decoded instruction from the instruction decoding unit 7, processes the data, requests the bus operation to the bus control unit 4 if necessary, and outputs the logical address required for the bus operation. To occur. This instruction execution unit internally has an ALU for processing data, an adder and a subtractor for calculating an address, a register device for storing data, and a PLA for controlling each of these circuit parts. And a control device group mainly configured by.

Internal data bus 14 is a 32-bit internal data bus connecting the external data bus interface device 3, the memory management device 5, the memory management debug device 8 and the instruction execution device 9.

Signals and signal line code contents 11S A signal indicating the output timing of the address, a group of encoded signals for transmitting the type of the bus cycle to the outside, and the upper and lower bits of the data bus in 8-bit units. Output signal group for bus control such as decoded signal group for controlling, signal that returns acknowledge to request for bus right, 12S Signal for externally transmitting end of bus cycle to microprocessor, external signal for bus Input signal group such as a signal requesting a right of use, a plurality of interrupt request signals, etc. 15 Lower 12 bits of the internal address bus sent from the instruction execution unit 9 to the external address bus interface unit 1 16 External address from the memory management unit 5 .Bus interface device 20-bit bus for outputting a physical address to 1 17 Upper 20 bits of the internal address bus sent from the instruction execution unit 9 to the memory management unit 5 18 Attached to the bus for transferring the fetched machine language instruction code from the external data bus interface unit 3 to the instruction decoding unit 7 Control signal 19 Control signal group 2S1 attached to the bus for transmitting the decoded instruction from the instruction decoding device 7 to the instruction execution device 9 is received by the control signal input / output device 2 and sent to the bus control device 4. Partial processed input signal group 4S1 Bus control signal for controlling the external address bus interface device 1 transmitted from the bus control device 4S2 Transmitted from the bus control device 4 to the control signal input / output device 2, Control signal Bus control signal group 4S3 which is a source of output from the input / output device 2 Sent from the bus control signal 4 Bus control signal for controlling the external data bus interface device 3 4S4 External interrupt signal sent to the event reception device 6 via the bus control device 4S5 sent from the bus control device 4 to the instruction execution device 9 Control signal group 5S1 Signal sent from the memory management device 5 to the memory management debug device 8 indicating that the content stored in the associative memory does not match the logical address (BIT31-12) 5S2 From the memory management device 5 Page miss interrupt signal sent to the event reception device 6 5S3 Bus operation request signal sent from the memory management device 5 to the bus control device 6S1 To transmit the event received by the event reception device 6 to the instruction decoding device 7 Signal group 7S1 From instruction decoding device 7 to external data bus interface device 3 Prefetch request signal 8S1 Debug interrupt signal sent from the memory management debug device 8 to the event reception device 6 8S2 Debug operation enable signal for prohibiting normal operation sent from the memory management debug device 8 to the memory management device 9S1 Instruction execution Internal interrupt signal sent from the device 9 to the event reception device 6 9S2 Control signal group associated with a bus operation request sent from the instruction execution device 9 to the bus control device 4 9S3 Control sent from the instruction execution device 9 to the instruction decoding device 7 Signal group The memory management device and the memory management debug device in the integrated circuit microprocessor of this example will be further described with reference to FIG.

Memory management device 5 Associative memory unit 51 and first to fourth register devices 5
2, 53, 54, 55 and the first to fourth control devices 5
7, 59, 58, 56 are provided. Associative memory unit 51
Includes a data unit 511 and a comparison unit 512.

The data section 511 is realized as a 20-bit × 32-word RAM array using readable / writable normal static RAM cells. However,
The comparison unit 512 is provided as a unit equivalent to an address decoding unit required when configuring a normal RAM.
The data section 511 is an internal address bus (BIT31-
12) It is possible to read and write via 17 and also read to the external address bus interface device 1. The read / write control signal 58S1 is transmitted to the third controller 5
Generated by 8.

The comparison unit 512 is a static RAM having a 32-word structure corresponding to the plurality of comparators and the data unit 511.
The contents stored in the static RAM and the address arriving via the internal address bus 17 are sequentially compared with each other, and it is possible to determine a match or a mismatch. The stored contents in the static RAM are managed by the controller so that only one match occurs at a time. If a match is detected, a select signal is sent to the word in the data section that corresponds to the word in the comparison section. It is possible to read and write to the static RAM via the internal address bus 17. A read / write control signal 58S2 for this purpose
Are generated by the third controller 58.

(First Control Device 57) This is a device for performing control for reading the "page table" in the main memory when there is no match in the comparing section 512. When the non-coincidence signal 512S1 indicates a non-coincidence, the first controller 57 requests the bus controller 4 for the bus operation by using the bus operation request signal 5S3. However, when the "debug operation" command is input from the memory management debug device 8 side, no bus operation request is issued and the signal 5S1 indicating the mismatch is output to the memory management debug device 8 side. , Stop its operation.

(Third control device 58) Controls reading and writing with respect to the data section 511 and the comparison section 512 of the associative memory section 5. The contents of the first register device 52 are used as data for specifying and reading / writing a word to be accessed.

(First Register Device 52) This is a register device which serves as a window for reading and writing to the data section 511 and the comparison section 512 of the associative memory section 5. In this example, the instruction execution unit 9 can output to the internal address bus but cannot input it, and can read and write data by an instruction to the outside only through the internal data bus. I can't. Therefore, the data section 511 and the comparison section 512
In the case of reading / writing to / from, the first register device 52 is temporarily accessed through the internal data bus 14, and then the third control device 58 is controlled by the third control device 58 according to the contents of the register device 52. Read and write to 512. The result read out is also the register device 5
Stored in 2.

(Second register device 53) This is a register used to indicate the head address of the "page table" placed in the main memory. Normally, the system software builds a "page table" on the main memory and sets the start address in this register. Since this is an instruction-based operation, it is done via the internal data bus 14. In addition, the first control device 57 is
When a "table" is to be read, the contents of the third register device 54 are sent to this register device 53 for composition and used for accessing the "page table".

(Third register device 54) It has a function of selectively holding the addresses appearing on the internal address buses 15 and 17, and when a mismatch occurs in the comparing section 512, it causes the mismatch. The second and fourth register devices 53 and 55 by holding the address
The first controller 57 serves to supply the address to be used when accessing the "page table" via. It is readable and writable via the internal data bus 14, does not perform normal operation, and is read and used by software when using a "debug" interrupt.

(Fourth register device 55) This is a temporary register used when searching the "page table". The contents read from the "page table" are written to this register device from the external data bus interface device 3 via the internal data bus 14. This register detects from the content of the specific bit that the page does not exist in the main memory and detects the absence signal 55.
S1 is generated. In addition, the read contents are stored in the data section 51.
It is also possible to output to the internal address bus for transfer to 1. Furthermore, in order to enable multi-level "page table" searches that are commonly performed, a third
It is also possible to synthesize the contents of the register device 58 of FIG. 1 and its own contents to generate a deep level “page table” address and output it to the internal address bus.

(Second control device 59) A device for determining the absence signal 55S1 from the fourth register device 55.
If the page concerned does not exist in the main memory, the absence notification signal 59S1 is sent to the fourth controller 56 to generate the page miss interrupt signal 5S2. If the corresponding page exists in the main storage device, the write instruction signal 59S2 is generated and the content output from the fourth register device 55 to the third control device 58 is transferred to the data section 511. Set and instructs the comparator 512 to set the contents output from the third register device 54.

[0036] Memory Management Debug equipment 8 memory management debugging unit 8 includes a control device 83 of the fifth and sixth, a fifth register means 81.

(Fifth register device 81) A flag device for instructing whether the operation mode is a normal memory management operation or a debug operation is provided. In this example, it is composed of a single-bit flag and is logically a 32-bit wide register, but the substance is a flip-flop.
It consists of one flop and an interface circuit for the internal data bus. The software for debugging is
By manipulating this flag to the on state, the "debug" operation can be enabled.

(Fifth Control Unit 82) The state of the fifth register unit 81 is monitored, and when the state becomes a state indicating debug-on, the first control unit 57 is prohibited from normal operation. The debug operation permission signal 8S2 is output.

(Sixth Controller 83) First Controller 5
In response to the non-coincidence signal 5S1 from 7, the debug interrupt signal 8S1 is generated.

Operation FIG. 3 shows the flow of the address conversion operation performed by the microprocessor having the above configuration. The example shown here is the flow of processing when the configuration of the "page table" has two stages. As shown in the figure, step S1
The logical address received at is compared by the comparison unit 512 in the associative memory unit 51 to determine whether there is a match. If there is a match, the process proceeds to step S2, and the physical address obtained from the data section 511 is output as a signal 16 to the outside. This completes the address conversion process.

On the other hand, if no match is obtained in step S1, the process proceeds to step S3 to determine whether the "debug mode" is designated by the fifth register device 81 of the memory management debug device 8. To determine. If the debug mode is not designated, the "page miss" process after step S4 is executed. That is, the first-stage page table is read in step S4, and the page descriptor is inspected in step S5. If the page of interest exists in this page table, the page of the second stage in step S6
The table is read and the page descriptor is checked in step S7. If the target page exists,
After updating the contents of the comparison 512 and the data part 511 in step S8, the data part is output as a physical address in step S9.

When a "page miss" in which the target page does not exist in steps S5 and S7, control is transferred to steps S10 and S11, and "page miss" processing is executed.

Next, when the debug mode is detected in step S3, the control shifts to the side of step S21. In step S21, the debug interrupt signal 8S1
Is generated to prohibit the normal operation described above. Next, in step S22, the control is shifted to the debug routine. Then, as shown in step S23, the address conversion is performed by software processing in this debug routine.

In the above example, the "page table" is composed of two stages, and various control devices are logically designed. However, the "page table" can be changed from a simple one-step search to an arbitrary n-step by simply changing the logic of the control device without making any correction to the hardware configuration of the register device or the like. ..

[0045]

As described above, according to the present invention, an integrated circuit microprocessor having a paging-type memory management device using an associative memory device is provided with a mechanism for debugging the associative memory operation. Has been adopted. Therefore, according to the present invention, such software debugging can be easily realized by utilizing the built-in mechanism in the development of the virtual memory management software. Therefore, it is possible to easily debug such a virtual storage system without using expensive conventional dedicated equipment, and to efficiently develop such a system.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing a main part in an integrated circuit microprocessor which is an embodiment of the present invention.

FIG. 2 is a block diagram showing in detail a memory management device and a memory management debug device in FIG.

FIG. 3 is a flowchart showing a flow of address conversion processing using the associative storage device according to the embodiment of FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Integrated circuit microprocessor 5 ... Memory management device 8 ... Memory management debug device 16 ... 20-bit bus for physical addresses output from the memory management device 51 ... Associative memory unit 511・ ・ ・ Data unit 512 ・ ・ ・ Comparison unit 52, 53, 54, 55 ・ ・ ・ Register device in the memory management device 56, 57, 58, 59 ・ ・ ・ Control device in the memory management device 81 ・ ・ ・ Memory Register device in management debug device 82, 83 ... Control device in memory management debug device 5S1 ... Mismatch signal 5S2 ... Page miss interrupt signal 8S1 ... Debug interrupt signal

Claims (1)

[Claims] 1. A logical address generating means for generating a logical address, and a page number included in the logical address. When the page number is written in advance, the corresponding block number is output to output the page number. If there is not, an associative storage means for outputting that effect,
When the page number does not exist, page fault detection means for detecting whether or not the block number corresponding to the page number is written on the page table expanded in the main storage device, and the page fault detecting unit. A page fault processing means for updating the page table based on the detection result of the detection means, and a physical address on the main storage device based on the block number output from the associative storage means and the information contained in the logical address. In the integrated circuit microprocessor having a physical address generating means for performing, at least a debug mode designating means for designating a debug mode for debugging the processing operation by the page fault processing means, and when the debug mode is designated by the designating means, The page fault process Paging monitoring mechanism characterized by having a interrupt generating means prohibits the operation by means for generating a debug interrupt.