JPH0697438B2 - Storage device - Google Patents

Description

The present invention relates to a storage device.

[Prior Art] FIG. 2 is a block diagram showing an example of the configuration of a computer system using a conventional cache memory.
In the figure, 1 is a CPU unit, 2 is a cache memory unit, 3 is a main memory unit, 4a, 4b and 4c are address buses, and 5a and 5b.
And 5c are buses for data, 6 is a hit signal for notifying the CPU unit that the cache memory unit is hit, 7 is the address and data supplied by the CPU unit 1 to the address bus 4a and the data bus 5a, respectively. 2 is a registration permission signal indicating that registration should be made in 2. FIG. 3 is a block diagram showing an internal configuration of the cache memory unit 2 of FIG. 2 which is composed of a conventional associative memory unit and a RAM unit, in which 8 is an associative memory unit for registering an address, Reference numeral 9 is a RAM unit for registering data, 10 is an address input latch for latching an address to be registered in the associative memory unit, 11 is data for being registered in the RAM unit 9 or being output from the RAM unit 9. Data input / output latch,
12 detects if the cache memory is hit,
A hit detection circuit that sends a hit signal 6 to the CPU unit 1 when a hit occurs, 13 a branch generation signal output from the decoder circuit 15, 15 a decoder circuit in the CPU unit 1, and 16 a cache in the CPU unit 1. A memory unit control circuit, 17 is a counter circuit in the cache memory unit control circuit 16.

Next, the operation of the conventional cache memory will be described with reference to FIG. When the CPU unit 1 accesses the data in the main storage unit 3, the CPU unit 1 first supplies the address corresponding to the desired data to the address bus 4a. The address bus 4a is connected to the main memory unit 3, and is also connected to the cache memory unit 2 via the address bus 4b. Is the desired data registered using this address in the cache memory unit 2? Search for something. If registered, the hit signal 6 is validated and the data is supplied to the data bus 5a via the data bus 5b. Since the cache memory unit 2 uses a memory element that can be accessed faster than the main storage unit 3, it can supply data faster than the main storage unit 3. Therefore, when the desired data is registered in the cache memory unit 2, the CPU unit 1 can fetch and process the data faster than accessing the main storage unit 3. On the other hand, if it is not registered, the cache memory unit 2 invalidates the hit signal 6 and informs the CPU unit 1 that it is not registered. Then, the CPU unit 1 requests from the main memory unit 3 via the data bus 5b. Capture the data of. At this time
Branch occurrence signal 13 from decoder circuit 15 inside CPU unit 1
Is generated and sent to the counter circuit 17 in the cache memory unit control circuit 16 to enable the registration permission signal 7 a predetermined number of times, the cache memory unit 2 causes the address bus 4b and the data bus 4b. Since the address (that is, the address corresponding to the data accessed by the CPU unit 1 now) and the data (that is, the data accessed by the CPU unit 1 now) are respectively registered in 5b, the CPU unit next When 1 accesses the data, it can be fetched from the cache memory unit 2 which can be accessed at high speed.

Next, the registration operation of the cache memory unit 2 will be described with reference to FIG. The cache memory unit 2 registers an address for searching whether or not the target data is registered in the cache memory unit 2 and an address corresponding to the address as a set. First, the address and the data corresponding to that address are
4b and data bus 5b. Then, when the registration permission signal 7 indicating that the address and data currently supplied to the address bus 4b and the data bus 5b should be registered becomes valid, the address and the data are respectively transferred to the address input latch 10 and the data input / output latch. After being fetched by 11, it is registered in corresponding positions of the associative memory unit 8 and the RAM unit 9 via the address bus 4c and the data bus 5c, respectively. However, if the registration permission signal 7 is invalid, the address and data are not taken into the address input latch 10 and the data input / output latch 11, respectively, and the associative memory unit 8 and RA
It is not registered in M section 9.

When this cache memory is used as a branch target buffer, CP and address and data registration control
This is performed by the cache memory unit control circuit 16 inside the U unit 1. When a branch is generated by a branch instruction and a set of N sets of addresses after the branch and data corresponding to the address is registered, the cache memory unit control circuit 16 inside the CPU unit 1 outputs the address and the data, respectively. When supplied to the address bus 4b and the data bus 5b, the counter circuit 17 enables the registration permission signal 7 up to N times after branching to N + 1.
It is invalid after the first time. Therefore, the address input latch
10 and the data input / output latch 11 have N and
The group is registered.

[Problems to be Solved by the Invention] Since the conventional cache memory is configured as described above, for example, when it is used as a branch target buffer, the address and the data are stored in the address bus 4a.
CPU and data bus 5a respectively
Since the registration permission signal 7 is also supplied from the unit 1, there is a problem in that the CPU unit 1 performs the control for supplying this signal, which increases the load on the CPU unit.

The present invention has been made to solve the above problems, and by providing a counter means inside a storage device, the counter function, which has been a burden on the arithmetic processing means side in the past, is provided on the arithmetic processing means side. Not required, therefore
The purpose is to reduce the burden on the arithmetic processing means side.

[Means for Solving the Problems] A storage device according to the present invention is provided with an address processing path and data for an arithmetic processing means for performing a logical operation processing operation and for generating a registration request signal from an instruction decoding means included therein. First storage means connected via a path for performing data input, storage and output operations in response to address input, and address and data input in response to a registration permission signal,
Temporary holding means for performing the temporary holding and output operations are connected to each other, and further connected to the temporary holding means for second storage means for performing address input and storage and data input, storage and output operations, and arithmetic processing. The counter means is connected to the means and generates a predetermined number of registration permission signals in response to the registration request signal and provides the temporary holding means with the counter means.

[Operation] The memory device according to the present invention is connected to the arithmetic processing means for the logical operation processing operation and generating the registration request signal from the instruction decoding means included therein via the address path and the data path, First storage means for inputting, storing and outputting data in response to an input, and inputting an address and data in response to a registration permission signal,
Temporary holding means for performing the temporary holding and output operations are connected to each other, and further connected to the temporary holding means for second storage means for performing address input and storage and data input, storage and output operations, and arithmetic processing. Means for generating the registration permission signal a predetermined number of times in response to the registration request signal and providing the temporary holding means with the counter means, the arithmetic processing means generates the registration request signal. Since it is not necessary to repeatedly generate the registration permission signal a predetermined number of times, it is possible to reduce the load on the arithmetic processing means.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. First
The figure shows an associative memory unit and a RAM according to an embodiment of the present invention.
FIG. 2 is a block diagram showing an internal configuration of a cache memory unit 2 composed of parts, in which 1 is a CPU unit, 2 is a cache memory unit, 4a, 4b and 4c are address buses,
5a, 5b and 5c are buses for data, 6 is a hit signal that informs the CPU unit 1 that the cache memory unit 2 is hit, and 7 is an address and data supplied by the CPU unit 1 to the address bus 4a and the data bus 5a, respectively. Is to be registered in the cache memory, 8 is an associative memory unit for registering addresses, 9 is a RAM unit for registering data, and 10 is an address to be registered in the associative memory unit 8. Address input latch for latching data, 11 is a data input / output latch for latching data to be registered in the RAM section 9, 12
Is a hit detection circuit that detects whether or not the cache memory has been hit, and sends a hit signal 6 to the CPU 1 if there is a hit, and 13 is a CP when a branch occurs due to a branch instruction.
The branch occurrence signal sent from the U unit 1, 14 is set to an initial value "0" by the branch occurrence signal 13, and the counter value is incremented by +1 each time an address is supplied thereafter, and it is predetermined. A counter circuit that repeatedly generates the registration permission signal 7 until the value (N) is reached, 15 is the CPU unit 1
A decoder circuit inside 16 and a cache memory control circuit 16 inside the CPU 1.

Next, the operation will be described. When registering a set of N sets of addresses after a branch occurs and data corresponding to the address, first, the decoder circuit 15 in the CPU 1 decodes the instruction to determine that the instruction is a branch instruction. Then, the decoder circuit 15 enables the branch occurrence signal 13. In response to this, the counter circuit 14 sets the counter value to an initial value (here, "0") and validates the registration permission signal 7. This registration permission signal 7
Are enabled, the address input latch 10 and the data input / output latch 11 are connected to the address bus 4b and the data bus, respectively.
The branch destination address on 5b and the data corresponding to that address are fetched. The fetched address and data are sent to the associative memory unit 8 and the RAM unit 9 via the address bus 4c and the data bus 5c, respectively, and written in the corresponding positions. Then, the second address from the branch destination and the data corresponding to the address are respectively transferred to the address bus.
When supplied to 4a and data bus 5a, the counter value is +
One is added to become "1", and the registration permission signal 7 is validated. Then, registration is performed in the same manner as described above. The registration operation is repeated as described above, and up to the Nth address and data set is registered. After this, the branch destination N + 1th address and the data corresponding thereto are
When supplied to the address bus 4a and the data bus 5a, respectively, the counter value becomes "N" and the registration permission signal 7 is invalidated. Then, the registration permission signal 7 is not generated until the counter value is set again to the initial value "0" by the branch generation signal 13 later. Therefore, the number of registered addresses and data is up to N. After that, when a new branch occurs and it becomes necessary to register it in the cache memory unit 2, the branch generation signal 13 sets the counter value to the initial value "0" again, and the same operation as above is performed. A set of the first N sets of addresses and data corresponding to the addresses is registered.

In the above embodiment, the initial value of the counter circuit 14 is set to "0".
However, the initial value may be set to “N” and decremented until the value becomes “0”, and the registration permission signal 7 may be invalidated.

[Effects of the Invention] As described above, according to the present invention, the address processing path and the data processing path are provided to the arithmetic processing means for the logical operation processing operation and for generating the registration request signal from the instruction decoding means included therein. First storage means connected via the input and storing and outputting data in response to an address input, and temporary holding for inputting, temporarily holding and outputting an address and data in response to a registration permission signal Means are connected to each other, and are further connected to a temporary holding means, and are connected to a second storage means for inputting and storing an address and for inputting, storing and outputting data, and an arithmetic processing means for receiving a registration request signal. In response, since the counter means for generating the registration permission signal of a predetermined number of times and giving it to the temporary holding means is provided, the burden on the arithmetic processing means is reduced. Therefore, the processing capacity of the arithmetic processing means can be used more effectively.

[Brief description of drawings]

FIG. 1 shows an associative memory unit and RA showing an embodiment of the present invention.
FIG. 2 is a block diagram of a cache memory unit configured by an M unit, FIG. 2 is a block diagram showing an example of the configuration of a computer system using a conventional cache memory, and FIG. 3 is a conventional associative memory unit. FIG. 3 is a block diagram of a cache memory unit configured by a RAM unit and a RAM unit. In the figure, 1 is a CPU unit, 2 is a cache memory unit, 3
Is a main memory, 4a, 4b and 4c are address buses, 5a,
5b and 5c are data buses, 6 is a hit signal, 7 is a registration permission signal, 8 is an associative memory section, 9 is a RAM section, 10 is an address input latch, 11 is a data input / output latch, 12 is a hit detection circuit, Reference numeral 13 is a branch generation signal, 14 is a counter circuit, 15 is a decoder circuit, 16 is a cache memory unit control circuit, and 17 is a counter circuit. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (7)

[Claims] 1. An arithmetic processing means for performing a logical operation processing operation and for generating a registration request signal from an instruction decoding means contained therein, and the arithmetic processing means are connected via an address path and a data path. And a first storage means for inputting, storing, and outputting data in response to an address input, and the arithmetic processing means and the first storage means are connected via the address path and the data path for registration. Temporary holding means for inputting, temporarily holding and outputting addresses and data in response to a permission signal; and second holding means connected to the temporary holding means for inputting and storing addresses and inputting, storing and outputting data Connected to the storage means and the arithmetic processing means, generates a registration permission signal for a predetermined circuit in response to the registration request signal, and temporarily holds the registration permission signal. Storage device comprising a counter means for providing the step. 2. The storage device according to claim 1, wherein the second storage means includes address storage means and data storage means. 3. The storage device according to claim 1, wherein said temporary holding means includes address input latch means and data input / output latch means. 4. The storage device according to claim 1, wherein the arithmetic processing means includes a central processing unit. 5. The storage device according to claim 1, wherein the first storage means includes a main storage device. 6. The storage device according to claim 1, wherein said instruction decoding means includes a decoder circuit. 7. The storage device according to any one of claims 1 to 6, wherein the registration request signal is a branch occurrence signal.