JPS648459A - Storage device - Google Patents

Storage device

Info

Publication number
JPS648459A
JPS648459A JP62164332A JP16433287A JPS648459A JP S648459 A JPS648459 A JP S648459A JP 62164332 A JP62164332 A JP 62164332A JP 16433287 A JP16433287 A JP 16433287A JP S648459 A JPS648459 A JP S648459A
Authority
JP
Japan
Prior art keywords
signal
address
registration
data
counter value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62164332A
Other languages
Japanese (ja)
Other versions
JPH0697438B2 (en
Inventor
Shunichi Iwata
Naoyoshi Nakano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62164332A priority Critical patent/JPH0697438B2/en
Publication of JPS648459A publication Critical patent/JPS648459A/en
Publication of JPH0697438B2 publication Critical patent/JPH0697438B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To reduce the load of an arithmetic processing means by providing the arithmetic processing means side constituting a storage device only with a function for generating a registration request signal and omitting the necessity of generation of a registration permitting signal repeated by the fixed number of times. CONSTITUTION:In case of registering the N groups of addresses obtained after branch generation and the groups of data corresponding to the addresses, a branch generation signal 13 is generated from a decoder circuit 15 in a CPU 1 and a counter value is set up to an initial value '0' in a counter circuit 14 to validate a registration permitting signal 7 at first. Then, an address latch 10 and a data latch 11 enter a branched address and data corresponding to the address and sent the input data to an associative memory part 8 and a RAM part 9. When the 2nd address and data are inputted from the branched parts, '1' is added to the counter value and the signal 7 is validated again. When the counter value goes to 'N' after repeating said operation, the signal 7 is invalidated and registration is restarted from the initial value '0'.
JP62164332A 1987-06-30 1987-06-30 Storage device Expired - Lifetime JPH0697438B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62164332A JPH0697438B2 (en) 1987-06-30 1987-06-30 Storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62164332A JPH0697438B2 (en) 1987-06-30 1987-06-30 Storage device

Publications (2)

Publication Number Publication Date
JPS648459A true JPS648459A (en) 1989-01-12
JPH0697438B2 JPH0697438B2 (en) 1994-11-30

Family

ID=15791160

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62164332A Expired - Lifetime JPH0697438B2 (en) 1987-06-30 1987-06-30 Storage device

Country Status (1)

Country Link
JP (1) JPH0697438B2 (en)

Also Published As

Publication number Publication date
JPH0697438B2 (en) 1994-11-30

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