JP2014197889A - Image processor, method of controlling the same, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem in which in an image processor including a plurality of image processing circuits, a dedicated memory attached to an image processing circuit in a temporarily stopped state due to an operation mode cannot be used from another image processing circuit during operation.SOLUTION: An image processor comprises: a plurality of image processing circuits that process image data; a shared memory that is shared by the plurality of image processing circuits; and a memory control circuit that allocates an input buffer of the image processing circuits, an output buffer of the image processing circuits, and a reference data storage area of the image processing circuits to the shared memory.

Description

  The present invention relates to an image processing apparatus, a control method therefor, and a program.

  In recent years, scanners, video cameras, and the like have become widespread as input devices. As output devices, various color printers using an ink jet, dye thermal sublimation type, or electrophotographic system are widely used. In general, as typical image processing used in these color input / output devices, there are “color space conversion” and “spatial filter processing”.

  “Color space conversion” is a process of converting the color space of the input device to the color space of the output device in order to solve the problem relating to color reproducibility between input / output devices for color images and the like. Specifically, there are cases where the entire series of image processing such as input γ correction, luminance density conversion, masking, black generation, UCR, output γ correction, and the like, and only certain processes among them are indicated.

  “Spatial filter processing” refers to local (neighboring) image processing that performs some operation using all pixels included in a spatial filter region including pixels to be processed (hereinafter referred to as processing pixels). is there. For example, it refers to processing such as edge enhancement processing and blurring processing.

  In an image processing circuit that realizes such image processing, in addition to various arithmetic circuits, reference data necessary for various arithmetic circuits is temporarily stored, and pixel values of processed pixels of a color image are temporarily stored. Often comes with a memory to do. The memory used in these image processing circuits will be described in detail with specific examples.

  In the previous color space conversion, the digital image signals of the three colors of the input device are often referred to at the same time and converted into the digital image signals of the three colors or the four colors of the output device. Here, the three colors of the input device indicate, for example, three colors of red, blue, and green (hereinafter abbreviated as “RGB”). The three colors of the output device are, for example, three colors of cyan, magenta, and yellow (hereinafter abbreviated as “CMY”). The four colors of the output device indicate, for example, four colors of cyan, magenta, yellow, and black (hereinafter abbreviated as “CMYK”). Further, in the case of an electrophotographic copying machine, the engine characteristics of the printer change with the operating time, so that periodic calibration is required. In such a case, conversion from the four colors of the output device (for example, “CMYK”) to the four colors of the output device (for example, “C′M′Y′K ′”) is also necessary.

  As means for realizing the color space conversion, the conversion result is stored in advance in a memory as a lookup table (hereinafter abbreviated as “LUT”), and the conversion result is input from the LUT to the input digital image signal. There is a way to output.

  In this color space conversion method using an LUT, an LUT used for a three-color input digital image signal is referred to as a three-dimensional lookup table (hereinafter abbreviated as “3D-LUT”). The LUT used for the four-color input digital image signal is called a four-dimensional lookup table (hereinafter abbreviated as “4D-LUT”).

  Here, when the three-dimensional input color space (RGB space) is divided into 16 in each axial direction, the 3D-LUT requires a memory having the number of entries of the cube of 16 (see Patent Document 1). Accordingly, in order to convert the RGB space to the CMYK space, if the data amount is 4 bytes per entry, a memory having a capacity of 16 Kbytes is mounted as a dedicated memory (a part of the circuit) of the color space conversion circuit.

  In addition, when the four-dimensional input color space (CMYK space) is divided into 16 in each axial direction, the 4D-LUT requires a memory having the number of entries to the fourth power of 16 (16 times the size of the 3D-LUT). It becomes. That is, in order to convert the CMYK space into the C′M′Y′K ′ space, if the data amount is 4 bytes per entry, a memory having a capacity of 256 Kbytes is a dedicated memory for the color space conversion circuit (part of the circuit). Implemented as

  In the case of the previous spatial filter processing, image processing is performed pixel by pixel along the main scanning direction from the upper left pixel of the digital image data, and image processing is performed up to the right end pixel. Then, the image is advanced by one pixel in the sub-scanning direction, and image processing is performed again from the leftmost pixel to the rightmost one pixel along the main scanning direction. This series of image processing is repeated until the image processing for the lower right pixel of the digital image data is completed, and desired image processing is performed.

  In such a technique, a large memory capacity is required as the width of the digital image data in the main scanning direction increases. For example, when an A4 size image is read by a scanner having a resolution of 600 dpi and converted to digital image data, the width of the digital image data is 4953 pixels. When one pixel is composed of the above-described RGB and RGB has a data amount of 3 bytes, a delay memory for 2 lines is required for the 3 × 3 spatial filter area. A memory having a capacity of about 29 Kbytes (4953 pixels × 2 lines × 3 bytes) is mounted as a dedicated memory (a part of the circuit) of the spatial filter circuit.

  Further, consider a case where one pixel is composed of the above-described CMYK, and CMYK has a data amount of 4 bytes. In this case, for the 3 × 3 spatial filter area, a memory having a capacity of about 39 Kbytes (4953 pixels × 2 lines × 4 bytes) is mounted as a dedicated memory for the spatial filter circuit (part of the circuit). Is done.

  In recent years, various image processing circuits are required in an image processing apparatus in order to improve the image quality and enhance the functions of products. However, the processing contents of the image processing circuit cannot be changed by exchanging a program like a CPU. Therefore, among various image processing circuits of the image processing apparatus, one image processing circuit is operated by changing the operation mode of various products, and another image processing circuit is unnecessary and temporarily stopped. The situation of being allowed to happen.

  At this time, the dedicated memory attached to the stopped image processing circuit is also stopped at the same time, and cannot be used from other operating image processing circuits. As described above, the memory capacity connected to the image processing circuit as a dedicated memory is very large, and the circuit scale of the dedicated memory accounts for a large proportion of the entire image processing LSI. These memories are temporarily wasted, and hardware resources are not effectively used (the activation rate of the entire image processing LSI is not improved).

JP 2007-67956 A

  As described above, in the image processing apparatus including a plurality of image processing circuits, there is a problem that the dedicated memory attached to the image processing circuit that is temporarily stopped depending on the operation mode cannot be used from other image processing circuits in operation.

  The present invention has been made in view of the above-described problems. By sharing the dedicated memories of a plurality of image processing circuits with each other, even when some image processing circuits do not operate, other image processing circuits in operation It aims at providing the technology that can be used.

An image processing apparatus according to the present invention for solving the above problems is as follows.
A plurality of image processing circuits for processing image data;
A shared memory shared by the plurality of image processing circuits;
A memory control circuit that allocates an input buffer of the image processing circuit, an output buffer of the image processing circuit, and a reference data storage area of the image processing circuit to the shared memory;

  According to the present invention, by sharing the dedicated memories of a plurality of image processing circuits with each other, even when some of the image processing circuits do not operate, an area for the circuit is allocated to other operating image processing circuits. be able to. Thereby, it is possible to improve the activity rate of the memory that is always used for image processing.

1 is a block diagram illustrating an example of the overall configuration of an image processing apparatus 10. 3 is a block diagram illustrating an example of a circuit configuration of an image processing unit 150. FIG. 5 is a diagram illustrating an example of a shared memory control circuit 270. FIG. 5 is a diagram for explaining an example of an address map of a shared memory 280. FIG. It is a figure which shows an example of the circuit structure of the image process part of the state which can stop the clock of an unused memory, and an example of the address map of a shared memory. It is a flowchart which shows an example of a shared memory control process. It is a figure explaining an example of operation | movement of the band process corresponding to the 4th Embodiment of invention.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

[First Embodiment]
FIG. 1 is a block diagram showing an example of the overall configuration of the image processing apparatus 10 according to the first embodiment. In FIG. 1, the image reading unit 120 includes a lens 124, a CCD sensor 126, an A / D conversion unit 127, and the like. In the image reading unit 120, image information of the original 110 formed on the CCD sensor 126 through the lens 124 is converted into analog electric signals of R (Red), G (Green), and B (Blue) by the CCD sensor 126. The The image information converted into the analog electric signal is input to the A / D conversion unit 127, corrected for each color of R, G, and B, and then subjected to analog / digital conversion (A / D conversion). Thus, a digitized full color signal (referred to as a digital image signal) is generated. A digital image signal composed of a set of R, G, and B represents one pixel of the image.

  The CPU 102 controls a DMAC (Direct Memory Access Controller) 192 for writing, and stores the generated digital image signal as image data in the RAM 106 of the CPU circuit unit 100 via the shared bus 190. Next, the CPU 102 controls the reading DMAC 194 to read the image data stored in the RAM 106 and input it to the image processing unit 150.

  The image processing unit 150 performs, for example, correction of individual differences of reading elements of a sensor device such as a scanner and color correction such as input gamma correction on the input digital image signal, normalizes the read image, and maintains a certain level. Create image data. The digital image signal subjected to these processes is again stored in the RAM 106 by the writing DMAC 196 under the control of the CPU 102.

  The image processing unit 150 can perform printing on the input digital image signal by performing input color correction processing, spatial filter processing, color space conversion, density correction processing, and image processing as preprocessing for printing. Image data can also be created. Also in this case, the data is stored in the RAM 106 by the write DMAC 196 as described above.

  Finally, the CPU 102 controls the reading DMAC 198 to read the image processed image data stored in the RAM 106, performs halftone processing, and outputs it to the image printing (printer) unit 170. The image printing (printer) unit 170 includes a print output unit (not shown) such as a raster plotter using an inkjet head, a thermal head, or the like, for example, and an image is printed on paper by an input digital image signal. Record.

  The CPU circuit unit 100 includes a CPU 102 for arithmetic control, a ROM 104 for storing fixed data and programs, a RAM 106 for temporarily storing data and loading programs, an external storage device 108, and the like. The CPU circuit unit 100 controls the image reading unit 120, the image processing unit 150, the image printing (printer) unit 170, and the like, and comprehensively controls the sequence of the image processing apparatus 10 of the present embodiment.

  The external storage device 108 is a storage medium such as a disk that stores parameters, programs, and correction data used by the image processing apparatus 10 according to the present embodiment. The data, programs, and the like in the RAM 106 are loaded from the external storage device 108. It does not matter as a configuration.

  Next, the image processing unit 150 in FIG. 1 will be described in detail. FIG. 2 is a block diagram illustrating an example of a circuit configuration of the image processing unit 150 of the present embodiment.

  A digital image signal is input to the image processing unit 150, and image processing described below is executed. The image processing unit 150 includes an image processing input circuit 210, a spatial filter processing circuit (1) 220, a spatial filter processing circuit (2) 230, a color space conversion circuit 240, an output γ correction circuit 250, and an image processing output circuit 260. Configured.

  Hereinafter, the image processing input circuit 210, the spatial filter processing circuit (1) 220, the spatial filter processing circuit (2) 230, the color space conversion circuit 240, the output γ correction circuit 250, and the image processing output circuit 260 will be described in detail.

[Image processing input circuit 210]
A digital image signal 205 is input via a read DMAC 194 outside the image processing unit 150. The digital image signal 205 is composed of R, G, and B luminance signals. The image processing input circuit 210 is capable of controlling a double buffer memory and receives the digital image signal 205 and temporarily stores it in the buffer. On the other hand, the digital image signal stored in the previous buffer is read and output as a digital image signal 215.

[Spatial Filter Processing Circuit (1) 220 / Spatial Filter Processing Circuit (2) 230]
The digital image signal 215 output from the image processing input circuit 210 is input to the spatial filter processing circuit (1) 220. The spatial filter processing circuit (1) 220 can control the delay memory for performing the filter processing, and performs smoothing and edge processing based on the digital image signal already stored in the delay memory and the input digital image signal 215. Perform local (neighboring) image processing such as enhancement. The processing result is output as a digital image signal 225. Simultaneously with the processing, unnecessary digital image signals among the digital image signals already stored in the delay memory are replaced with the input digital image signal 215.

  The spatial filter processing circuit (2) 230 also receives the input of the digital image signal 225, performs the same processing as the spatial filter processing circuit (1) 220, and outputs it as a digital image signal 235.

[Color space conversion circuit 240]
The digital image signal 235 output from the spatial filter processing circuit (2) 230 is input to the color space conversion circuit 240. The color space conversion circuit 240 can control a memory that holds a 3D-LUT or 4D-LUT for color conversion. The color space conversion circuit 240 obtains reference data from the 3D-LUT, performs an interpolation operation, and converts the luminance signals R, G, B of the input digital image signal 235 into luminance signals R ′, G ′, Conversion into B ′, density signals C, M, Y and density signals C, M, Y, K. The conversion result is output as a digital image signal 245. When the input digital image signal 235 is four components of density signals C, M, Y, and K, the color space conversion circuit 240 acquires reference data from the 4D-LUT and performs an interpolation operation. The density signals C, M, Y, and K of the digital image signal 235 are converted into other density signals C ′, M ′, Y ′, and K ′, and are output as the digital image signal 245.

[Output γ Correction Circuit 250]
Digital image signals (luminance signals R ′, G ′, B ′, density signals C, M, Y, etc.) 245 output from the color space conversion circuit 240 are input to the output γ correction circuit 250. The output γ correction circuit 250 can control a memory that holds a 1D-LUT for performing color correction unique to the output device device. The output γ correction circuit 250 acquires reference data from the 1D-LUT, performs interpolation calculation, corrects the input digital image signal 245, and outputs the digital image signal 255 as a digital image signal 255.

[Image processing output circuit 260]
The image processing output circuit 260 is capable of controlling a memory with a double buffer configuration and receives the digital image signal 255 and temporarily stores it in the buffer. On the other hand, the digital image signal stored in the previous buffer is read, and the digital image signal 265 is output to the RAM 106 via the write DMAC 196 outside the image processing unit 150.

  The plurality of image processing circuits 210 to 260 constituting the image processing unit 150 all perform image processing by controlling the memory. Each processing circuit operates the shared memory control circuit 270 via the control port 272 for the memory control. Each of the image processing circuits sends a memory access method designation signal 274 to the shared memory control circuit 270, receives a memory access end signal 276 from the shared memory control circuit 270, and synchronizes with the shared memory control circuit 270. Realize. When the memory control from each of the image processing circuits is data write (write), each of the image processing circuits writes the write (write) data simultaneously or continuously with the sending of the memory access method designation signal 274. Send to 270.

  When the memory control from each of the image processing circuits is data read (read), each of the image processing circuits receives read data from the shared memory control circuit 270. When the memory control is data read (read), each of the image processing circuits can determine the completion of the memory control by receiving the read (read) data. Therefore, a mounting method in which the memory access end signal 276 is omitted, or a mounting method in which the memory access end signal 276 is received at the same time, in advance, or at the end of reception of read data.

  Shared memory control circuit 270 is connected to shared memory 280, read DMAC 290, and write DMAC 294. However, if all of the image processing circuits do not support the read cache mode described later, the shared memory control circuit 270 need not be connected to the read DMAC 290. If all of the image processing circuits do not support the write cache mode described later, the shared memory control circuit 270 does not need to be connected to the write DMAC 294. Even if any of the image processing circuits supports the read cache mode or the write cache mode, the read DMAC 290 and the write DMAC 294 may be outside the image processing unit 150. At that time, the shared memory control circuit 270 may be mounted by connecting to a control port for controlling the read DMAC 290 or the write DMAC 294.

  The shared memory 280 of the present embodiment is composed of one or more memories (illustrated by the memories 280-1 to 280-N), and constitutes the shared memory in consideration of the processing performance of the image processing circuits 210 to 260. The number of memories to be determined is determined. At this time, the shared memory 280 is a virtual memory formed by integrating a plurality of memories (substances).

  Also, in LSI mounting, the circuit scale increases when the memory of a certain capacity is mounted by dividing it into a plurality of sub memories having a smaller capacity. This is because one memory requires a region for securing power and a region for connecting a test circuit for testing the memory. However, when the memory is divided into a plurality of sub-memory, the amount of data that can be read / written in parallel increases, so it is easy to improve the processing performance per cycle. The image processing circuits 210 to 260 require a total of eight control ports 272.

  For example, if the processing performance of the image processing circuits 210 to 260 is 1/10 [pixel / cycle] in a consumer printer image processing apparatus, each of the image processing circuits controls the memory at a rate of once per 10 clocks. It will do. In this case, the shared memory 280 may be realized only by the memory (1) 280-1.

  On the other hand, if the processing performance of the image processing circuits 210 to 260 is 1/1 [pixel / cycle] in a printer image processing apparatus for an office machine, the shared memory 280 includes at least 10 memories (1) to (N). ) (N = 10). Note that the spatial filter processing circuit is approximated as described above when it is assumed that memory control is required twice for reading and writing data.

  The shared memory control circuit 270 also controls a chip select signal (cs), a read / write identification signal (rw), and an address signal (address) for controlling the memories (1) 280-1 to (N) 280-N. , Write data (write_data) is output. Further, read data (read_data) is received from the memory (1) 280-1 to the memory (N) 280-N (these signals are collectively referred to as a memory control signal 284).

  The allocation of the used area of the shared memory 280 according to the operation mode of the present embodiment will be described with reference to FIG. First, the address map described in case 1 corresponding to the first operation mode shows a case where all of the image processing circuits described in FIG. 2 are used.

  The double buffer used in the image processing input circuit 210 is realized by switching between the input buffer 410 and the input buffer 412. The spatial filter processing circuit (1) 220 uses a delay memory (1) 420, and the spatial filter processing circuit (2) 230 uses a delay memory (2) 430. The color space conversion circuit 240 uses a three-dimensional LUT 440 and the output γ correction circuit 250 uses a one-dimensional LUT (1) 450. The double buffer used in the image processing output circuit 260 is realized by switching between the output buffer 460 and the output buffer 462.

  Case 2 and case 3 shown in FIG. 4 show an example of an address map and a configuration example of an image processing circuit in second and third operation modes different from the first operation mode. In case 2, the spatial filter processing circuit (1) 220 of the case 1 is stopped, and the unused area of the shared memory 280 is used by the input buffers 410 and 412 of the case 1, the delay memory (2) 430, and the output buffers 460 and 462. . More specific processing contents will be described in the fourth embodiment. In case 2, the three-dimensional LUT 440 and the one-dimensional LUT (1) 450 have the same capacity, although the start addresses on case 1 and shared memory 280 are different.

  In case 3, the spatial filter processing circuit (1) 220 and the spatial filter processing circuit (2) 230 of the case 1 are stopped, and unused areas are allocated to the color space conversion circuit 240 and the output γ correction circuit 250. Yes. In an example of case 3, the input digital image signal has four colors of C, M, Y, and K, and the color space conversion circuit 240 performs C ′, M ′, Y ′ by color space conversion using a four-dimensional tetrahedral interpolation method. , K 'are output. Since the 4D-LUT required at this time also requires 256 Kbytes as described above, in the illustrated example, the cache data is expanded in the data cache 440 for the four-dimensional LUT in the shared memory 280. The output γ correction circuit 250 is also assigned a one-dimensional LUT 450 for digital image signals of four colors.

  As described above, depending on the operation mode of the image processing apparatus 10, the used area of the shared memory 280 used by the stopped image processing circuit may be used to improve the efficiency (processing performance) of image processing. Another image processing circuit can be used. In some cases, another image processing circuit in operation can be used to improve functions including high image quality.

  Through the processing of the flowchart illustrated in FIG. 6, the use area of the shared memory 280 used by the stopped image processing circuit is allocated to another image processing circuit that is appropriately operating. First, in step S601, the CPU circuit unit 100 determines an image processing operation mode. Next, in step S602, based on the determined image processing operation mode, the CPU circuit unit 100 functions as a processing circuit control unit, and selects an image processing circuit to be used. In step S603, the image processing unit 150 calculates the capacity of a buffer for inputting / outputting digital image data from other related domains from the transfer amounts of the read DMAC 194 and the write DMAC 196. In subsequent step S604, the memory capacity required for each image processing circuit selected by the operation mode is calculated according to the image processing content.

  First, in step S604, it is determined whether or not color space conversion using the color space conversion circuit 240 is performed. If color space conversion is to be performed (“YES” in step S604), the process proceeds to step S605. On the other hand, when color space conversion is not performed ("NO" in step S604), the process proceeds to step S606.

  In step S605, the color space conversion LUT capacity is calculated. Since color space conversion uses a three-dimensional LUT or a four-dimensional LUT, the capacity corresponding to the LUT to be used is calculated. As described above, for example, in the case of 3D-LUT, it is 16K bytes, and in the case of 4D-LUT, it is 256K bytes. Thereafter, the process proceeds to step S606.

  Next, in step S606, it is determined whether or not to perform output γ correction by the output γ correction circuit 250. If output γ correction is to be performed (“YES” in step S606), the process proceeds to step S607. On the other hand, when the output γ correction is not performed (“NO” in step S606), the process proceeds to step S608. In step S607, the capacity of the one-dimensional LUT 450 for the digital image signals of four colors used for output γ correction is calculated.

  In a succeeding step S608, it is determined whether or not the spatial filter processing circuit (1) 220 is used. If the spatial filter processing circuit (1) 220 is used (“YES” in step S608), the process proceeds to step S609. In step S609, the delay memory capacity is calculated, and the process proceeds to step S610. At this time, if necessary, the band height is calculated. Details of the calculation of the band height will be described later in the fourth embodiment. On the other hand, when the spatial filter processing circuit (1) 220 is not used (“NO” in step S608), the process proceeds to step S610.

  In a succeeding step S610, it is determined whether or not the spatial filter processing circuit (2) 230 is used. If the spatial filter processing circuit (2) 230 is used (“YES” in step S610), the process proceeds to step S611. In step S611, the delay memory capacity is calculated. At this time, if necessary, the band height is calculated. On the other hand, when the spatial filter processing circuit (2) 230 is not used (“NO” in step S610), the process proceeds to step S612.

  In the subsequent step S612, allocation of the used area of the shared memory 280 is determined. In the following step S613, it is determined whether or not there is an unused memory. If there is an unused memory (“YES” in step S613), the process proceeds to step S614. On the other hand, when there is no unused memory (“NO” in step S613), the process proceeds to step S615.

  In step S614, the clock supply to the unused memory is stopped, and the process proceeds to step S615. In step S615, in accordance with the determined allocation of the shared memory 280, a predetermined value is set in advance in the conversion table of the shared memory control circuit. In step S616, image processing in the operation mode determined in step S601 is executed.

  Hereinafter, the operation of the shared memory control circuit and the cooperation with the image processing circuit will be described in more detail with reference to FIG.

  The block diagram shown in FIG. 3 shows details of the shared memory control circuit 270. Each of the image processing circuits inputs the above-described memory access method designation signal to the instruction queue 314 via the control port 272 connected to the shared memory control circuit 270.

  The control port 272 has one port 311 for each image processing circuit. The port 311 has an instruction queue 314 and an instruction completion queue 316. A memory access method designation signal for the shared memory 280 from each image processing circuit is written in the instruction queue 314. In addition, a memory control end signal for notifying the end of control to the memory or read (read) data from the shared memory 280 is written in the instruction completion queue 316.

  The memory access arbitration circuit 310 takes out the memory access method designation signal in the instruction queue 314 of the control port input from each of the image processing circuits in accordance with the prioritization and sends it to the conversion table 370.

  The memory access method designation signal includes an ID (tag) for identifying the memory access method and a relative start address (pointer) for specifying the memory access position. The table value of one entry constituting the conversion table 370 is constituted by the start address and capacity (number of words) on the address map of the shared memory, the number of times of memory control to be executed by one instruction, and the memory access method.

  There are five memory access methods in the present embodiment: write (Write), read (Read), write after read (Read & Write), read cache, and write cache. Each of these memory access methods is assigned an ID (tag). A table value for realizing memory access for image processing registered in advance according to the ID (tag) is acquired from the conversion table 370.

  The operation of each memory access method will be briefly described below.

[Write]
When the memory access method of the table value is write (write), write (write) data is written to the shared memory continuously for the number of times of memory control from the addition result of the relative start address (pointer) and the start address.

[Read]
When the memory access method of the table value is read (Read), read (read) data is continuously read from the shared memory by the memory control count from the addition result of the relative start address (pointer) and the start address.

[Write after reading (Read & Write)]
When the memory access method of the table value is write after read (Read & Write), read (read) data is read from the shared memory continuously for the number of times of memory control from the addition result of the relative start address (pointer) and the start address. Thereafter, write data is written to the same address in the shared memory.

[Write cache]
When the memory access method for the table value is a write cache, the relative start address (pointer) is regarded as a cache tag number, and a cache hit / miss hit is determined. If there is a hit, write (write) data is written to the shared memory continuously for the number of times of memory control from the addition result of the relative start address (pointer) and the start address.

  If there is a miss hit, the write DMAC controller 360 controls the write DMAC for data at a predetermined address in the shared memory continuously for the number of times of memory control from the addition result of the relative start address (pointer) and the start address. One end is written into the RAM 106. Thereafter, write data is written to a predetermined address of the shared memory.

[Read cache]
When the table value memory access method is a read cache, the relative start address (pointer) is regarded as a cache tag number, and a cache hit / miss hit is determined. If there is a hit, read (read) data is read from the shared memory continuously from the addition result of the relative start address (pointer) and the start address by the number of times of memory control. If there is a miss, the read DMAC controller 350 controls the read DMAC continuously for the number of times of memory control from the addition result of the relative start address (pointer) and the start address. Then, read (read) data is re-acquired from the RAM 106, and the read (read) data is read simultaneously with writing the (read) data to a predetermined address of the shared memory.

  Control for each memory access method is performed by the control circuit 380. The control circuit 380 includes a cache tag determination circuit that determines a hit / miss hit of the cache, a FIFO pointer circuit, a read circuit (READ), a write circuit (WRITE), and a selector that controls input / output to each circuit ( sel).

  From the control circuit 380, a predetermined address that defines an access destination to the shared memory 280 and the memory control count are sent to the memory control circuit 330. The memory control circuit 330 determines the memory control for the memory (1) to the memory (N) from the predetermined address and the memory control count. The memory control circuit 330 generates a memory control signal and reads / writes data from / to the memory (1) to the memory (N).

  The SRAM controllers 340-1 to 340 -N, the read DMAC controller 350, and the write DMAC controller 360 are each equipped with a sequencer 345 for performing memory control continuously for the number of times of memory control.

  The SRAM controllers 340-1 to 340 -N, the read DMAC controller 350, and the write DMAC controller 360 send a memory control end signal to the read / data acquisition circuit 320 if writing. If it is read, read data or a memory control end signal is sent to the read data acquisition circuit 320. The memory control end signal is input to an instruction completion queue 316 in each control port 272 of the image processing circuit, and each of the image processing circuits obtains a memory control end signal or read (read) data.

  A memory access method in each image processing circuit will be described below.

  The image processing input circuit 210 needs to realize a double buffer configuration, and writes the input digital image data from the read DMAC 194 to the shared memory at any time by designating “Write” as the memory access method. When digital image data stored in the previous buffer is sent to the subsequent image processing circuit, the memory access method is designated as “Read” and the digital image data is read from the shared memory.

  The spatial filter processing circuit (1) 220 and the spatial filter processing circuit (2) 230 control the delay memory. In the case of the delay memory control, the memory access method is designated as “write after read (Read & Write)”, and the shared memory is read and written simultaneously.

  The color space conversion circuit 240 and the output γ correction circuit 250 control the LUT. In the case of LUT control, “Read” is designated as the memory access method, and digital image data is read from the shared memory.

  When the color space conversion circuit 240 reads the read (read) data from the four-dimensional LUT, if all the LUTs cannot be stored in the shared memory, “read cache” is designated as the memory access method. This adds a cache function when referring to the LUT from the shared memory.

  The image processing output circuit 260 needs to realize a double buffer configuration, and writes the output digital image data from the image processing circuit to the shared memory at any time by designating the memory access method as “Write”. When digital image data previously stored in the buffer is sent to the RAM 106 via the DMAC (Write), the output digital image data is read from the shared memory by specifying “Read” as the memory access method.

  The control method for sharing the memory in the multiple image processing circuits has been described above, but the above content is an example. Therefore, the ID (tag) and the relative start address (pointer) of the memory access method designation signal do not necessarily have to be output as described above. Also, the start address and capacity (number of words) on the shared memory address map, the number of times of memory control to be executed by one instruction, and the memory access method, which are table values of one entry constituting the conversion table 370, are not necessarily described above. The circuit configuration may not be as follows. For example, the conversion table 370 may not be mounted, and all the information for performing the memory control may be included in the memory access method designation signal.

[Second Embodiment]
In the first embodiment, the memory access method is defined by general memory control requirements, and the image processing circuit combines them to realize reading and writing to the shared memory.

  Specifically, the image processing input circuit 210 combines two memory access methods, [Write (Write)] and [Read (Read)]. Actually, there are four memory access methods ([Write (Write)] and [Read (Read)] to the input buffer [A] 410), [Write (Write)] to the input buffer [B] 412 and the conversion table. [Read (Read)]) is registered. In addition, the image processing input circuit 210 selects two of the four conversion table values to realize a double buffer.

  On the other hand, in the second embodiment, the memory access method is defined by requirements specific to the image processing circuit. That is, the double buffer mode is defined as the memory access method for the image processing input circuit 210 described above. Then, the input buffer [A] 410 and the input buffer [B] 412 are automatically switched on the shared memory control circuit side by specifying the relative start address (pointer) of the memory access method specifying signal.

  For the memory access method of the spatial filter processing circuits (1) 220 and (2) 230, the above-mentioned [Write after Read (Read & Write)] is defined as a delay buffer (FIFO) mode. At this time, the length of the ring FIFO may be registered in the conversion table in addition to the delay buffer capacity. For the memory access method of the color space conversion circuit 240 and the output γ correction circuit 250, the above-mentioned “Read” is defined as a lookup table mode. At this time, instead of continuously reading out how to read the LUT from the predetermined address of the shared memory in the conversion table, the shared memory control means that the vertices necessary for tetrahedral interpolation described in JP 2007-67956 A are read continuously. It may be a mounting method automatically performed on the circuit side.

  Further, an implementation method may be used in which the ID (tag) of the memory access method designation signal does not indicate the entry number of the conversion table as in the first embodiment, but is a unique number indicating the image processing content.

[Third Embodiment]
FIG. 5 is a diagram illustrating an example of a circuit configuration of the image processing unit and an example of an address map of the shared memory in a state where the clock of the unused memory can be stopped according to the present embodiment. In the circuit configuration of FIG. 5, the shared memory is composed of four memories of the same capacity (1) 280-1, memory (2) 280-2, memory (3) 280-3, and memory (4) 280-4. It is configured. As shown in FIG. 5, it is assumed that the same capacity is allocated in the order of the memory (1), the memory (2), the memory (3), and the memory (4).

  As shown in the circuit configuration of FIG. 5, only the image processing input circuit 210, the spatial filter processing circuit (1) 220, and the image processing output circuit 260 depend on the operation mode among all the image processing circuits of the image processing apparatus 10. Suppose it is working and the others are stopped. At this time, the designated area of the shared memory 280 is allocated so as to fit within the area of the memory (1) 280-1 constituting the shared memory as shown in the memory map of FIG. Alternatively, the allocation is adjusted so that there is a memory to which the area is not allocated, by collecting as much as possible so that the used area is not distributed among a plurality of memories.

  As a result, in the case of FIG. 5, the memories (2) 280-2 to (4) 280-4 are not used and are not used for image processing. Then, an excessive memory clock can be stopped to reduce the power consumption of the image processing circuit. Even in other cases, the power consumption can be reduced by stopping the clock for the memory to which no area is allocated.

  When each of the image processing circuits is connected to a dedicated memory, it is possible to suppress power consumption by stopping the clocks for the unused image processing circuit and the dedicated memory depending on the operation mode. On the other hand, in the present invention, the power consumption can be suppressed by operating the designated area of the shared memory according to the operation mode.

[Fourth Embodiment]
As described in JP-A-2006-139606, the delay memory capacity required for a spatial filter processing circuit for local (neighboring) image processing such as edge enhancement processing and blurring processing can be reduced. For example, it is assumed that local image processing such as edge enhancement processing and blurring processing is performed on the digital image data 700 of FIG. At this time, the digital image data is divided for each region, and local image processing is performed for each separate region. In general, in such a technique, as shown in FIGS. 7A to 7D, the entire digital image data is divided into strips (strips), and various image processing is sequentially performed for each region. Done.

  This elongated and divided area is called a band area, a storage area where the band area is expanded is called a band memory, and an action of dividing an image is called a band division. The band memory is not necessarily reserved as a storage area in the main memory, and may be allocated in any storage area on the system. However, for the sake of brevity, the band memory is used as the main memory. An example of securing in the memory will be described.

  In addition, as shown in FIG. 7E, the digital image data coordinate system (main scanning direction-sub-scanning direction) defines a new coordinate system (band region coordinate system) of the length direction and the height direction. The band region is expressed by length × height. The band area is set so that either the length or the height always has the value of the width of the digital image data in the main scanning direction or the height of the sub scanning direction. For example, when the length of the band area is matched with the width of the digital image data in the main scanning direction, the height of the band is an arbitrary value. On the other hand, when the height of the band area is matched with the height of the digital image data in the sub-scanning direction, the length of the band is an arbitrary value.

  The band processing will be described in detail. First, the first band area 701 shown in FIG. 7A is developed in a band memory on the main memory to perform image processing. Next, the second band area 702 shown in FIG. 7B is overwritten on the band memory in which the first band area 701 is expanded to perform image processing. Further, the third band area 703 shown in FIG. 7C is overwritten on the band memory in which the second band area 702 is expanded to perform image processing. Finally, the fourth band area 704 shown in FIG. 7 (d) is overwritten on the band memory where the third band area 703 is expanded, and image processing is performed.

  As is clear from FIGS. 7A to 7D, the band regions 701 to 704 have the same length, but the heights need not be the same. In FIG. 7, the band regions 701 to 703 have the same height, and the band region 704 has a lower height. Therefore, the height of the band memory, which is a storage area secured in the main memory, depends on the band area having the largest size in the height direction (in the case of FIG. 7, the first to third band areas 701 to 703). It is determined.

  In such a technique, in order to perform local image processing without a gap between the band regions, each band region is devised so that a part thereof overlaps each other at a boundary with an adjacent region. In Japanese Patent Laid-Open No. 2006-139606, the capacity of a delay memory that scans pixels one by one in the same direction as the height of each band area and holds processing pixels necessary for local image processing is set to the height of each band area. It is specified by the size of. Thereby, the memory saving of the delay memory is realized.

  In general, in order to perform the local image processing described as an example, a delay memory having a capacity that is an integer number of the number of pixels in the horizontal width of the paper (the number of taps of the spatial filter process-1) is required. In such a technique, the delay memory capacity is determined by the size of the paper and cannot be changed. However, in Japanese Patent Laid-Open No. 2006-139606, the delay memory capacity is an integral number of divided band heights (number of taps of spatial filter processing-1) times, but an arbitrary band height can be designated according to the number of band divisions. Therefore, the delay memory capacity can be changed.

  In this embodiment, the feature that the delay memory capacity can be changed is used. That is, the band height is calculated by the following equation 1 according to the free capacity of the shared memory (delay memory capacity that can be secured on the shared memory) and the number of taps of the spatial filter processing.

Band height = delay memory capacity that can be secured on shared memory / (number of taps -1) / (data amount of one pixel) (Equation 1)
According to the present invention, even when a part of the image processing circuit of the image processing apparatus 10 does not operate, the image processing circuit in operation can always use the memory, and the memory mounted for image processing can be effectively used. The memory activation rate of the entire LSI can be improved. In addition, since it is not necessary for each image processing circuit to share the connection destination memory, the memory control method is easy for each image processing circuit, and the design of each image processing circuit is also easy.

  Conventionally, the dedicated memory attached to each image processing circuit has various sizes and is unevenly distributed according to each processing content. On the other hand, according to the present invention, a certain amount of memory (in many cases, the same capacity is desirable) is integrated and configured as one virtual shared memory, so that circuit layout and wiring at the time of LSI development is easy. Become.

  Furthermore, since it is sufficient that the capacity of the shared memory is larger than the total amount of memory of the image processing circuit that operates by specifying the operation mode among the plurality of image processing circuits, the total amount of all memories of the plurality of image processing circuits in the LSI as in the past. There is no need to implement it. Therefore, the circuit scale of the memory mounted as a total is reduced.

  Further, in the method of performing image processing sequentially by dividing the band, the capacity of the delay memory used for local image processing such as a spatial filter circuit depends on the number of taps of the spatial filter and the band height. In such image processing, the number of redundantly retransmitted pixels varies depending on the ratio of the number of taps of the spatial filter to the band height, and the larger the band height, the better the image processing efficiency. More flexible image processing can be realized by combining the shared memory of the present invention and image processing sequentially by dividing the band. Specifically, when there are a large number of image processing circuits that focus on functions and operate in the operation mode, the free capacity of the shared memory naturally becomes small. At this time, an executable band height is calculated from the free area of the shared memory and the number of taps of the spatial filter, and sequential image processing is performed for each predetermined band height although efficiency is reduced. On the other hand, when there are very few image processing circuits that operate in the operation mode, naturally the free capacity of the shared memory also increases, and efficient image processing can be performed by setting a band height as large as possible. That is, it is possible to adjust the band height according to the free area of the shared memory, trade off the function and efficiency of image processing, and realize flexible image processing.

  In each of the above embodiments, the present invention has been described as an image processing apparatus having a plurality of image processing circuits. However, embodiments of the invention are not limited to image processing apparatuses. That is, in an information processing apparatus including a plurality of processing circuits, the present invention is provided to solve the problem that a dedicated memory attached to a processing circuit that is temporarily stopped depending on the operation mode cannot be used by other processing circuits that are operating. can do. In such an information processing apparatus, by sharing the dedicated memories of a plurality of processing circuits with each other, even when some of the processing circuits do not operate, an area for the circuit is allocated to other operating processing circuits. be able to.

[Other Embodiments]
Note that the present invention can be applied to a system including a plurality of devices (for example, a host computer, an interface device, a reader, and a printer), and a device (for example, a copying machine and a facsimile device) including a single device. You may apply to.

  The object of the present invention can also be achieved by supplying, to a system, a storage medium that records the code of a computer program that realizes the functions described above, and the system reads and executes the code of the computer program. In this case, the computer program code itself read from the storage medium realizes the functions of the above-described embodiments, and the storage medium storing the computer program code constitutes the present invention. In addition, the operating system (OS) running on the computer performs part or all of the actual processing based on the code instruction of the program, and the above-described functions are realized by the processing. .

  Furthermore, you may implement | achieve with the following forms. That is, the computer program code read from the storage medium is written into a memory provided in a function expansion card inserted into the computer or a function expansion unit connected to the computer. Then, based on the instruction of the code of the computer program, the above-described functions are realized by the CPU or the like provided in the function expansion card or function expansion unit performing part or all of the actual processing.

  When the present invention is applied to the above storage medium, the computer program code corresponding to the flowchart described above is stored in the storage medium.

Claims (6)

A plurality of image processing circuits for processing image data;
A shared memory shared by the plurality of image processing circuits;
A memory control circuit that allocates an input buffer of the image processing circuit, an output buffer of the image processing circuit, and a reference data storage area of the image processing circuit to the shared memory;
An image processing apparatus comprising:   The image processing apparatus according to claim 1, wherein the reference data is a cache used by an image processing circuit.   The image processing apparatus according to claim 1, wherein the reference data is a look-up table used by an image processing circuit.   2. The memory control circuit according to claim 1, wherein the type of reference data stored in the reference data storage area allocated to the shared memory varies depending on an image processing circuit used in an image processing mode of the image processing apparatus. The image processing apparatus described. A plurality of image processing circuits for processing image data;
A shared memory shared by the plurality of image processing circuits;
An image processing apparatus control method comprising:
A control method for an image processing apparatus, comprising: a memory control step for allocating an input buffer of the image processing circuit, an output buffer of the image processing circuit, and a reference data storage area of the image processing circuit to the shared memory. Computer
A plurality of processing means;
A program for causing a shared memory shared by the plurality of processing means to function as a memory control means for allocating an input buffer of the image processing circuit, an output buffer of the image processing circuit, and a reference data storage area of the image processing circuit.

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