JPS61262342A - Communication control equipment - Google Patents

Abstract

PURPOSE:To realize a communication controller with high performance and less hardware quantity by providing a transmission buffer and a reception buffer in a line adaptor and changing over the mode so as not to use a buffer circuit in case of the basic procedure and so as to use it in case of the HDLC procedure. CONSTITUTION:A transmission buffer circuit 4 and a reception buffer circuit 5 are providing between a serial/parallel converting circuit 1 and a communication control basic section in a line adaptor and the communication control basic section gives an indication to change over the mode using the transmission buffer circuit and the reception buffer circuit and the mode not using them. The communication control basic section transfers a data in plural bytes to one processing request from the line adaptor in the operating mode and transfers a data in 1 type to one processing request in the mode not using them. For example, the communication controller does not use the transmission buffer circuit and the reception buffer circuit in case of the basic procedure and uses the buffer circuits in case of the HDLC procedure.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a communication control device. In particular, basic procedures and high-level data link transmission control procedures (rH
This invention relates to a communication control device that supports both DLC procedures (DLC procedures).

〔overview〕

The present invention provides a communication control device that controls data transmission and reception between a central processing unit and a communication line using both the basic procedure and the HDLC procedure. By switching the mode so that these buffer circuits are not used in the case of HDLC procedures and are used in the case of HDLC procedures, a high-performance communication control device can be realized with a small amount of hardware.

[Conventional technology]

Conventional communication control devices include a line adapter that connects communication lines and performs serial/parallel conversion of transmitted and received data, and a line adapter that connects multiple line adapters to control various transmission control procedures and interface control with a central processing unit. It consists of a basic communication control unit that performs the following operations. The communication control basic unit scans a plurality of line adapters one by one, detects processing requests from the line adapters, and executes processing corresponding to the requests.

[Problem to be Solved by the Invention 1] The conventional communication control device described above is designed to transfer 1 byte of data in response to a single processing request from a line adapter. Therefore, when connecting a high-speed line, it is necessary to shorten the processing time in the communication control basic unit for one processing request from the line adapter, which increases the amount of hardware in the communication control basic unit. There was a drawback.

This drawback can be solved by providing a buffer circuit on the line adapter side. However, when controlling basic procedures, it is necessary to control each byte for detecting control characters, etc., and if a buffer circuit is provided on the line adapter side, the control of this buffer circuit becomes complicated. .

[Means for solving problems]

The communication control device of the present invention includes one or more line adapters, each connected to a communication line, and a communication control basic unit that is connected to the line adapters and controls transmission control procedures and interfaces with a central processing unit. In a communication control device, the line adapter includes a serial-to-parallel conversion circuit that performs serial-to-parallel conversion of data transmitted and received over a communication line, and the line adapter includes the serial-to-parallel conversion circuit and the communication control basic unit. a transmitting buffer circuit and a receiving buffer circuit are provided between the transmitting buffer circuit and the receiving buffer circuit, and means for switching between a mode in which the transmitting buffer circuit and the receiving buffer circuit are used and a mode in which the transmitting buffer circuit and the receiving buffer circuit are not used according to an instruction from the communication control basic unit; The basic part transfers multiple bytes of data in response to a single processing request from the line adapter in the mode used above, and 1 byte in response to a single processing request from the line adapter in the mode not used. The invention is characterized in that it includes a control means for transferring data.

[For production]

The communication control device of the present invention does not use a transmission buffer circuit and a reception buffer circuit in the case of a basic procedure, and
These buffer circuits are used in the case of the DLC procedure. Therefore, the basic procedure can be transmitted and received without performing complicated buffer control within the line adapter, and the HDLC procedure can be transmitted and received with simple control.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a communication control device according to an embodiment of the present invention.

The communication control basic unit 201 is connected to the central processing unit via a signal line 250, and to line adapters 300-1 to 300-n via signal lines 30 to 32, 34 to 37.

The communication control basic unit 201 controls HDCL procedures and basic procedures, and controls the interface with the central processing unit. Line adapters 300-1 to 300-n and signal lines 30 to 32 and 34 to 37 will be described below.

FIG. 2 is a block diagram of the line adapter used in this embodiment.

The serial-to-parallel conversion circuit 1 is connected to a line via signal lines 80, 81, to the buffer control circuit 3 and the selector 10 via a signal line 51, to the selector 13 via a signal line 52, and is connected to a signal line 80. ! It is connected to the selector 14 via the signal line 53, and to the buffer control circuit 3, the selector 11, the reception buffer circuit 5, and the selector 12 via the signal line 50.

Line adapter 2 includes signal line 106 and path receiver 2
0 to the signal line 30, connected to the signal line 31 via the signal line 107 and the path receiver 21, connected to the buffer control circuit 3 via the signal line 71, and connected to the selector 13 via the signal line 72. and to the selector 14 via a signal line 73.

The buffer control circuit 3 is connected to the selector 1 via a signal line 62.
3, connected to the selector 14 via the signal line 63, connected to the receive buffer circuit 5 via the signal lines 66.67, connected to the transmit buffer circuit 4 via the signal lines 64.65, and connected to the selector 14 via the signal line 63. It is connected to the selector 10 via the line 61 and to the signal line 37 via the signal line 100 and the path driver 27.

The transmission buffer circuit 4 is connected to a signal line 32 via a signal line 101 and a path receiver 23, connected to a selector 11 via a signal line 102, and connected to a signal line 34 via a signal line 103 and a path receiver 24. be done.

The reception buffer circuit 5 is connected to the signal line 35 via the signal line 104 and the bus driver 25, and is connected to the selector 12 via the signal line 105.

The selector 11 connects the path receiver 2 via the signal line 101.
Connected to 3. The selector 12 is connected to the signal m32 via the bus driver 22.

The serial-parallel modulation circuit 1 is a circuit that converts serial data on the line and parallel (8-bit) data inside the line adapter, and is generally a U RT (Universal Re
It is realized using an LSI called ``civer and trans+5itter''.

The line adapter control circuit 2 is a circuit that controls the entire line adapter, and the line adapter address (
When the LA address (hereinafter referred to as rLALA address) and the LA address sent from the communication control basic unit match, a control operation for the own line adapter is performed. The buffer control circuit 3 is a circuit that controls the transmission buffer circuit 4 and the reception buffer circuit 5.

The transmission buffer circuit 4 stores transmission data and control information for the serial-parallel modulation circuit 1. The capacity of the transmission buffer is 64 words x 9 bits (8 bits of data + 1 bit of data/control identification), and is referred to as first-in, first-out memory (referred to below as r).
F I F O (First In First Ou
t) consists of ``memory'').

The reception buffer circuit 5 stores received data and control information sent from the serial/parallel conversion circuit l.

The capacity of the receive buffer is 64 words x 9 bits (8 bits of data + 1 bit for each data/system 111m).
It is FIFO memory.

The selector 10 is a switching circuit that switches between the interrupt signal from the serial/parallel conversion circuit 1 and the interrupt signal from the buffer control circuit 3, and selects the signal from the buffer control circuit 3 for the buffer use mode. The selector 11 is a switching circuit that switches between the data sent from the communication control basic unit 201 and the output data of the transmission buffer circuit 4, and selects the output of the transmission buffer circuit 4 for the buffer use mode.

The selector 12 is a switching circuit that switches between the line adapter internal data bus and the output of the reception buffer circuit 5, and selects the output of the reception buffer circuit 5 in the buffer use mode.

The selector 13 switches between the output of the buffer control circuit 3C and the output of the line adapter control circuit 2, and generates an address specifying the internal register of the serial/parallel conversion circuit l. For the buffer use mode, the output of the buffer control circuit 3 is selected. The selector 14 switches between the output of the buffer control circuit 3 and the output of the line adapter control circuit 2, and generates control signals (read signal R[!AD, write signal WRITII!, etc.) for the serial/parallel conversion circuit 1. For the buffer use mode, the output of the buffer control circuit 3 is selected.

The bus driver 22.25.26.27 is enabled only when its own line adapter is selected by the LA address.

Signal line 30 carries a signal indicating the LA address and internal address information of the line adapter, and signal line 106 carries the path receiver output signal of signal line 30. The signal line 31 transmits control signals for the line adapter (read signal RBAD, write signal -RITE, etc.), and the signal line 107 transmits the path receiver output signal of the signal line 30.

The signal line 32 is an 8-bit bidirectional data bus signal DAT.
A, and signal line 101 carries the path receiver output signal of signal line 32.

The signal line 35 transmits a signal that identifies whether the data sent from the reception buffer circuit 5 to the communication control basic unit 201 is reception data or control information. The signal line 104 is connected to the signal line 35
bus driver input signals.

The signal line 34 transmits a signal that identifies whether the data sent from the communication control basic unit 201 to the transmission buffer circuit 4 is transmission data or control information. Signal fi103 is signal line 3
4 pass receiver output signals.

The signal line 36 transmits an interrupt signal INT to be sent to the communication control basic section 201.

The signal line 37 transmits an end signal END for terminating data transfer to the communication control basic unit 201, and a signal *ioo
is a signal'! s37 bus driver input signal is transmitted.

The signal line 50 is a bidirectional data bus (
8 bits) and is connected to the serial/parallel converter circuit 1, the buffer control circuit 3, the selector 11, the reception buffer circuit 5, and the selector 12. The signal line 51 is connected to the serial/parallel conversion circuit 1
transmits the interrupt signal output from the

The signal line 52 transmits address information specifying a register inside the serial-to-parallel conversion circuit 1. The signal line 53 transmits control signals (read signal READ, write signal wmE, etc.) to the serial/parallel conversion circuit 1.

The signal m62 transmits the address information output by the buffer control circuit 3 and specifies the internal register of the serial/parallel conversion circuit 1. The signal M72 transmits the address information output by the line adapter control circuit 2, and specifies the internal register of the serial/parallel conversion circuit l. The signal line 63 transmits a control signal output from the buffer control circuit 3 to the serial/parallel conversion circuit 1 .

The signal [73 conveys a similar control signal output by the line adapter control circuit 2.

The signal line 64 carries a control signal (
(read signal READ, write signal WRITE, etc.). The signal line 66 carries control signals (read signal READ, write signal WRITIE, etc.) for the reception buffer circuit 5.
Communicate. The signal line 65 transmits a control signal indicating the state of the transmission buffer circuit 4 (buffer empty, buffer full, control information available, etc.). A signal line 67 carries a control signal indicating the state of the reception buffing circuit 5 (buffer empty, buffer full, etc.).
Communicate.

The signal line 71 transmits a signal to set the buffer to either a mode in which the buffer is used or a mode in which it is not used. This signal is output by terminating the address information inside the line adapter sent from the communication control basic unit 201.

Signal line 80 transmits transmission data TXD to the line, and signal line 81 transmits reception data RXD from the line.

FIG. 3 is a time chart of the transmission operation in the mode using the buffer circuit. Transmission operation in this mode is performed as follows.

The LA address of the signal line 30 is set by adding "1" to the address value of each line adapter because the communication control basic unit 201 scans the line adapters 300-1 to 300-n one by one. Different values are set for this value on the sending and receiving sides. If the interrupt signal INT of signal -36 is not set from the corresponding line adapter, the communication control basic unit 201 will:
No processing is performed on the corresponding line adapter, and the process moves to the next address. When a certain amount of buffer space is detected in the transmission buffer circuit 4 and an interrupt signal INT is input, the communication control basic unit 201 outputs transmission data on the signal line 32 and outputs a write signal WRITE on the signal line 31. By doing so, the transmission data is written to the transmission buffer circuit 4. This transfer operation ends when the line adapter detects the state of the buffer or the writing of control information to the transmission buffer circuit 4, and sets the end signal END to the signal line 27.

Transfer of transmission data from the transmission buffer circuit 4 to the serial/parallel conversion circuit l is performed by the buffer control circuit 3
The interrupt signal from the transmission buffer circuit 4 and the control signal from the transmission buffer circuit 4 are monitored, and control is performed in the same manner as the communication control basic unit 201 in the mode in which no buffer is used. When the transmission data is written, the serial/parallel conversion circuit 1 converts it into serial data according to a preset line speed, and sends the transmission data TXD onto the line.

FIG. 4 is a reception operation time chart in a mode using a buffer circuit. The reception operation in this mode is performed as follows.

The serial/parallel conversion circuit 1 converts the received data RXD from the line into parallel data. From the serial/parallel converter circuit 1 to the receiving bar τ・
To transfer the received data to the buffer circuit 5, the buffer 1 control circuit 3 monitors the interrupt signal from the serial-to-parallel converter circuit 1 and the control signal from the reception buffer circuit 4. The control is performed in the same manner as in 201. When a certain amount of received data is written to the reception buffer circuit 5 and an interrupt signal INT is set on the signal line 36 from the line adapter specified by the LA address, the communication control basic unit 201 outputs the read signal REA.
D to the signal line 31. The line adapter sends the received data stored in the receive buffer circuit 5 to the signal line 32 in response to the read signal READ.

This transfer operation ends when the line adapter detects the state of the buffer circuit or the reading of control data from the reception buffer circuit 4 and sets an end signal END on the signal line 27.

FIG. 5 is a time chart of a transmission operation in a mode that does not use a buffer circuit. Transmission operation in this mode is performed as follows.

The interrupt signal of the serial-to-parallel conversion circuit 1 is outputted to the signal line 36 as is. When the interrupt signal INT is set to the signal line 36 from the line adapter specified by the LA address, the communication control basic unit 201 sets the read signal READ and the address information in the line adapter to interrupt the serial/parallel conversion circuit 1. Reads the status register located in the register and determines the cause of the interrupt (transmission interrupt/reception side interrupt, etc.). If there is a transmission interrupt, then the transmission interrupt register in the serial/parallel conversion circuit 1 is read using the same means, and the cause of the transmission interrupt (transmission request/underrun, etc.) is determined.

If there is a transmission request, output the transmission data to the signal line 32,
By outputting a write signal to signal m31, the transmission data is directly written into the transmission data register in the serial/parallel conversion circuit 1.

FIG. 6 is a time chart of a receiving operation in a mode that does not use a buffer circuit. The reception operation in this mode is performed as follows.

Signal from the line adapter specified by LA address! When the interrupt signal INT is sent to s36, the communication control basic unit 20
1 reads the status register. If there is a reception interrupt, then the reception interrupt register is read using the same means to determine the cause of the reception interrupt (reception request/end of reception, etc.). If there is a reception request, the reception data register in the serial/parallel conversion circuit 1 is read out using the same means, and the reception data is sent to the communication control basic unit 201.

The difference in control between the mode using the buffer circuit and the mode not using the buffer circuit is whether the serial-to-parallel conversion circuit 1 is controlled by the buffer control circuit 3 or directly by the communication control basic unit 201.

The block configuration diagram of the line adapter shown in FIG. 2 only shows features of the present invention, and there are actually circuits and connections that are not shown. Further, in FIG. 2, the number of circuits per line adapter is one, but the present invention can be implemented in the same way even if the number of circuits is plural.

〔Effect of the invention〕

As explained above, in the case of HDLC procedure control that performs frame-by-frame control, the communication control device of the present invention controls the hardware amount of the communication control basic section by controlling the line adapter in a mode that uses a buffer. It is possible to improve performance such as high speed without increasing the speed. In addition, in the case of the basic procedure that controls each character, by controlling the line adapter in a mode that does not use a buffer, there is no need to complicate buffer control within the line adapter, and the configuration of the buffer circuit is simplified. Become.

Generally, communication control devices are HDLC, which requires high speed.
Often supports both procedures and basic procedures used at low or medium speeds.

The present invention has the effect of making it possible to mix control procedures and realizing a high-performance communication control device with a smaller amount of hardware.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a communication control device according to an embodiment of the present invention. FIG. 2 is a block diagram of a line adapter used in this embodiment. FIG. 3 is a time chart of a transmission operation in a mode using a buffer circuit. FIG. 4 is a time chart of reception operation in a mode using a buffer circuit. FIG. 5 is a time chart of transmission operation in a mode that does not use a buffer circuit. FIG. 6 is a time chart of reception operation in a mode that does not use a buffer circuit. DESCRIPTION OF SYMBOLS 1... Serial/parallel conversion circuit, 2... Line adapter control circuit, 3... Buffer control circuit, 4... Transmission buffer circuit, 5... Receiving buffer circuit, 10-14... Selector, 22.25.26.27...bus driver,
20.21.23.24...Pass receiver, 201.
...Communication control basic unit, 300-1 to 300-n...Line adapter.

Claims (1)

[Claims] (1) comprising one or more line adapters, each connected to a communication line, and a communication control basic unit connected to the line adapters and controlling transmission control procedures and interface control with a central processing unit; In a communication control device, the line adapter includes a serial-to-parallel conversion circuit that performs serial-to-parallel conversion of data transmitted and received over a communication line; a buffer circuit and a reception buffer circuit, and means for switching between a mode in which the transmission buffer circuit and reception buffer circuit are used and a mode in which the transmission buffer circuit and reception buffer circuit are not used according to an instruction from the communication control basic unit, the communication control basic unit: In the mode used above, multiple bytes of data are transferred in response to a single processing request from the line adapter, and in the mode not used above, 1 byte of data is transferred in response to a single processing request from the line adapter. 1. A communication control device characterized by comprising a control means for controlling.