JPH01201751A - Memory protecting device - Google Patents

Abstract

PURPOSE:To lighten the burden of a hardware by providing the banks of register files corresponding to plural tasks and setting the upper limit and the lower limit of the address of a memory space used for the banks and a memory space used in common for the banks. CONSTITUTION:The title device is provided with registers 1a and 1b to set an upper limit BCLMTH and an lower limit BCLMTL of the address of the memory space common to the plural banks and is provided with registers 2a and 2b to set an upper limit BnLMTL and a lower limit BnLMTL of the memory space used by each bank. An address from a microprocessor 1, etc., is compared with the contents of the registers 1a and 1b by a comparator 4a and is compared with the contents of the registers 2a and 2b by a comparator 4b and the outputs of the comparators 4a and 4b are passed through AND circuits 5 and 5 and outputted from an OR circuit as a memory access permission signal.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention is a multi-task execution system in which a microprocessor or the like has a plurality of register file banks, and each bank is used in a multi-task execution system in which a plurality of tasks can be processed in parallel by time division, etc. By setting the upper and lower limits of the address of the memory space (work area, etc.) that can be used, and the upper and lower limits of the address of the memory space that can be shared by each bank, the memory space of the bank other than the one currently being executed is destroyed. The present invention relates to a memory protection device that prevents this from occurring.

2. Description of the Related Art In a mile task system in which a plurality of tasks are processed in parallel in a time-sharing manner, a large number of tasks including an operating system (hereinafter abbreviated as O8) will exist simultaneously in memory. In such a situation, O8 must manage the execution of each task. Also, there must be no illegal access from one task to another task. For example, if a user program illegally
It must never be allowed to infiltrate O8 and confuse it or rewrite data of other tasks.
If this happens, there is a possibility that the program will run out of control and the system may crash. In other words, it is necessary to protect each logical address occupied by each task by specifying that it can be executed/read/written only in OS mode, or that the user can only execute it.

Until recently, the execution of this protection was entirely left to the management of the O8, and the O8 had to update and check the protection content each time the task was switched. Therefore, when a malfunction such as a programming error or a hard error occurs in the O3 itself, the contents of the memory are often destroyed and the system goes down.

Therefore, at present, a memory management unit (hereinafter abbreviated as MMU) is often used in combination to protect the memory.

It is convenient to configure programs and data modules as independent segments and program them using logical addresses. When these segments are stored in the main memory and referenced, a physical address determined by the hardware must be given to the main memory. This diagram is shown in FIG.

When executing a program programmed with logical addresses, the processor will, of course, output logical addresses, so hardware must be placed between the processor and main memory to convert logical addresses to physical addresses. This is called MMU.

Now, in order to convert a logical address into a physical address, the MMU stores a segment base address for each segment (a logical address is expressed by a segment number and an offset, and a physical address corresponds to the segment number. Using the segment base address, it is determined by the formula: physical address = segment base address + offset.

At this time, for each segment, segment base
In addition to the address, specify the segment size and segment attributes. First, if the offset value exceeds the segment size, it is considered a violation. This is because there is a risk of destroying other adjacent segments. In addition, there are various possible segment attributes, but mainly there are distinctions between O8 and user areas, and areas where only reading is permitted.

A group of status signals are output from the processor every bus cycle. It also outputs a control signal that specifies whether a bus cycle is a read cycle or a write cycle.The MMU compares these signals with the attributes of the segment for each memory reference. When the MMU detects a violation of the segment violation, it sends a segment violation signal to the processor. When a processor receives a violation signal, it interrupts instruction execution and performs exception handling. This protects memory.

Problems to be Solved by the Invention However, in the conventional method described above, the segment base address, segment size, and segment attributes are expanded for each segment (memory space must be prepared separately from main memory). This was a big burden on the hardware.

Means for Solving the Problems The present invention solves the above-mentioned conventional problems. It has a plurality of banks of register files corresponding to a plurality of tasks, and sets the upper and lower limits of the address of the memory space used for each bank. Memory protection is achieved by setting upper and lower limits of addresses in the memory space used for bank sharing, and determining whether the output address is within the memory space range.

This makes the burden on the hardware relatively light.
Moreover, detailed protection can be applied to the memory space.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration block diagram of memory protection in an embodiment of the present invention.

In this figure, 1a and 1b are registers for setting the upper limit Bo, LMTH and lower limit B, LMTL of the address of the bank-shared memory space (work area, etc.), and 2a, 2
b is the upper limit B of memory space used for each bank. , L.M.
There are as many registers as there are banks for setting TH and lower limits B, LMTL, and 3a and 3b are multiplexers (MP
X), 4a, 4b are comparators, 5 is an AND circuit, 6 is O
This is an R circuit.

Figure 2 shows that in a multitask execution system with multiple banks, task A is currently being executed in bank 1, task B and D are being executed in bank 2, task C is being executed in bank 3, and task C is being executed in bank 2. 3 is a map diagram of the memory space when task B suspends task D. FIG. Here, when bank 2 is in the -RUN- state, the memory space available for bank 2 is the area shown by diagonal lines.

That is, the upper limit B, LMTH and lower limit B, LMTL of the address of the memory space used for bank sharing and the current RU
Upper limit B of addresses in memory space used by banks in the N-state. , LMTH and lower limits Bo and LMTL are set in advance, and the memory is protected by allowing memory access only within these ranges.

Therefore, in FIG. 1, when an address is output to the memory from a microprocessor or the like, a comparator 4a is used to determine whether the address is in the memory space used for bank sharing. -+- and B c , L M T
Compare L −+ b with the address output from a microprocessor or the like.

If the address is below Bo, LMTH, then B,,L
If it is more than MTL, Bc, E N through AND circuit 5
A B L E is output.

In addition, in order to determine whether the bank in the -RUN'' state is within the range of the memory space to be used, bank 2
is running, then B+1. L M T H-
B 2 , LM using M P X-3a from za
Take out T H, and in the same way, Bn, LMTL-2b
From B2. The LMTL is extracted and this value is compared with the address output from a microprocessor or the like. Similarly to the above, if the address is 82, L M T H or less, B
t, L M T L or more, Bn, ENABL
E is output.

And B,, E N A B L E and Bn, EN
The OR circuit 6 obtains the logical sum of ABLE and uses this as a memory access permission signal. This is nothing special; if this is output, it indicates that data is being read or written from the currently accessible memory space.

If we consider protecting only memory writes, the memory protection configuration block will be as shown in FIG. Here, 7 is an inverter, 8 is an AND circuit, and 9 is a memory protection configuration block shown in FIG.

With this configuration, when an address is output from a microprocessor or the like, the memory access permission block 9 determines whether it is an accessible memory, that is, a work area, and if it is within the work area and writing, a write signal WE is sent. A logical product with a memory access permission signal is taken, and this can be used as a memory write signal. Furthermore, if it is outside the work area and it is a write, the write signal WE is ANDed with the inversion of the memory access permission signal, and this can be used as an exception interrupt for a microprocessor or the like.

Effects of the Invention As described above, the present invention provides memory space ( It has a group of registers that set the upper and lower limits of the addresses of the work area, etc.) and the upper and lower limits of the addresses of the memory space that can be shared by each bank, and compares these with the addresses output from the microprocessor, etc. This achieves memory protection.

This reduces the burden on hardware compared to when a memory management unit (MMU) is used, and allows fine-grained protection of the memory space.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the configuration of a memory protection device according to the first embodiment of the present invention, FIG. 2 is a map of the memory space, FIG. 3 is a block diagram of the configuration when memory protection is performed only during writing, and FIG. The figure is a memory management diagram in a conventional example. la, lb...Registers for setting the upper and lower limits of the shared work area, 2a, 2b...Registers for setting the upper and lower limits of the work area for each bank, 3
a, 3b...Multiplexer, 4a, 4b...
... Comparator, 5, 8 ... AND circuit, 6.
...OR circuit, 7...Inverter, 9
...Memory access permission block. Name of agent Patent attorney Toshio Nakao 1 person Figure 1 Figure 2 Memory view Rezuzuta group Kuzuta group Figure 3 Figure 4 (Program) Mutator is also Neil) (1 Memory logic Adshimata and Akari address

Claims (1)

[Claims] One microprocessor and multiple banks of register files corresponding to multiple tasks, and a first register that sets the upper and lower limits of addresses of the memory space (work area, etc.) used for each bank in the register file. Multiplexer that selects the registers of the register group and the bank that is being executed. A comparator that determines whether the address output when the program is executed is within the memory space used by the bank that is being executed. Upper limit of addresses in the memory space used in bank sharing. and a second group of registers that set the lower limit, and a comparator that determines whether the output address is within the memory space range used for bank sharing.As a result of the determination by these comparators,
If the output address is a memory space that can be used in the bank that is being executed, or if it is a memory space that can be shared by a bank, it outputs a memory access permission signal and writes the permission signal to the memory, or A memory protection device characterized by a read control signal.