JPS6011934A - Display device for action mode - Google Patents

Abstract

PURPOSE:To display an action mode even with a system which contains no action mode display function by providing a control part which stores the action mode value in a mode register and another control part which resets a shunted action mode value to the mode register. CONSTITUTION:A program P1 which is under execution in a mode M1 calls out a program M2 which can be executed in a mode M2. Then an arithmetic processor 1 delivers the execution start address of the P2 to an address bus 13 as well as to a fetch signal line 14. A control part A5 detects that the value equal to the contents of a mode switching register 3 is sent to the bus 13. The contents of a register 4 for set mode value are stored in a mode register 10. Therefore it is possible to change the action mode display value to M2 from M1 as soon as the program control is branched to P2 from P1. In such a way, the mode switching is possible even with a system containing no action mode display function.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an operation mode display device for displaying the operation mode of an arithmetic processing unit in a computer system such as a microcomputer.

Conventional configurations and their problems With the development of microcomputers, microcomputer systems have also become larger, and processing capabilities comparable to those of previous minicomputers are now being demanded and implemented. While it was possible to manage everything by the user while the scale of the system was small, as the scale of the system increased, resources such as user programs, peripherals, and main memory could be managed more efficiently and the processing unit It is hoped that a control program will be introduced to control the operation of the system, thereby significantly reducing user management. In this case, the resources that can be handled by the user program and the control program are clearly differentiated due to the nature of their processing contents.

This point will be explained using the aspect of input/output management as an example.

A secondary storage device is a typical input/output device of a computer system. Programs and data are held in the form of files on the secondary storage device, and are recorded according to a certain format defined by the system. This fixed format is not managed by the user but by the control program, so that the user does not need to know the file format. Therefore, input/output to the secondary storage device cannot be performed directly from the user program, and must be configured so that the control program is used as an intermediary. In other words, it is necessary to switch the control of the hardware device so that access to the input/output device is prohibited or disabled while the user program is running, and access to the outgoing car area is allowed only while the user program is running. Become.

In this way, in order to instruct the switching of hardware devices, there is an operation mode display device that displays whether the currently running program is the authorized program (control program) or the non-privileged program (program for use). It becomes necessary.

This function of displaying the operating mode is provided by the arithmetic processing unit itself in minicomputers and above, but microprocessors that currently exist and are widely used have the s-1 function.
The above idea is still a no-go for LSI, and the number of pins is limited.
Since it does not have an operation mode display function, it is a major obstacle in constructing a high-performance microprosenosan stem. Moreover, this switching of hardware due to a change in operating mode must be performed in hardware at the same time as branching of the program (change in operating mode) due to the privileged and non-privileged nature of programs. Also, there may be multiple types of privileged modes.

OBJECTS OF THE INVENTION As described above, an object of the present invention is to provide an operation mode display device for a system in which the arithmetic processing unit itself does not have an operation mode display function.

Structure of the Invention The present invention comprises a mode register, a mode switching address register, a setting mode value register, a mode save register,
Equipped with a mode return address register, when the arithmetic processing unit accesses the same address as the contents indicated in the mode switching address register in an instruction code read cycle, the contents of the mode register are stored in the mode save register, and after storing, the setting mode value register is Store the contents in the mode register to change the operation mode value, access the same address as the contents shown in the mode return slip register as an instruction code read cycle, and then store the contents of the mode save register in the mode register at the Nth operation cycle. By storing the return to
This displays the operating mode.

DESCRIPTION OF EMBODIMENTS FIG. 1 shows an embodiment of an operation mode display device according to the present invention. In FIG. 1, 1 is an arithmetic processing unit, 2 is a main memory, 12 is a data bus, and 13 is an address bus. 3 is a mode switching address register, 4 is a setting mode value register, 6 is a mode return address register, and 14 is an instruction read status display signal indicating that the arithmetic processing unit 1 is accessing the main memory 2 as an instruction code read cycle. line (hereinafter referred to as fetch signal).

10 is a mode register, 11 is a mode save register, 5
7 is a mode return delay value register, 8 is a sub-control unit B, and 9 is a mode return delay counter section. Here, for the sake of explanation, the control unit A6 and the mode switching address register 3. A pair of setting mode value registers 4 and a sub-control unit B8 . Each pair of return delay value register 7 and mode return address register 60 is one set.

Currently, the arithmetic processing unit 1 is executing program P1 that is allowed to run in mode M1, branches to program P2 that is allowed to run in mode M2, and branches to program P2 that is allowed to run in mode M2.
After completing the processing in step 2, return to program P1 again and switch to mode M1.
Consider the case where processing continues with .

Since the currently running program P1 is allowed to run in mode M1, the value Ml is set in the mode register 10 at the same time as the execution of program P1 is started to indicate that the operating mode is Ml. Stored. The mode switching address register 3 contains the execution start address of program P2, the setting mode value register 4 contains the mode value M2 at which execution of program P2 is permitted, and the mode return address register 6 contains the execution start address of program P2. The address where the instruction to return to the program P2 is stored is stored in the mode return delay value register 7, and the operating mode is instructed to be returned at the Nth instruction code reading cycle after the execution of the return instruction from program P2. Instead, the value N is preset in each case by means not shown.

It is assumed that the machine processing unit 1 can read and write the contents of the mode save register 11 by means not shown.

When the fetch signal line 14 is 111, the control unit A5 compares the value of the address bus 13 and the contents of the mode switching address register 3, and if they match, sends a coincidence detection signal to the mode switching signal line 1.
6, the contents of the mode register 1o are transferred to the mode save register 11 via the mode display signal line 21, and the contents of the setting mode value register 4 are transferred to the mode register 10 via the setting mode data line 20.

When the fetch signal line 14 is 111, the sub-control unit B8 compares the value of the address bus 13 and the contents of the mode return address register 6, and if they match, outputs a coincidence detection signal to the mode return detection signal line 16, and returns to the mode. The contents of the delay value register 7 are transferred to the mode return delay counter section 9 via the return delay data line 23.

The mode return delay counter section 9 is connected to the mode return detection signal line 1.
When the value of 6 changes from 11+ to 101 (when it falls), it is initialized to the value indicated by the return delay data line 23, and when the fetch signal line 14 falls in synchronization with 9 o'clock, the value is decreased by 1. is set and the counter value is 1.
The value of the input signal 14 is transmitted to the mode return signal line 17, and when the value of the mode return signal line 17 becomes 111, the contents of the mode save register 11 are transferred to the mode register 10 via the mode return data line 22. . Further, when the value of the counter becomes 0, the operation of the mode return delay counter section 9 is stopped.

An explanation will be added regarding the operation of the mode return delay counter section 9. FIG. 3 is a schematic diagram of a case where program P1, which is allowed to be executed in operation mode M1, branches to program P2, which is allowed to be executed in operation mode M2, and returns to program P1 after completing processing in program P2. shows. Considering the relationship between the operating mode value and the program execution permission mode, if the program Pi has an operating mode value Mi
To be allowed to execute the program, the value of the operation mode value M1 must be guaranteed while the program Pi is in operation (i=1.2). Program P1 to Program P2
When branching to , the control section A mentioned above causes the program P to
1 and the operation mode value M1, and the correspondence between the program P2 and the operation mode value M2 are guaranteed. However, when returning from program P2 to program P1, if program P2 fetches the return instruction and returns the operating mode value to Ml,
Even though the program P2 is executing the return instruction, the operation mode value becomes M1, and the correspondence between the program P2 and the operation mode value M2 cannot be guaranteed.

Therefore, after program P2 fetches the return instruction,
It is necessary to control so that the operating mode value during the period immediately before restarting the program P1 after a series of return procedures is completed is M2, and the mode return delay counter section 9 fulfills this function.

When a program P1 running in mode M1 calls a program P2 executable in mode M2, the arithmetic processing unit 1
outputs the execution start address of program P2 to the address bus line 13 and outputs 111 to the fetch signal line 14 at the same time. At this time, the control unit A5 detects that the same value as the content of the mode switching address register 3 is output to the address bus 13 in the fetch cycle of the instruction, and by the above-mentioned function, the mode save register 11 is stored in the mode register 1o. The contents M1 are stored in the mode register 1o, and the contents M2 of the setting mode value register 4 are stored in the mode register 1o. As a result, the program control branches from program P1 to program P2, and at the same time, the operation mode display value of arithmetic processing unit 1 also changes from Ml to M.
It can be changed to 2. Next, the processing of program P2 ends.

When returning to the program P1, the sub-control unit B8 detects that the same value as the contents of the mode return address register 6 is output to the address bus 13 in the instruction fetch cycle, and uses the above-mentioned function to set the mode return delay value. Contents of register 7 N
is transferred to the mode return delay counter section 9, and then transferred to the mode save register 11 at the subsequent N-th fetch signal output.
The content M1 of is stored in the mode register 10, and the l'L1 operating mode value can be returned to Ml.

As described above, according to this embodiment, even in a computer system using an arithmetic processing unit that does not have an operation mode display function, it is possible to simultaneously switch programs and hardware, which are defined by the operation mode. , it is possible to prevent the user from illegally changing the mode and gaining access rights to resources that are not allowed to be accessed without branching to a program with a different mode. In this embodiment, a mode switching address register, a setting mode value register,
Mode return address register, mode return delay value register,
Although the control section A and the sub-control section B are set as one set, it is also possible to have a plurality of sets, and if the mode return delay value is constant, only one mode return delay value register is required.

Furthermore, if multiple operating modes are defined, when the program is called, the contents of the mode save register are read and saved to the work area, and the contents of the saved work area are stored again to the mode save register before returning. Therefore, it is possible to nest the operating modes themselves in the same way as the programs themselves. Since the mode of the calling program can be confirmed by referring to the contents of the mode save register, it is possible to prevent illegal calls when the operating modes form a hierarchical structure, such as Ml - M2 - M3 from a lower level. It is possible to detect a jump call of an M3 program from an M1 program in such cases.

Note that the input signal that decreases the value of the return delay counter section is not limited to the fetch signal, and depending on the mutual inclusion relationship of the range of resources that can be handled determined by the operation mode value (for example, Sl and P2, etc.), the input signal that decreases the value of the return delay counter section is not limited to the fetch signal. It is also possible to omit the return delay value register.

Effects of the Invention The operation mode display device of the present invention detects that the arithmetic processing unit accesses a preset address as an instruction code read cycle, and stores the operation mode value defined in that case in the mode register. By providing the first control section and the second control 1''-6 for restoring the saved operation mode value to the mode register, it is possible to use an arithmetic processing unit without an operation mode display function. In the system as well, the operating mode display value can be changed at the same time as processing is transferred to a program with a different operating mode.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of an operation mode display device in one practical example of the present invention, FIG. 2d is a timing diagram showing the operation of the mode return delay counter section in FIG. FIG. 1...Arithmetic processing unit, 2...Main storage device, 3-
...Mode switching address register, 4... -Setting mode value register, 5...Control unit A (first control unit)
, 6... -Mode return address register, 7...Mode return delay value register, 8...Sub-control unit B, 9--
・Mode return delay counter section, 10...Mode register, 11...Mode save register, 30-...
...control unit B (second control unit).

Claims (1)

[Scope of Claims] (1) A mode register for displaying an operating mode of the arithmetic processing unit of a computer system including an arithmetic processing unit and a main storage device that holds a program executed by the arithmetic processing unit, and a mode switching address. Compare the contents of the register, the setting mode value register, the mode return address register, the mode save register, the address value outputted by the arithmetic processing unit to the main memory as an instruction code read cycle, and the mode switching address register. , a first control unit that stores the contents of the mode register in the mode save register when a match is detected, and stores the contents of the setting mode value register in the mode register after storage; The address value outputted as an instruction code read cycle is compared with the contents of the mode return address register, and the contents of the mode save register are compared with the contents of the mode save register in the An operation mode display device comprising: a second control unit storing data in a mode register; (?) a mode switching address register, a setting mode value register,
Claim (1) characterized in that it has a plurality of sets of a mode return address register, a first control unit, and a second control unit, and the value of N can take a different value depending on each set. Operation mode display device as described in section. (3) Claim (1) characterized in that the unit of N is the instruction code reading cycle of the arithmetic processing unit.
The operation mode display device according to item (2) or item (2). (4) The operation mode display device according to claim (1) or (2), wherein the unit of N is 77 cycles of the arithmetic processing unit.