JPH0221614B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an operation mode display device for displaying the operation mode of an arithmetic processing unit in a computer system such as a microcomputer.

Conventional configurations and their problems With the development of microcomputers, microcomputer systems have become larger, and processing capabilities comparable to those of previous small-sized minicomputers are now being demanded and realized. As long as the scale of the system was small, it was possible to have everything managed by the user, but as the scale of the system increased, resources such as user programs, peripherals, and main memory could be managed more efficiently, and the processing It is hoped that a control program will be introduced to control the operation of the system, thereby significantly reducing user management. In this case, the resources that can be handled by the user program and the control program are clearly differentiated due to the nature of their processing contents. This point will be explained using the aspect of input/output management as an example.

A secondary storage device is a typical input/output device of a computer system. On the secondary storage device,
Programs and data are held in the form of files, and they are recorded according to a certain format defined by the system. This fixed format is not managed by the user, but by the control program, so that the user does not need to know the file format. Therefore, input/output to the secondary storage device cannot be performed directly from the user program, and must be configured so that the control program is used as an intermediary.
In other words, it is necessary to switch the control of the hardware device so that access to the input/output device is prohibited or disabled while the user program is running, and access to the input/output device is allowed only while the control program is running.

In this way, in order to instruct switching of hardware devices, an operation mode display device is required that displays whether the program in operation is a privileged program (control program) or a non-privileged program (user program). This function of displaying the operation mode is possessed by the arithmetic processing unit itself in minicomputers and above, but in the microprocessors that exist and are widely used, there is a function to display the operation mode due to design considerations or LSI (large scale integrated circuit). Due to the limited number of pins, it does not have an operation mode display function, which is a major obstacle in building a high-performance microprocessor system. Also, there may be multiple types of privileged modes,
Furthermore, this switching of hardware due to a change in operating mode must be performed in hardware at the same time as program branching (change in operating mode) due to the privileged and non-privileged nature of programs.

OBJECTS OF THE INVENTION In view of the above drawbacks, it is an object of the present invention to provide an operation mode display device for a system in which the arithmetic processing unit itself does not have an operation mode display function.

Composition of the Invention In order to achieve the above object, the present invention detects that a preset address is accessed as an instruction code read cycle, stores the operation mode value defined at that time in an operation mode register, and stores the operation mode value defined at that time in an operation mode register. It is designed to express.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

The figure shows the configuration of an operation mode display device in an embodiment of the present invention.

In the figure, 11 is an arithmetic processing unit, 12 is a main storage device, 13 is a data bus line, and 14 is an address bus line. 15 and 25 are mode switching address registers, 19 and 29 are setting mode value registers, and 21 is an instruction reading status display signal line (hereinafter referred to as , Fetch signal line), 17 is a mode register, 22
is a mode save register, and 16 and 26 are control units.

Currently, the arithmetic processing unit 11 is executing a program P1 that is allowed to be executed in mode M1, and a program P2 that is allowed to be executed in mode M2.
After the processing of program P2 is completed, the program branches to program P1 and continues processing in mode M1.

Now, the currently running program P1 is in mode M1.
Since execution is allowed in the mode register 17 at the same time as execution of the program P1 is started.
A value M1 is stored in the field to indicate that the operation mode is M1. Note that the mode switching address register 15 is preset with the execution start address of the program P2, and the setting mode value register 19 is preset with a mode value M2 at which execution of the program P2 is permitted. When the fetch signal line 21 is "1", the control section 16 compares the value of the address bus 14 and the contents of the mode switching address register 15, and if they do not match, outputs "0" to the mode switching signal line 18, and if they do not match. If so, “1” is sent to the mode switching signal line 18.
is output, and in synchronization with this signal "1", the contents of the mode register 17 are transferred to the mode save register 22 via the mode display signal line 23, and the contents of the setting mode value register 19 are transferred via the setting mode data line 20. Transfer to mode register 17. Control unit 26
has a similar function, but the contents of the mode switching address register 25 and the setting mode value register 29 are undefined at present.

When program P1 running in mode M1 calls program P2 that can be executed in mode M2,
The arithmetic processing unit 11 outputs the execution start address of the program P2 to the address bus line 14 and at the same time outputs "1" to the fetch signal line 21. Then, the control section 16
detects that the same value as the content of the mode switching address register 15 is output to the address bus 14 in the fetch cycle of the instruction, and the content M1 of the mode register 17 is stored in the mode save register 22 by the above-mentioned function. , the content M2 of the setting mode value register 19 is stored in the mode register 17.
Thereby, after the program control branches from the program P1 to the program P2, the operation mode display value of the arithmetic processing unit 11 can also be changed from M1 to M2 at the same time.

Next, when the processing of program P2 ends and returns to program P1, the contents of the mode save register 22 are read (currently M1), the value is stored in the setting mode value register 29, and the return is made to the calling program. After storing the address in the mode switching address register 25, when a return instruction to the calling program is executed, the instruction stored at the return address is fetched by the same mechanism as when program P2 starts execution, and the program control is changed to program P2.
At the same time as returning to program P1 from M2, the operating mode display value can be returned from M2 to the operating mode display value of the calling program (M1 in this case).

As described above, according to this embodiment, even in a computer system in which the arithmetic processing unit 1 itself does not have an operation mode display function, switching of programs and hardware defined by the operation mode is possible. It is possible to prevent unauthorized mode changes and gaining access rights to resources to which access is not permitted, without branching to programs with different modes.

In this embodiment, mode switching address register 1
Although two sets each of the 5, 25 setting mode value registers 19, 29 and the control units 16, 26 are provided, it is also possible to have three or more sets each. Furthermore, if the return mode value after changing the operating mode, that is, the value set in the setting mode value register 29 in this embodiment, is a value that is always known in advance, the mode save register 23 can be omitted. be.

Further, an LED or the like may be connected to the mode display signal line 23 so that the display state can be determined.

Also, if multiple operation modes are defined,
Similar to the nesting of the program itself, the operating mode itself can also have a nesting structure, and the mode of the calling program can be confirmed by referring to the contents of the mode save register 22, so the operating mode itself can be nested. It is possible to detect illegal calls when a hierarchical structure is formed, such as overcalls from program P1 to program P3 even when there are P1-P2-P3 from a lower level.

Effects of the Invention As described above, the operation mode display device of the present invention detects that a preset address is accessed as an instruction code read cycle, and stores the operation mode value defined in that case in the operation mode display register. By providing a control section to
Even in a computer system using an arithmetic processing unit that does not have an operation mode display function, the operation mode display value can be changed the moment processing shifts to a program with a different operation mode, and this has great value.

[Brief explanation of drawings]

The figure is a block diagram of an operation mode display device which is an embodiment of the present invention. 11...Arithmetic processing unit, 12...Main storage device,
15, 25...Mode switching address register, 16,
26...Control unit, 17...Mode register, 1
9, 29...Setting mode value register, 22...Mode save register.

Claims (1)

[Scope of Claims] 1. An arithmetic processing device that performs arithmetic processing, a main storage device that holds a program executed by the arithmetic processing device, a mode register that displays an operating mode of the arithmetic processing device, and a mode switchable mode register. A mode switching address register that stores an address value, a setting mode value register that stores a value of the mode to be switched, and an address value that the arithmetic processing unit outputs from the main memory as an instruction code read cycle. An operation mode display device comprising: a control unit that compares the contents of the mode switching address register and stores the contents of the setting mode value register in the mode register if they match. 2. The operation mode display device according to claim 1, comprising a plurality of sets of mode switching address registers, setting mode value registers, and control sections. 3. An arithmetic processing unit that performs arithmetic processing, a main memory that holds programs executed by the arithmetic processing unit, a mode register that displays the operating mode of the arithmetic processing unit, and a value of an address at which the mode is switched. a mode switching address register, a setting mode value register storing the value of the mode to be switched, a mode save register,
Compare the address value outputted by the arithmetic processing unit to the main memory as an instruction code read cycle with the contents of the mode switching address register, and if they match, store the contents of the mode register in the mode save register. , a control section that stores the contents of the setting mode value register in the mode register. 4. The operation mode display device according to claim 3, comprising a plurality of sets of mode switching address registers, setting mode value registers, and control sections.