JP4641391B2 - Direct memory access device, control method therefor, and data processing device - Google Patents

Description

The present invention relates to a direct memory access device, a control method therefor, and a data processing device capable of simultaneously and independently executing complicated data transfer using various access patterns.

  Conventionally, in order to realize data transfer between a device (a device that generates data and writes data in a memory, or a device that reads data from the memory and performs data processing) and the memory without applying a load on the CPU, various direct operations are performed. A memory access (Direct Memory Access: hereinafter abbreviated as DMA) device has been proposed (see, for example, Patent Document 1).

In a typical DMA device, first, the memory address of the data transfer destination or data transfer source, the data transfer direction (the data transfer direction from the device to the memory, the data transfer direction from the memory to the device), the size of the data to be transferred, etc. Is previously set by the CPU. Next, when the data transfer operation is started, data transfer between the device and the memory is performed without intervention of the CPU until the transfer of the data of the set size is completed while sequentially updating the set memory addresses. When the data transfer is completed, the DMA device notifies the CPU of an interrupt, so that the CPU recognizes the completion of the data transfer and processes the transferred data. Further, similarly to the above, setting and starting related to another data transfer are continuously performed.
JP-A-5-67033

  However, the conventional DMA device performs data transfer according to a fixed access pattern. For this reason, in order to execute complex data transfer using various access patterns, it is necessary to change the setting for each access pattern with a CPU (software), which increases the load on the CPU. . As a solution to this problem, DMA devices having various access patterns have been proposed in advance, but there is a problem that the circuit scale increases as the number of access patterns increases.

  In addition, when it becomes necessary to cope with a new access pattern after the development of the hardware of the DMA device, the developed hardware can only deal with a fixed access pattern, so that it is necessary to recreate the hardware. There was a point.

  In addition, if multiple devices issue data transfer requests at the same time and need to transfer data to different memory addresses according to each data transfer request, prepare DMA devices for the number of devices. Therefore, there is a problem that the circuit scale increases.

An object of the present invention is to enable complex data transfer without increasing the circuit scale, and when a data transfer command is received, if there is no data transfer request from a device related to the data transfer command, other commands It is an object of the present invention to provide a direct memory access device, a control method therefor, and a data processing device that are capable of processing efficiently by controlling so as to process.

In order to achieve the above object, a direct memory access device according to the present invention includes a plurality of program counters that hold addresses storing instructions, a selection unit that selects one of the plurality of program counters , and data A plurality of instructions including a transfer instruction, an instruction storage means for outputting an instruction stored at an address of a program counter selected by the selection means, a device and a memory according to the instruction output from the instruction storage means When no data transfer request is output from an execution unit that executes data transfer between the data transfer device and a device that is a target of data transfer by the data transfer command output from the command storage unit, there is no data transfer request. Suppressing selection by the selection means of a program counter corresponding to a device data transfer instruction Suspends execution of the data transfer instruction by said execution means, and a execution control means for executing on said execution means an instruction program counter other than the program counter that holds the data transfer instruction is indicated by the address holding It is characterized by that.

According to the present invention, data transfer between a device and a memory is executed in accordance with an instruction output from an instruction storage unit that stores a plurality of instructions including a data transfer instruction. Here, when a data transfer request is not output from a device that is a target of data transfer by the data transfer instruction, the selection of the program counter corresponding to the data transfer instruction of the device that does not have the data transfer request is suppressed. The execution of the data transfer instruction is suspended, and the execution means is caused to execute the instruction indicated by the address held by the program counter other than the program counter holding the data transfer instruction. Thereby, a plurality of data transfers can be executed in parallel according to each data transfer request. Therefore, unlike the conventional case, it is not necessary to switch the setting through the CPU when executing complicated data transfer, and complex data transfer (direct memory access transfer) can be realized without increasing the circuit scale. Is possible. As a result, it is possible to flexibly switch tasks related to a plurality of transfer instructions without interposing a CPU. Also, when a data transfer instruction is received, if there is no data transfer request from the device related to the data transfer instruction, execution of the data transfer instruction without the data transfer request is suspended and other instructions are processed. By doing so, it is possible to process efficiently.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a block diagram showing an electrical configuration of a DMA device as a data transfer device according to the first embodiment of the present invention.

  In FIG. 1, the DMA device includes a program counter (PC) 3-1, 3-2, 3-3, a program counter selection unit 4, an instruction memory 5, an instruction decoding unit 6, a data transfer execution unit 7, an execution suppression / selection. A permission signal generation unit 8, a program counter selection signal generation unit 9, and a program counter update unit 10 are provided.

  The DMA device is connected to the DMA devices 1-1 and 1-2 for making a data transfer request and the CPU bus 14, and stores data and the memory 2 as the data transfer source or the data transfer destination, and the CPU bus 14. A CPU 11 is connected to control the operation of the DMA device. The DMA device, the DMA devices 1-1 and 1-2, the memory 2, and the CPU 11 constitute a data processing device.

  In addition, in the notation of the lines connecting the blocks in FIG. 1, the data system connection is illustrated by a thick white solid line, and the control system connection is illustrated by a thin solid line. However, not all the connections are illustrated, and only representative connections necessary for the description of the present embodiment are shown.

  Program counters 3-1, 3-2 and 3-3 indicate addresses of data transfer instructions being executed in the instruction memory 5. The program counter selection unit 4 converts the value stored in one of the program counters 3-1, 3-2 and 3-3 into the program counter selection signal output from the program counter selection signal generation unit 9. Based on this, the address of the instruction memory 5 is selected. The instruction memory 5 stores a data transfer instruction. The instruction decoding unit 6 decodes a data transfer instruction that is a data output of the instruction memory 5 and determines a data transfer direction, a data transfer destination, a data transfer source, and the like.

  The data transfer execution unit 7 drives the two DMA ports 7-1 and 7-2 or the bus interface 7-3 in accordance with the data transfer instruction decoded by the instruction decoding unit 6, so that the DMA devices 1-1, 1 and 1 are driven. -2 and data transfer between the memory 2 are executed. Details of the data transfer execution unit 7 will be described later.

  The execution suppression / selection permission signal generation unit 8 includes a transfer source / transfer destination detection unit 8-1, a DMA request detection unit 8-2, a match determination unit 8-3, an execution suppression signal generation unit 8-4, and a selection permission signal generation. Part 8-5. When the data transfer request is not output from the DMA device as the data transfer source or the data transfer destination, the execution suppression / selection permission signal generation unit 8 deselects the program counter corresponding to the data transfer instruction being executed. The data transfer instruction indicated by the program counter can be executed. The details of the execution suppression / selection permission signal generator 8 will be described later.

  The transfer source / transfer destination detector 8-1 detects the data transfer source or the data transfer destination based on the output of the instruction decode unit 6. The DMA request detector 8-2 detects a data transfer request from the DMA devices 1-1 and 1-2. The coincidence determination unit 8-3 determines whether or not the detection result of the transfer source / transfer destination detection unit 8-1 matches the detection result of the DMA request detection unit 8-2, that is, whether the data transfer source or the data transfer destination is DMA. It is determined whether or not the DMA device is outputting a data transfer request.

  In the execution suppression signal generation unit 8-4, the determination result of the match determination unit 8-3 does not match (the detection result of the transfer source / transfer destination detection unit 8-1 does not match the detection result of the DMA request detection unit 8-2). In this case, an execution suppression signal for suppressing data transfer of the data transfer execution unit 7 is output. When the determination result of the match determination unit 8-3 does not match, the selection permission signal generation unit 8-5 sets the program counter corresponding to the currently executing data transfer instruction until the data transfer request is output from the DMA device. A program counter selection permission signal for selection is generated.

  The program counter selection signal generation unit 9 generates a program counter selection signal to be sent to the program counter selection unit 4 every time data transfer is executed based on the program counter selection permission signal output from the selection permission signal generation unit 8-5. Based on the program counter selection signal output from the program counter selection signal generation unit 9, the program counter update unit 10 updates the value of the selected program counter one by one for each data transfer execution. The CPU 11 stores a data transfer command in the command memory 5 via a data port (not shown) and controls the operation of the DMA device.

  Next, the program counter 3-1, 3-2, 3-3, the program counter selection unit 4, the instruction memory 5, the data transfer execution unit 7, the execution suppression / selection permission signal generation unit 8, the program counter shown in FIG. The update unit 10 and the CPU 11 will be described in more detail.

  In each block of FIG. 1, first, the reset of the CPU 11 is released. The CPU 11 can sequentially release the reset of each block by controlling a reset signal (not shown) by fetching and executing an instruction from the built-in ROM. In the reset state of all the blocks other than the CPU 11, first, the CPU 11 writes a data transfer instruction executed by the DMA device into the instruction memory 5.

  FIG. 2 is a block diagram showing the actual configuration and input / output ports of the instruction memory 5 used in the DMA device.

  In FIG. 2, an instruction memory 5 is a 2-port (1Read / 1Write) SRAM, and has a data width of 32 bits and a word length of 64. The read address (READ ADDRESS) of the instruction memory 5 is 6 bits. When a read enable signal (READ ENABLE) is asserted, 32-bit read data is read from the READ DATA port. In the present embodiment, the read address is supplied from the program counter selection unit 4 and the read data is supplied to the instruction decoding unit 6.

  The write address (WRITE ADDRESS) of the instruction memory 5 is 6 bits, and when the write enable signal (WRITE ENABLE) is asserted, the data transfer instruction data driven on the 32-bit write data (WRITE DATA) signal is written to the write address. Is written to. In this embodiment, both the write address and the write data are supplied from the CPU 11.

  When the writing of the data transfer command data to the command memory 5 is completed, the CPU 11 releases the reset of each block and the DMA device starts its operation.

  FIG. 3 is a block diagram showing the detailed configuration of the program counter 3-1, 3-2, 3-3, the program counter selection unit 4, and the program counter update unit 10.

  In FIG. 3, each of the program counters 3-1, 3-2, 3-3 is composed of 6-bit flip-flops, and initial values at reset are “000000”, “010000”, “100000”, respectively. It has become. That is, the program counter 3-1 executes an instruction from the address 0x0, the program counter 3-2 executes an instruction from the address 0x10, and the program counter 3-3 executes an instruction from the address 0x20. The program counter update unit 10 includes a selector 10-1, a selector 10-2, and a +1 adder 10-3.

  The output signal of the selector 10-1 is input to the program counter 3-1. The selector 10-1 includes the current value of the program counter, the value obtained by adding 1 to the current value, the value loaded by the Load instruction (store_d), and the return value of the program counter when looping back by the Loop instruction (lp_back_pc) , One of the jump destination addresses (jump_pc) by the Jump instruction is selected and output.

  The selector 10-2 selects either the program counter output itself (current value) or the value obtained by adding 1 to the program counter value (the output of the +1 adder 10-3) as the program counter selection signal pc_sel. Select based on. That is, the selector 10-2 selects a value obtained by adding 1 to the value of the program counter when the program counter is selected in the clock cycle, and the current value when the program counter is not selected. Select.

  The program counters 3-2 and 3-3 also have the same configuration as the program counter 3-1, and the program counter update unit 10 updates the program counter value.

  The program counter selection unit 4 responds to the 3-bit program counter selection signal pc_sel [2: 0] with program counters 3-1 (PC (0)), 3-2 (PC (1)), 3-3 (PC One of the outputs of (2)) is selected and output as a read address of the instruction memory 5. pc_sel [2: 0] is a one-hot signal (a signal in which 1 of 3 bits is “1”). When “001”, the program counter 3-1 is selected, and when “010”, the program counter 3-1 is selected. 3-2 is selected. When “100”, the program counter 3-3 is selected. That is, when pc_sel [n] = “1”, PC (n) is selected (where n = 0, 1, 2).

  FIG. 4 is a block diagram showing a detailed configuration of the program counter selection signal generation unit 9.

  In FIG. 4, flip-flops 9-1, 9-2, 9-3 of the program counter selection signal generation unit 9 are connected to a clock signal and a reset signal, respectively, and the output is a program counter selection signal. The flip-flop 9-1 is set to “1” by the reset signal, the output of the selector 9-4 is connected to the D input, and the Q output becomes pc_sel [0]. In the flip-flop 9-2, "0" is set by the reset signal, the output of the selector 9-5 is connected to the D input, and the Q output becomes pc_sel [1]. In the flip-flop 9-3, "0" is set by the reset signal, the output of the selector 9-6 is connected to the D input, and the Q output becomes pc_sel [2].

  The decoder 9-7 of the program counter selection signal generator 9 outputs a program counter selection permission signal output from the selection permission signal generator 8-5 of the execution suppression / selection permission signal generator 8 and a stall instruction for executing the data transfer instruction. Decode the stall signal shown. The decoder 9-7 generates program counter selection signals (sel_cnt [0], sel_cnt [1], sel_cnt [2]) indicating which program counter should be selected as a result of decoding, and selects the selectors 9-4, 9-. 5 and 9-6, respectively.

  FIG. 5 is a diagram showing a relationship between a stall that is an input and a program counter selection signal that is an output with respect to the program counter selection permission signal.

  In FIG. 5, the illustrated table shows the relationship between the stall that is an input and the program counter selection signal sel_cnt [2: 0] that is an output with respect to the program counter selection permission signal pc_en [2: 0]. For example, when the stall is “1”, sel_cnt [2], sel_cnt [1], and sel_cnt [0] are all 2, and all the flip-flops 9-1, 9-2, 9− of the program counter selection signal generation unit 9 are set. 3 holds the current value. That is, pc_sel is not updated.

  When stall is “0” and pc_en = “111”, sel_cnt [2], sel_cnt [1], and sel_cnt [0] are all 0, and pc_sel operates as a shift register. That is, transition is made from “001” → “010” → “100” → “001”, and the program counter is selected in the order of PC (0) → PC (1) → PC (2) → PC (0). If the stall is “0” and pc_en = “011”, sel_cnt = “301” and pc_sel is “001” → “010” → “001” → “ Transition is made from “010” to “001”, and the program counter is selected in the order of PC (0) → PC (1) → PC (0) → PC (1) → PC (0).

  A data transfer instruction corresponding to the program counter selected by the program counter selection unit 4 is read from the instruction memory 5 and input to the instruction decoding unit 6. The data transfer instruction is composed of 32 bits and is decoded by the instruction decoding unit 6 as shown in FIG.

  FIG. 6 is a diagram showing an instruction decoded by the instruction decoding unit 6.

  In FIG. 6, the numbers in [] of Inst shown below correspond to the numbers described in the upper two columns of FIG. When a 32-bit data transfer instruction is expressed as Inst [31: 0], the instruction decoding unit 6 has a special instruction when Inst [31:30] = “00”, and Inst [31:30] = “ When 01 ”, it is decoded as a load instruction, when Inst [31:30] =“ 10 ”, it is decoded as a store instruction (Store Instruction), and when Inst [31:30] =“ 11 ”, it is decoded as an invalid instruction.

  The load instruction is a data transfer instruction from the memory 2 to the internal resources (including the DMA port) of the DMA device. The store instruction is a data transfer instruction from the internal resource to the memory 2. Special instructions include instructions provided in general processors such as NOP instructions (instructions that do nothing), loop instructions (Loop), jump instructions (Jump), and the like.

  Inst [29:27] is a field indicating the data size, and details are shown in FIG. For example, when the data size is “000”, 1-byte data transfer is indicated, and when the data size is “100”, it indicates 5-byte data transfer.

  Inst [26:23] is a field indicating the index of the data transfer source resource, and Inst [22:19] is a field indicating the index of the data transfer destination resource. These include the resource identifier indicated by Inst [18:16] (indicating the data transfer destination in the case of a load instruction and the data transfer source in the case of a store instruction), and what number of which internal resource is data Indicates whether to transfer.

Details of the internal resource identifier are shown in FIG. “000” indicates a PC, that is, a program counter. “001” indicates AR, that is, an address register. “010” indicates GPR, that is, a general-purpose register. “01 1 ” indicates IN / OUT, that is, a DMA port (IN / OUT is identified by whether it is a load or a store). “100” indicates LP, that is, a loop register. “101” indicates OFST, that is, an offset register. Details of the address register AR, the general-purpose register GPR, the loop register LP, and the offset register OFST will be described later.

  The internal resource identifier indicating the data transfer source in the case of the load instruction and the data transfer destination in the case of the store instruction is fixed in the address register, and only the index is designated by each index field.

  Inst [15:13] is a field indicating the valid byte lane of the data transfer source or the data transfer destination, and indicates how many bytes are transferred to and from which byte lane together with the data size field.

  9 and 10 are diagrams illustrating the relationship among the data size field, the byte lane field, and the effective byte lane.

  In FIG. 9 and FIG. 10, the tables shown in detail show the byte lanes that are effective depending on the combination of the data size and the byte lane. The data is 64-bit and byte lanes are [63:56], [55:48], [47:40], [39:32], [31:24], [23:16], [15: 8 ], [7: 0], there are 8 lanes, and “v” is written in the effective byte lane. For example, if the data size field (size) is “000” or 1 byte, and the byte lane field (pos_d / s) is “011” or 4th byte lane, data [31:24] (data bus signal) is used. Thus, 1 byte of data is transferred.

  Here, in order to deepen the understanding of data transfer instructions (load instruction, store instruction, special instruction) handled by the DMA device, some examples of data transfer instructions are shown below.

  When Inst = “01_000_0001_0010_100_001_000000000000”, this is a load instruction, and 1-byte data on the memory 2 indicated by the address register AR (1) is loaded into [15: 8] of the loop register LP (2).

  When Inst = “10_111_0001_0010_011_000_000000000000”, this is a store instruction, and 8-byte data read from the DMA input port IN (1) is stored in the memory indicated by the address register AR (2).

  FIG. 11 is a diagram illustrating encoding of special instructions.

  In FIG. 11, EnableThread is a command for enabling a specific program counter, and can be used when starting another program counter other than the program counter. DisableThread is a command that disables a specific program counter. When other program counters other than the program counter are put into a sleep state or when program execution ends, the program counter itself is put into a sleep state. Can be used when

  Jump is a jump instruction and copies the operand Inst [23:12] to the currently selected program counter. In the present embodiment, since the program counter has 6 bits, Inst [17:12] is actually copied. LoadImmidiateByte is an instruction for loading an immediate value into an internal resource, and copies 1 byte indicated by the operand Inst [7: 0] to the internal resource specified by the other operand. ClearResiger is an instruction to clear internal resources to zero. LoopIn is a loop entry instruction and realizes a loop by a combination of the loop register LP and the offset register OFST specified by LoopIndicator (Inst [22:19]).

  Returning to FIG. 1, the data transfer execution unit 7 executes data transfer according to the instruction decoding result of the instruction decoding unit 6. The data transfer execution unit 7 includes four general-purpose registers GPR, address registers AR, loop registers LP, and offset registers OFST (not shown) as internal resources. Further, the data transfer execution unit 7 uses the DMA port 7-1 (IN (0) and OUT (0)) for data transfer with the DMA device 1-1 and the DMA for data transfer with the DMA device 1-2. A bus interface 7-3 is provided for data transfer between the port 7-2 (IN (1) and OUT (1)) and the memory 1.

  The general-purpose register GPR is a register that temporarily holds data. For example, the general-purpose register GPR is used when data loaded from the memory 2 is copied to another internal resource for each byte. The address register AR is a register that generates an address to be output to the bus interface 7-3. Similar to a general processor, a configuration including a mode (automatic update addressing mode) for updating the value of the address register AR for each data transfer is also preferable. The loop register LP is a register indicating the number of instruction loops. The offset register OFST is a register indicating an instruction address to be looped back.

  A predetermined value is loaded into the loop register LP and the offset register OFST, and a loop instruction is executed to enter the loop. When the operation of the program counter progresses and the value of the program counter matches the value stored in the offset register OFST, the value of the program counter is updated to the address indicating the instruction next to the loop instruction, and the loop register LP Decrease the value by 1. When the value of the loop register LP becomes 0, the loop is exited, that is, 1 is simply added to the value of the program counter.

Here is an example of a program that uses a very simple loop.
Instruction address Instruction
0x00 Load immediate value 0x20 to AR (0) [7: 0]
0x01 Loads the value in memory indicated by AR (0) into LP (0)
(Data = 0x20)
0x02 Load immediate value 0x04 to OFST (0)
0x03 LoopIn instruction (indicator 0)
0x04 Read data from DMAPort (0) to memory address indicated by AR (1)
Store and AR (1) ++
0x05 Sleep yourself with DisableThread.

  According to the instruction sequence that constitutes the above program, a loop is entered by executing the instruction at address 0x03, and in the data transfer from the DMA port at address 0x04 to memory 2, the program counter loops back because it matches the offset register OFST. Jump to the next address of the instruction, that is, address 0x04. This is repeated the number of times of LP (0), that is, 32 times, and exits the loop and ends.

  The execution suppression / selection permission signal generation unit 8 is based on the instruction decoding result by the instruction decoding unit 6, the DMA request of the DMA devices 1-1 and 1-2, and the program counter selection signal from the program counter selection signal generation unit 9. In addition, an execution suppression signal to the data transfer execution unit 7 and a selection permission signal to the program counter selection signal generation unit 9 are generated.

  FIG. 12 is a block diagram illustrating a detailed configuration of the execution suppression / selection permission signal generation unit 8.

  In FIG. 12, comparators 6-1, 6-2, 6-3, 6-4, and 6-5 are included in the instruction decode unit 6, but are shown in FIG. The comparator 6-1 determines whether the instruction is a load instruction, and asserts a load signal if the instruction is a load instruction. The comparator 6-2 determines whether the instruction is a store instruction, and asserts a store signal if the instruction is a store instruction.

  The comparator 6-3 determines whether the data transfer source index or the data transfer destination index is 0, and asserts the Port0 signal when the index is 0. The comparator 6-4 determines whether the data transfer source index or the data transfer destination index is 1, and if the index is 1, asserts the Port1 signal. The comparator 6-5 determines whether the data transfer source or the data transfer destination is a DMA port, and asserts a DMA signal if it is a DMA port.

  The gates 8-11, 8-12, 8-13, and 8-14 constitute a transfer source / destination detection unit 8-1 of the execution suppression / selection permission signal generation unit 8. A load signal, a Port0 signal, and a DMA signal are input to the gate 8-11, and a logical product of three inputs is output as an LD_OUT0 signal. The LD_OUT0 signal indicates that an instruction for loading data to DMA port 0 has been issued. A load signal, a Port1 signal, and a DMA signal are input to the gate 8-12, and a logical product of three inputs is output as an LD_OUT1 signal. The LD_OUT1 signal indicates that an instruction to load data to DMA port 1 has been issued.

  The store signal, the Port0 signal, and the DMA signal are input to the gate 8-13, and a logical product of three inputs is output as the ST_IN0 signal. The ST_IN0 signal indicates that an instruction to read data from DMA port 0 and store it in the memory has been issued. The store signal, the Port1 signal, and the DMA signal are input to the gate 8-14, and a logical product of three inputs is output as the ST_IN1 signal. The ST_IN1 signal indicates that an instruction to read data from DMA port 1 and store it in the memory has been issued.

  Gates 8-31, 8-32, 8-33, and 8-34 constitute a coincidence determination unit 8-3 that detects whether or not a DMA request corresponding to the issued instruction is asserted. DMAOReq0 is asserted to “1” when the DMA device 1-1 requests data transfer from the memory 2. DMAOReq1 is asserted to “1” when the DMA device 1-2 requests data transfer from the memory 2. DMAIReq0 is asserted to “1” when the DMA device 1-1 requests data transfer to the memory 2. DMAIReq1 is asserted to “1” when the DMA device 1-2 requests data transfer to the memory 2.

  The outputs of the gates 8-31, 8-32, 8-33, and 8-34 indicate that when there is no data transfer request from the DMA port that the issued instruction is trying to access, one of them is at the “0” level. Become.

  The gate 8-41 constitutes the execution suppression signal generator 8-4, and outputs when any one of the outputs of the gates 8-31, 8-32, 8-33, and 8-34 becomes “0”. Becomes “0”. Therefore, the output of the gate 8-41 becomes an execution suppression signal (“0” level when it should be suppressed).

  Gates 8-51, 8-52, 8-53, and 8-54 detect which of the program counters that issued the DMA instructions received execution suppression when accessing which DMA port. The flip-flops 8-55, 8-56, 8-57, 8-58 hold the execution suppression detection result. Gates 8-21, 8-22, 8-23, and 8-24 constitute a DMA request detection unit 8-2 that detects that a DMA request corresponding to a DMA instruction whose execution is being suppressed is generated.

  When it is detected that a DMA request corresponding to the DMA instruction whose execution is being suppressed is generated, the flip-flops 8-55, 8-56, 8-57, and 8-58 are cleared. The gate 8-591 generates an execution suppression state, and the gate 8-592 generates an execution suppression release state. The execution suppression state of a specific program counter is generated by the gate 8-593, and this is output to the program selection signal generation unit 9 as the program counter selection permission signal pc_en [2: 0]. That is, when pc_en [n] is “1”, selection is permitted, and when it is “0”, selection is not permitted.

  In FIG. 12, an integer n indicates which program counter is used. Since n is 0, 1, or 2, in this embodiment, the gates 8-21, 8-22, 8-23, 8-24, 8-51, 8-52, 8-53, 8 -54, 8-591, 8-592, 8-593 and flip-flops 8-55, 8-56, 8-57, 8-58 are the number of program counters, that is, there are three sets, but illustration is omitted. ing.

  Next, the overall operation of the DMA apparatus of the present embodiment having the above configuration will be described in detail with reference to the timing chart of FIG. 13 and the flowcharts of FIGS.

  In the present embodiment, basically, a program indicated by the program counter PC (0) (instructions at addresses 0x03 and 0x05) transfers data to the DMA device 1-1, and the program indicated by the program counter PC (1) ( Instructions at addresses 0x12 and 0x16) are set to perform data transfer of the DMA device 1-2.

  In clock cycle 0, the Reset signal is asserted (“1”) and is in a reset state (step S1). In the reset state, the program counter selection signal pc_sel outputs “001”, and the program counter selection permission signal pc_en outputs “111”. The initial values of the program counter are PC (0) = 0x00, PC (1) = 0x10, and PC (2) = 0x20.

  In clock cycle 1, the reset is released, first the program counter PC (0) is selected (selected PC = PC (0)), and the instruction is executed (step S2).

  In clock cycle 2, pc_sel becomes “010”, the program counter PC (1) is selected, and the instruction is executed (step S3).

  In clock cycle 3, pc_sel becomes “100”, the program counter PC (2) is selected, and the instruction is executed (step S4).

  In this way, the program counter PC (0) → PC (1) → PC (2) → PC (0) is sequentially selected and the instruction is executed.

  In clock cycle 4, the data transfer request DMAReq1 of the DMA device 1-2 is asserted (“1”), but the transfer response signal DMAAck1 is not asserted because the data transfer command for the DMA device 1-2 is not executed (step S5). ).

  In clock cycle 6, the program counter PC (1) becomes 0x12, and this program counter PC (1) indicates a data transfer command to the DMA device 1-2 (step S6). The data transfer instruction is actually executed in clock cycle 8 when pc_sel becomes “010” next, and DMAAck1 is asserted in clock cycle 8 (step S7).

  On the other hand, in clock cycle 10, a data transfer instruction to DMA device 1-1 indicated by program counter PC (0) is issued, but since DMAReq0 is not asserted in clock cycle 10, program counter PC (0) Is suppressed from being executed (step S8). That is, the value of pc_en is “110”, and PC (0) remains 0x03 and is not updated. Until the clock cycle 14 when DMAReq0 is asserted, the programs indicated by the program counters PC (1) and PC (2) are executed in order (step S9).

  In clock cycle 14, when DMAReq0 is asserted (step S10), pc_en is updated to “111”.

  In clock cycle 15, PC (0) is selected and executed. That is, the transfer response signal DMAAck0 is asserted to complete the data transfer (step S11).

  In clock cycle 19, a data transfer instruction indicated by PC (1) = 0x16 is issued. However, since DMAReq1 is not asserted in clock cycle 19, pc_en becomes “101”, and PC (0), PC (2 ) Are sequentially executed (step S12).

  In clock cycle 21, execution of the instruction indicated by PC (1) is suppressed, and a data transfer instruction indicated by PC (0) = 0x05 is issued. However, in this clock cycle 21, DMAReq0 has already been asserted. The data transfer instruction is immediately executed and DMAAck0 is asserted (step S13).

  In clock cycle 23, when DAMReq1 is asserted (step S14), pc_en returns from “101” to “111”.

  In clock cycle 24, the data transfer instruction is executed and DMAAck1 is asserted (step S15).

  If the data transfer request rate of the DMA devices 1-1 and 1-2 is 2 cycles by the above-described operation, data transfer at every clock cycle may be possible if two program counters are enabled. Easy to understand. That is, while the circuits of the instruction decode unit 6 and the data transfer execution unit 7 are made common to the DMA devices 1-1 and 1-2, the data transfer requested from the DMA devices 1-1 and 1-2 is interleaved. Therefore, efficient data transfer is possible without increasing the circuit scale.

  In addition, since the memory address generation patterns of the two DMA devices 1-1 and 1-2 can be set to completely different ones, very flexible data transfer is possible. For example, if one program counter refers to image data in the x direction and the other program counter refers to image data in the y direction, it is possible to perform image rotation operations while performing image data processing. is there.

  As described above, according to the present embodiment, it is possible to previously program different access patterns for each data transfer request from a plurality of DMA devices, and a plurality of data transfers can be performed according to each data transfer request. It is possible to execute in parallel. This eliminates the need for a CPU to switch the setting for each access pattern when executing complex data transfer as in the prior art, and increases the circuit scale of complex DMA transfer with high functionality and high performance. Can be realized without any problem.

  Even for data transfer requests from the same consecutive DMA device, the access pattern can be changed in the middle without requiring the intervention of the CPU. As a result, the performance of the entire data processing device including the DMA device can be improved.

[Second Embodiment]
FIG. 16 is a block diagram showing an electrical configuration when a JPEG (Joint Photographic Experts Group) encoder module is connected as a DMA device to a DMA device as a data transfer device according to the second embodiment of the present invention. .

  In FIG. 16, the present embodiment is different from the first embodiment described above in that a JPEG encoder module 12 is connected as a DMA device to the data transfer execution unit 7 of the DMA device, and a storage 13 is stored in the CPU bus 14. Is different in that they are connected. Since the other elements of the present embodiment are the same as the corresponding ones of the first embodiment (FIG. 1) described above, description thereof is omitted.

  The DMA port 7-1 of the data transfer execution unit 7 is connected to the input unit of the JPEG encoder module 12, and the DMA port 7-2 of the data transfer execution unit 7 is connected to the output unit of the JPEG encoder module 12. Yes. A memory-mapped storage 13 is connected to the CPU bus 14. Data compressed by JPEG by the JPEG encoder module 12 can be stored in the storage 13.

  In the above configuration, the program counter PC (0) (3-1) executes a sequence for reading out image data from the memory 2 and inputting it to the JPEG encoder module 12. The JPEG encoder module 12 performs JPEG compression on the input image data, generates compressed code data having a data rate different from the data rate of the image data, and asserts a data transfer request.

  The program counter PC (1) (3-2) is activated in response to the data transfer request. The program counter PC (1) transfers the code data to the memory 2. Since the access speed of the storage 13 is slower than the access speed of the memory 2, the sequence controlled by the program counter PC (2) (3-3) transfers the code data to the storage 13 in the background.

  In such an operation, the program counter PC (0) loads and accesses the image data on the memory 2 in units of 8 × 8 blocks. The program counter PC (1) stores and accesses the code data at continuous addresses. The program counter PC (2) loads and accesses the code data from the continuous address, and stores and accesses the fixed address that is the data port of the storage.

  Through the above-described operation, three types of data transfer having different data rates and access patterns can be executed in parallel according to the respective data transfer requests. Furthermore, since the instruction decode unit 6 and the data transfer execution unit 7 can be operated in a time-sharing manner, efficient data transfer and data transfer with a complicated access pattern can be realized with a relatively small circuit scale. It becomes.

  As described above, according to the present embodiment, it is possible to realize complex DMA transfer with high functionality and high performance without increasing the circuit scale, as in the first embodiment described above. In addition, the performance of the entire system including the DMA device can be improved.

[Other embodiments]
In the first and second embodiments described above, the configuration in which the two DMA devices 1-1 and 1-2 are connected to the data transfer execution unit 7 of the DMA device has been described. However, the present invention is limited to this. Instead, a configuration may be adopted in which three or more DMA devices are connected to the data transfer execution unit 7 by increasing the number of DMA ports of the data transfer execution unit 7.

  In the first and second embodiments, the data processing device including the DMA device, the DMA devices 1-1 and 1-2, the memory 2, and the CPU 11 has been described. However, the present invention applies only to the data processing device. However, the present invention is not limited to the above-described application, and can be applied to various image processing apparatuses (printers, copiers, multifunction peripherals, facsimiles, etc.) equipped with a data processing apparatus.

1 is a block diagram showing an electrical configuration of a DMA device as a data transfer device according to a first embodiment of the present invention. It is a block diagram which shows the actual structure and input / output port of the instruction memory used in a DMA apparatus. It is a block diagram which shows the detailed structure of a program counter, a program counter selection part, and a program counter update part. It is a block diagram which shows the detailed structure of a program counter selection signal production | generation part. It is a figure which shows the relationship between the stall which is an input, and the program counter selection signal which is an output with respect to a program counter selection permission signal. It is a figure which shows the command decoded by the command decoding part. It is a figure which shows the meaning of a data size field. It is a figure which shows the meaning of an internal resource identifier. It is a figure which shows the relationship between a data size field, a byte lane field, and an effective byte lane. FIG. 10 is a diagram showing a continuation of FIG. 9. It is a figure which shows the encoding of a special instruction. It is a block diagram which shows the detailed structure of an execution suppression and selection permission signal production | generation part. It is a timing chart which shows the whole operation | movement of a DMA apparatus. It is a flowchart which shows the whole operation | movement of a DMA apparatus. It is a continuation of the flowchart of FIG. It is a block diagram which shows an electrical structure at the time of connecting a JPEG encoder module as a DMA device to the DMA apparatus as a data transfer apparatus concerning the 2nd Embodiment of this invention.

Explanation of symbols

1-1, 1-2 DMA devices (devices supported)
2 Memory (compatible with memory)
3-1, 3-2, 3-3 Program counter (corresponding to address storage means)
4 Program counter selection part (corresponding to the selection means)
5 Instruction memory (corresponding to instruction storage means)
6 Instruction decode unit (corresponds to decoding means)
7 Data transfer execution unit (corresponding to execution means)
7-1, 7-2 DMA port (corresponding to communication means)
7-3 Bus interface (corresponding to communication means)
8 Execution suppression / selection permission signal generator (corresponding to execution suppression means)
9 Program counter selection signal generator (corresponding to selection control means)
10 Program counter update unit (corresponding to update means)
11 CPU (corresponding to control means)
12 JPEG encoder module (supports encoder module)

Claims (14)

A plurality of program counters holding addresses storing instructions ;
Selecting means for selecting one of the plurality of program counters ;
Instruction storage means for storing a plurality of instructions including a data transfer instruction and outputting an instruction stored in an address of a program counter selected by the selection means;
Execution means for executing data transfer between the device and the memory according to the instruction output from the instruction storage means;
The selection of the program counter corresponding to the data transfer instruction of the device without the data transfer request when the data transfer request is not output from the device subject to the data transfer by the data transfer instruction output by the instruction storage means By suppressing the selection by the means, the execution of the data transfer instruction by the execution means is suspended, and an instruction indicated by an address held by a program counter other than the program counter holding the data transfer instruction is given to the execution means A direct memory access device comprising: an execution control means for executing. Selection indicating which program counter should be selected in response to the notification indicating the program counter storing the address of the instruction whose execution is suspended from the execution control means and the data transfer execution notification from the execution means Selection control means for outputting a signal to the selection means;
Update means for updating the stored value of the program counter corresponding to the instruction that started the data transfer for each data transfer execution notification from the execution means;
The execution control means sends an execution suppression signal for suppressing data transfer by the execution means when a data transfer request is not output from a device subject to data transfer by the data transfer instruction output by the instruction storage means. The selection control signal is output to the execution means and the selection permission signal for deselecting the program counter holding the data transfer instruction until a data transfer request is output from the device subject to data transfer by the data transfer instruction. 2. The direct memory access device according to claim 1, wherein the direct memory access device outputs the data to a means. The direct memory access apparatus according to claim 1, wherein the execution unit includes a plurality of communication units that respectively perform data transfer with the plurality of devices and the memory. The instructions stored in said instruction storage means, the data transfer instruction from said memory to internal resources of the direct memory access device, the data transfer instruction from the internal resources of the direct memory access device to the memory, the specific program counter 4. The direct memory access device according to claim 1, further comprising an instruction for enabling and an instruction for invalidating a specific program counter . 5. The device according to claim 1, wherein the device includes an encoder module that compresses image data to generate code data having a data rate different from a data rate of the image data. 6. Direct memory access device. The instruction storage means has a loop instruction for executing a data transfer instruction a plurality of times as an instruction to be executed by the execution means, and the execution means executes a data transfer instruction related to the loop instruction a plurality of times. The direct memory access device according to any one of claims 1 to 5. It said instruction storage means, said execution and store instructions to transfer data by the direct memory access said execution means from the apparatus to the direct memory access device outside the memory, from the direct memory access device external memory to said direct memory access device 7. The direct memory access device according to claim 1, further comprising a load instruction for transferring data by the means. Detecting means for detecting a request for data transfer from the device;
Determination means for determining whether a device related to an instruction output by the instruction storage means matches a device related to data transfer detected by the detection means;
The execution control unit outputs the instruction storage unit when the determination unit determines that the device related to the instruction output from the instruction storage unit matches the device related to the data transfer detected by the detection unit. The instruction storage means by the execution means is executed when it is determined that the device related to the instruction output from the instruction storage means does not match the device related to the data transfer detected by the detection means. pending execution of the output commands, and controls so as to execute the instruction indicated by the address held in another program counter to the execution unit and the program counter for holding an address for the instruction that the hold The direct memory access device according to claim 1. When the execution control means receives a data transfer request from a device related to a data transfer instruction that is suspended by the execution means, the execution control means causes the execution means to execute the data transfer instruction that is suspended. direct memory access apparatus according to any one of claims 1 to 8, characterized. Said program counter, a program counter for holding a value indicative of an address, if the instruction indicated by the address held in said program counter and executing said execution means, said program counter by one the value indicating the address direct memory access apparatus according to any one of claims 1 to 9, characterized in that increasing. It said selecting means, direct memory access device according to any one of claims 1 to 10, characterized in that switch the program counter to choose for each clock cycle. A decryption means,
The instruction storage means outputs a signal indicating an instruction, and the decoding means decodes an instruction to be executed by the execution means based on a signal output from the instruction storage means, and executes the decoded instruction to the execution means direct memory access apparatus according to any one of claims 1 to 11, characterized in that to. A data processing comprising: the direct memory access device according to any one of claims 1 to 12, the device, the memory, and a control unit that controls an operation of the direct memory access device. apparatus. Direct memory access having a plurality of program counters holding addresses storing instructions, a selection means for selecting one of the program counters, and an instruction storage means for storing a plurality of instructions including a data transfer instruction An apparatus control method comprising:
A selection step of selecting one of the plurality of program counters ;
An instruction output step for outputting the instruction stored in the address of the program counter selected in the selection step by the instruction storage means;
An execution step of performing data transfer between the device and the memory in accordance with the instruction output in the instruction output step;
A program corresponding to a data transfer instruction of a device having no data transfer request when a data transfer request is not output from the device as the data transfer source or data transfer destination indicated by the data transfer instruction output in the instruction output step The execution of the data transfer instruction is suspended by suppressing the selection by the selection means of the counter , and the instruction indicated by the address held by the program counter other than the program counter holding the data transfer instruction is executed by the execution step. An execution control step for executing the direct memory access apparatus.

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