JPH10177541A - Data transfer device and system therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To arbitrate plural I/O ports with small capacity of hardware and to perform the transfer of data with high efficiency by using an address counter, a data counter and a stream data transfer means in common to plural ports. SOLUTION: An address counter 22a is used in common to (n) ports and stores the head address of a memory area to which the stream data are transferred with DMA. A data counter 22b stores the size of the stream data, and (n) chain address counters 22c store the addresses of a command list. In the command list shown by the addresses stored in the counters 22c, the head address and the data size are corresponding to the contents of the counters 22a and 22b respectively. Then a data transfer device performs the DMA transfer of stream data of the stored size between the port corresponding to a specific chain address counter and the memory area that is shown by the stored head address.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer apparatus and a data transfer system capable of arbitrating data transfer competition for a plurality of I / O ports (input / output ports). A data transfer device and a data transfer device for transferring, by DMA (Direct Memory Access), stream data partitioned by a certain amount between an I / O port and a storage area allocated to the I / O port, respectively. About the system.

[0002]

2. Description of the Related Art A data transfer system for inputting and outputting stream data, which is continuous information such as video data, to a plurality of users is provided for each user based on a stream data transfer request with a specified user. Perform a demand-type service that transfers the specified stream data.

[0003] Such a data transfer system has a large-capacity storage device such as an HDD (hard disk drive) or an optical disk device for storing a large amount of stream data. From the stream data stored in this mass storage device, stream data specified for each user is extracted and transferred to each user through a channel, or stream data transferred from each user through a channel is It is stored in this mass storage device. Here, the channel refers to an I / O port for transferring data, which is assigned to each user.

FIG. 22 is a diagram schematically showing a conventional data transfer system. This device has a CPU 10, a memory 1
1, system bus 12, SCSI interface 1
3, HDD 14a, HDD 14b, HDD 14c, HD
D14d, a stream interface 50a, a stream interface 50b, a stream interface 50c, and a stream interface 50d. As an external device, a video monitor 1
6a, video monitor 16b, video monitor 16c and video cassette recorder 17 are shown on the same figure.

[0005] The CPU 10 creates a command or the like necessary for transferring the specified stream data based on the request for transferring the stream data with each user and stores the command or the like in the memory 11. SCS
The data is transferred to the I interface 13 and the stream interface 50a, 50b, 50c or 50d.

[0006] The memory 11 stores commands and the like created by the CPU 10, and temporarily stores stream data when stream data is transferred. The system bus 12 includes a CPU 10, a memory 11, an S
It is connected to the CSI interface 13, the stream interface 50a, the stream interface 50b, the stream interface 50c, and the stream interface 50d, and is used when transferring stream data or commands between the connected parts. The system bus 12 includes:
For example, PCI (Periph) which is a local bus standard
eral Component Intercone
ct) The bus is used. This PCI bus has a bus width of 32 bits or 64 bits and an operating frequency of 33M.
Hz. For example, when the bus width is 32 bits and the operating frequency is 33 MHz, a data transfer performance of 133 MB / s is possible.

The SCSI interface 13 includes a system bus 12, HDD 14a, HDD 14b, HDD 14
c and the HDD 14d, and the CPU 10 transfers commands and the like necessary for transferring stream data. Based on the commands, the stream data is transferred between the memory 11 connected via the system bus 12 and each HDD. To transfer.

HDD 14a, HDD 14b, HDD 14
c and the HDD 14d store stream data.
The stream interface 50a is connected to the system bus 1
2 and the video monitor 16a. The stream interface 50b is connected to the system bus 12 and the video monitor 16b.

The stream interface 50c is connected to the system bus 12 and the video monitor 16c. The stream interface 50d is connected to the system bus 12 and the video cassette recorder 17. Each stream interface receives commands and the like necessary for transferring stream data by the CPU 10, and transfers stream data between the memory 11 connected via the system bus 12 and each external device based on the commands. I do. In addition, for connection between each stream interface and each external device, for example, IEEE1394 which is a standard of serial digital transmission is used.
In the IEEE 1394 standard, transmission of about 100 Mbps at the maximum is possible, so that video information of about 30 Mbps can be transmitted with a sufficient margin.

Further, DMA transfer is generally used for data transfer performed by the SCSI interface 13 and each stream interface. An example of the conventional DMA transfer is disclosed in Japanese Patent Application Laid-Open No. 5-151146 (DMA transfer method). In this conventional technique, a plurality of DMA transfers can be executed only once by the CPU once by providing a means for following the address of the next transfer source and the byte length of the data to be transferred. Such chained DMA transfer is suitable for continuously transferring stream data having a high bit rate and a large data amount such as video data.

The DMA transfer between the memory and the input / output device managed by the virtual storage system is disclosed in, for example, Japanese Utility Model Laid-Open No. 3-54058 (DMA control circuit). In this conventional technique, by executing a chained DMA transfer, data stored in a memory managed by a virtual storage method can be continuously transferred.

Further, DMA transfer between a plurality of input / output devices and a memory is disclosed in, for example, Japanese Patent Laid-Open No. 6-250.
No. 965 (input / output control device). In this conventional technique, processing efficiency is improved by holding a plurality of commands and statuses. Furthermore, a plurality of input / output devices and a DRAM (Dynamic R)
DMA to a memory constituted by an AM device)
The transfer is disclosed in, for example, Japanese Patent Application Laid-Open No. 5-334232 (DMA transfer control device). In this prior art, by setting the number of accesses per one time in advance, the transfer amount between input / output devices is eliminated,
In addition, the frequency of memory access in the high-speed access mode of the DRAM is increased, and the efficiency of data transfer is improved.

The data transfer of such a conventional data transfer system has the following features. First, HD
In data transfer between D and the memory or between the memory and the stream interface, continuously stored stream data is read out in block units each having a certain size. By doing so, data can be read efficiently, the amount of data per process generated for each read is increased, and the total data transfer rate is increased. Therefore, the occupation time of the system bus can be shortened, and the system bus can be used effectively. Here, the data transfer rate is a value indicating the amount of data transferred per unit time. For example, a data transfer rate of an HDD having an interface of the Fast Wide SCSI standard is 20 M
B / s.

Second, the data transfer rate of one channel is lower than the data transfer rate between the HDD and the memory or between the memory and the stream interface. For example, the data transfer rate of video information compressed according to the MPEG1 standard is 1.5 Mbps (= 0.18
75 MB / s). In addition, even if the compressed video information has a higher image quality, the data transfer rate is 30 Mb.
It is about ps (= 3.75 MB / s).

Therefore, one data transfer system can simultaneously transfer a plurality of pieces of video information. It should be noted that such video information is usually composed of 30 frames per second, and is managed in frame units. A frame pulse is used to indicate such a frame break.

However, according to the above-mentioned prior art, since there is no coordination between data transfer for each I / O port, it is possible to guarantee real-time performance of each stream data output to a plurality of I / O ports. Can not.
In particular, when outputting a plurality of pieces of video information, there is a problem that the video information is interrupted for a certain period of time and the video is disturbed.

[0017]

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of such a problem, and a plurality of I / O ports are provided so that each stream data output to a plurality of I / O ports is not interrupted for a certain period of time. An object of the present invention is to provide a data transfer device and a data transfer system that can arbitrate an O port and perform data transfer efficiently.

[0018]

In order to achieve the above object, a data transfer device according to the present invention is a data transfer device that DMA-transfers stream data between n ports and a memory, respectively. n is an integer of 2 or more;
At least one set of command lists is stored in the memory in advance, and a memory area for storing stream data is secured, and the command list is stored as a head address of a memory area for storing stream data. N including the stream data size and a command indicating whether to change the port to be selected next,
An address counter for storing the start address of a memory area to which the stream data is DMA-transferred next to one of the n ports, which is also used for the n ports;
a data counter for storing the size of stream data to be DMA-transferred between the memory area indicated by the start address stored in the address counter and shared with the n ports and one of the n ports; An n number of chain address counters each of which corresponds to one port and stores an address of a memory in which a specific command list is stored, and an address stored in the specific chain address counter. In the command list, the head address of the memory area included in the command list corresponds to the content of the address counter, the size of the stream data included in the command list corresponds to the content of the data counter, and the data transfer device And a port for selecting one port from the n ports Selecting means, and each time one port is selected by the port selecting means, obtains a command list indicated by an address stored in a chain address counter corresponding to the one port selected by the port selecting means. The head address of the memory area included in the command list is transferred to the address counter, the size of the stream data included in the command list is transferred to the data counter, and the command included in the command list is passed to the port selection means. A command list transfer unit for updating an address stored in the chain address counter to a next address; and a memory area indicated by the one port selected by the port selection unit and a head address stored in the address counter. Between the data stored in the data counter Stream data transfer means for DMA-transferring the stream data of the stream, and the port selecting means determines a predetermined order and a command passed to the command list transfer means when the DMA transfer is completed by the stream data transfer means. The port in the next order is newly selected or the port selected just before is selected again based on the above, and the stream data transfer unit transfers the size of the stream data to the data counter by the command list transfer unit. Each time DMA transfer of the stream data of the size stored in the data counter is performed between one port selected by the port selection means and the memory area indicated by the head address stored in the address counter.

According to this configuration, since a plurality of I / O ports can be arbitrated, a plurality of stream data can be efficiently transferred. Further, transfer to a plurality of input / output devices can be realized with a relatively small amount of hardware, and expansion is easy. Further, the plurality of stream data may be asynchronous, and the DMA transfer may be equally assigned to each asynchronous port.
DMA transfers can also be assigned to specific ports at specific rates.

Also, stream data can be transferred without being affected by the transfer status of the other ports. Therefore, the data of each port is distributed on the system bus in units of burst transfer, and the data transfer of the multi-port multi-device can be efficiently executed as the whole system. In particular, the bus conversion function of the two buffer units enables more efficient overall data transfer on the system bus while reducing the amount of hardware.

Furthermore, it is possible to cope with an input / output port of m-times speed by adding a small amount of wiring on the port side, and the software can be made almost the same, so that the system is very easy to use.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 <Overall Configuration> FIG. 1 is a diagram schematically showing a data transfer system according to an embodiment of the present invention. This system is
Stream interface 50a, stream interface 50b, stream interface 50c
2 except that a multi-stream interface 15 is provided in place of the stream interface 50d.
2 has basically the same configuration as the conventional data transfer system. Therefore, the description of the common parts will be omitted, and the description will focus on the multi-stream interface 15.

The port 41a, the port 41b, the port 41c, and the port 41d are connection parts with each external device. Here, a case will be described in which stream data is transferred from this system to an external device based on a stream data transfer request to each user. HDD14
a, stream data is stored in advance in the HDD 14b, the HDD 14c, or the HDD 14d.

The CPU 10 sends the specified stream data to the HDD 14a, HDD 14b,
DMA from HDD 14c or HDD 14d to memory 11
An HDD command for transfer is created, temporarily stored in the memory 11, transferred to the SCSI interface 13, and the stream data of one frame unit stored in the memory 11 is transferred from the memory 11 to the specified external device by the DMA.
An external device-specific command and a command list for transfer are created and stored in the memory 11. Further, the CPU 10
Is that one frame unit of stream data is transmitted by the SCSI interface 13 to the HDDs 14a, 14b,
DMA from HDD 14c or HDD 14d to memory 11
When transferred, the multi-stream interface 15
Then, the external device-specific command is transferred from the memory 11 to the multi-stream interface 15 after the preparation of the command is completed.

Further, if the stream data requested to be transferred has not been transferred to all frames, the CPU 10
The above operation is repeatedly executed, and each time the next 1-frame unit of stream data is DMA-transferred to the memory 11 by the SCSI interface 13, the multi-stream interface 15 outputs the 1-frame unit of stream data to the external device specified from the memory 11. After the preparation for the DMA transfer to the internal buffer corresponding to the above is completed, the external device-specific command for the DMA transfer of the next stream data of one frame unit is transferred from the memory 11 to the multi-stream interface 15.

The CPU 10 provides, for each connected external device,
Perform the above operations in parallel. The detailed configuration of the command list and the multi-stream interface 15 will be described later. Note that the transfer of stream data from an external device to this device is easily realized only by reversing the data transfer direction and procedure.

<Detailed Configuration of Buffer Area Secured in Memory 11> FIG. 2 is a diagram showing a buffer area secured in the memory 11 in which stream data is temporarily stored. The stream data A61a, the stream data B61b, and the stream data C61c indicate stream data that has been DMA-transferred. Note that all stream data is assumed to be continuous before being transferred to the memory 11.

A start address A62a, a start address B62b, and a start address C62c indicate a start address of each stream data. Data size A
63a, data size B63b and data size C63
c indicates the size of each stream data. here,
OS of multitask multiuser such as UNIX as OS
It is assumed that S is used. Normally, under the management of such an OS, the memory 11 is virtual storage managed in page units,
The size of one page is 4 KB, and the storage area is a discrete area divided every 4 KB. In the case of a byte address, the lower 12 bits of the start address have the value 0, and the upper 20 bits represent the page address.
When the entire page is used, the data size is 4096 bytes (all 12 bits have a value of 1).

<Detailed Configuration of Command List> FIG. 3 is a diagram showing a configuration of a command list stored in the memory 11. Here, the command list is stored in the memory in a list format. A command list in which a plurality of command lists are arranged in order as shown in FIG. 3 is called a chain list.

Here, the command list A64a includes a start address A65a, a data size A67a, and a DM address.
A command bit A66a, the command list B64b similarly includes a start address B65b, a data size B67b, and a DMA command bit B66b, and the command list C64c includes a start address C6.
5c, a data size C67c and a DMA command bit C66c.

The start address A65a, start address B65b, and start address C65c indicate the start address of the buffer area secured in the memory 11 to which the stream data is DMA-transferred. The data size A67a, the data size B67b, and the data size C67c indicate the size of stream data to be DMA-transferred.

DMA command bit A66a, DMA command bit B66b and DMA command bit C66
c indicates the next DMA transfer operation. FIG. 4 shows the contents of the DMA command bit. Here, the DMA command bits are the same port (same-port) 66d and the port switching (c
change-port 66e, end-of-chain 66f, and wait-for-frame-pulse.
4 illustrates four operations of 66 g.

The same port 66d indicates that another DMA transfer to the same port is performed after the completion of the DMA transfer to the corresponding port. Port switching 66e
Indicates that after completion of the DMA transfer to the corresponding port, it is determined whether or not to perform the DMA transfer to a different port. The end 66f of the chain list indicates that the chain list has ended.

The frame pulse wait 66g determines whether or not to perform a DMA transfer to a different port after the completion of the DMA transfer to the corresponding port, and further determines whether the same port receives a frame pulse until the same port receives a frame pulse. Indicates that no DMA transfer is performed. The command list address A68a, the command list address B68b, and the command list address C68c indicate the start addresses of the command list A64a, the command list B64b, and the command list C64c, respectively.

<Multi Stream Interface 15
FIG. 5 is a diagram showing a detailed configuration of the multi-stream interface 15. The multi-stream interface 15 is provided for the DMA controller 2
0, BFIFO 23, buffer controller 30, buffer 33a, buffer 33b, buffer 33c, buffer 33d, I / O controller 40a, I / O controller 40b, I / O controller 40c, and I / O controller 40d. Where 4 x port 4
2 is a port, not shown in FIG. 1, to which stream data is transferred at a speed four times faster than the other ports.
A VCR (Video Cassette Recorder) or the like to which stream data is transferred at 4 times speed compared with other external devices is connected.

The system bus 12, port 41a,
Port 41b, port 41c and 4 × port 42 are shown on the same drawing. Here, it is assumed that the port 41a, the port 41b, the port 41c, and the 4 × port 42 output a frame pulse. Also, xnmode43, F
P44a, FP44b, FP44c and FP44d are control lines.

In FIG. 5, control lines and the like other than those described above are partially omitted. The DMA controller 20 includes a bus controller 21 for controlling memory access to the system bus 12 and the like, and a DMA register 22 for holding information necessary for DMA. BFIFO 23 is a bidirectional FI
An FO memory (first-in first-out memory) for buffering data transfer between the DMA controller 20 and the buffer controller 30.

The buffer controller 30 has a BFIFO
23, buffer 33a, buffer 33b, buffer 33
c, and data transfer is performed with the buffer 33d. Further, the buffer controller 30 includes a buffer interface 31 that controls data transfer between the BFIFO 23 and the buffers 33a, 33b, 33c, and 33d, and a buffer register 32 that holds information necessary for data transfer between the buffers. .

The buffers 33a, 33b, 33c, and 33d are, for example, field memories, and buffer data transfer between the buffer controller 30 and each I / O controller.
The I / O controller 40a, the I / O controller 40b, the I / O controller 40c, and the I / O controller 40d are connected to the ports of the buffers 33a, 33b, 33c, and 33d, respectively.

The I / O controller 40a has a buffer 3
Data transfer between 3a and port 41a or 4 × port 42 is performed, and similarly, I / O controller 40b performs data transfer between buffer 33b and port 41b or 4 × port 42, and I / O controller 40c Buffer 3
3c and data transfer between the port 41c or the 4 × port 42, and the I / O controller 40d
And data transfer between the port 41d and the 4 × port 42.

The × nmode 43 is a control line for the buffer controller 30 to select the I / O controller 40a, I / O controller 40b, I / O controller 40c or I / O controller 40d. FP44
a is a control line for transmitting the frame pulse received by the I / O controller 40a from the port 41a to the DMA controller 20, and similarly, the FP 44b
The I / O controller 40b is a control line for transmitting the frame pulse received from the port 41b to the DMA controller 20, and the FP 44c transmits the frame pulse received from the port 41c by the I / O controller 40c.
The FP 44d is a control line for transmitting the frame pulse received from the port 41d by the I / O controller 40d to the DMA controller 20.

<Detailed Configuration of DMA Register 22> FIG.
FIG. 6A is a diagram showing a detailed configuration of a DMA register 22 included in the DMA controller 20 shown in FIG.
This register group includes DMA address counters 22a, D
MA data counter 22b, chain address counter 22c, chain address counter 22d, chain address counter 22e, chain address counter 22
f, a control register 22g, a control register 22h, a control register 22i, a control register 22j, and a port number register 22k.

Here, it is assumed that one or more command lists are stored in the memory 11 shown in FIG. 1 in advance, and a memory area for storing stream data is secured. DMA address counter 22a
Stores the start address of the memory area where the stream data is DMA-transferred next to one of the four ports.

The DMA data counter 22b operates between the memory area indicated by the start address stored in the DMA address counter 22a and one of the four ports.
Stores the size of stream data to be DMA-transferred. The chain address counter 22c, the chain address counter 22d, the chain address counter 22e, and the chain address counter 22f each correspond to one port, and each address of a memory in which a specific command list is stored. Store.

Here, in the command list indicated by the address stored in the specific chain address counter, the start address of the memory area included in the command list corresponds to the contents of the address counter, and the stream included in the command list is included. The size of the data corresponds to the contents of the data counter. Control register 22
g, one control register 22h, one control register 22i, and one control register 22j correspond to one port.
Indicates the state of A transfer. Here, it is assumed that the control register 22g, the control register 22h, the control register 22i, and the control register 22j correspond to the port 41a, the port 41b, the port 41c, and the port 41d, respectively.

FIG. 6B shows the control register 22.
FIG. 6 is a diagram showing a configuration of a bit field inside g.
Note that the control register 22h, the control register 22i, and the control register 22j have basically the same configuration as the control register 22g, and a description thereof will be omitted. The control register 22g stores R
UN221, DONE22m, IO22n and FP22
o.

RUN 22l indicates whether or not to start DMA transfer to the corresponding port 41a. CPU10
Is set directly when DMA transfer is started for the corresponding port 41a. Here, “1” indicates activation, and “0” indicates non-activation. DONE 22m indicates whether or not the DMA transfer to the corresponding port 41a has been completed. The DMA command bit included in the command list read during the DMA transfer to the corresponding port 41a is set when the chain list ends 66f, and one DMA transfer to the corresponding port 41a is completed. Are reset when the CPU 10 starts the DMA transfer. Here, the port 41a corresponding to “1”
Indicates that the DMA transfer to the
This indicates that the MA transfer has not been completed.

IO 22n indicates the direction of the DMA transfer to the corresponding port 41a. Here, "0" indicates that the stream data is output to the port 41a,
"1" indicates that stream data is input from the port 41a. The FP 22o indicates whether a frame pulse has been received from the corresponding port 41a. Note that the FP 22o transmits the DM to the corresponding port 41a.
A included in the command list read at the time of A transfer
The MA command bit is reset when the frame pulse wait 66g is set, and is set when a frame pulse is received from the corresponding port 41a. Here, "0"
Indicates a frame pulse waiting state, and "1" indicates a transfer waiting state.

The port number register 22k stores the number of the port to which the stream data is DMA-transferred. <Detailed Configuration of Bus Controller 21> FIG. 7 is a diagram showing a detailed configuration of the bus controller 21 included in the DMA controller 20 shown in FIG.

The bus controller 21 comprises a frame pulse receiving section 21a, a port selecting section 21b, a command list transferring section 21c, a stream data transferring section 21d, and a buffer command generating section 21e. The frame pulse receiving unit 21a receives a frame pulse for each port, and sets an FP corresponding to the port that has received the frame pulse.

The port selection unit 21b clears or does not perform any FP corresponding to the selected port based on the DMA command bit passed from the command list transfer unit 21c, Based on the DMA command bit passed to the command list transfer unit 21c and the corresponding RUN and FP are set and DONE is not set, a port in the next order is newly selected, or Re-select the previously selected port.

Each time one port is selected by the port selection unit 21b, the command list transfer unit 21c transfers the command list indicated by the start address stored in the chain address counter corresponding to the selected one port. And transfers the DMA command bit included in the command list to the port selection unit 21b, and sets the start address of the memory area included in the command list to the DMA
The data is transferred to the address counter 22a, the size of the stream data included in the command list is transferred to the DMA data counter 22b, and the start address stored in the corresponding chain address counter is updated to the next start address.

Each time the stream size of the stream data is transferred to the DMA data counter 22b by the command list transfer unit 21c, the stream data transfer unit 21d sets one of the ports selected by the port selection unit 21b and the DMA.
The stream data of the size stored in the DMA data counter 22b is transferred to the memory area indicated by the start address stored in the address counter 22a.
Forward.

Each time one port is selected by the port selection unit 21b, the buffer command generation unit 21e sets the selected port, the memory capacity of the BFIFO 23, and the DMA
Based on the size of the stream data stored in the data counter 22b, a buffer command including information on the buffer to be selected and the data length to be transferred is generated and transmitted to the buffer controller 30.

FIG. 8 is a diagram showing a configuration of an internal bit field of the buffer command 22p generated by the buffer command generator. Buffer command 22p
Is composed of a MODE 22q and a data length 22r. MODE 22q indicates the identification information of the buffer that transfers the stream data and the direction of the data transfer.

The data length 22r indicates the length of data to be transferred. <Detailed Configuration of BFIFO 23> FIG.
FIG. 3 is a diagram illustrating a detailed configuration of a FIFO 23. BFIFO
23 is a FIFO 25a, FIFO 25b, data I /
It comprises an O port 24a and a data I / O port 24b.

The Empty flags EA26a, Em26
pty flag EB26b, Full flag FA26c,
Full flags FB26d, FDA26e and FDB2
6f is shown on the figure. The FIFO 25a is used for data transfer from the DMA controller 20 to the buffer controller 30.

The FIFO 25b is used for data transfer from the buffer controller 30 to the DMA controller 20. The data I / O port 24a selects a FIFO to be connected to the DMA controller 20. Data I / O
The port 24b selects a FIFO connected to the buffer controller 30.

Empty flag EA26a and Empty
The y flag EB26b indicates that the data stored in the connected FIFO is empty. Full flag FA2
6c and the Full flag FB26d are connected FI
Indicates that the data stored in the FO is full. FD
A26e is a bus connected to the DMA controller 20.

The FDB 26f is a buffer controller 3
This is a bus connected to 0. The FIFO memory is capable of completely asynchronous input / output for all of its memory areas. As described above, the BFIFO 23 can buffer the data transfer between the DMA controller 20 and the buffer controller 30 without being aware of the direction of the data transfer by providing the FIFO memory in both directions. .

The FIFO constituting the BFIFO 23
The memory capacity of the FIFO memory 25a and the FIFO 25b is sufficient to correspond to one burst transfer (continuous data transfer) between the DMA controller 20 and the memory 11. Here, the memory capacity of each of the FIFO 25a and the FIFO 25b is 3 bits, each word being 32 bits.
Two words.

<Detailed Configuration of Buffer Interface 31> FIG. 10 shows the buffer interface 3 shown in FIG.
1 is a diagram showing a detailed configuration of FIG. Here, BFIFO
23 to buffer 33a, buffer 33b, buffer 3
Only the case where stream data is transferred to 3c or the buffer 33d will be described.

The buffer interface 31 includes a latch 35a, a latch 35b, a latch 35c, a latch 35d, and a bus width converter (BUS-width-convert).
er) 36. The buffers 33a, 33b, 33c, 33d and the buffer register 32 are shown on the same drawing.

The latch 35a, the latch 35b, and the latch 35
c and the latch 35d temporarily hold 8-bit data. Here, BF is transmitted via a 32-bit bus FDB.
The data transferred from the IFO 23 is divided into four parts of eight bits each and temporarily latched. Bus width converter 36
Selects a buffer and converts the bus width from 32 bits to 8 bits. Here, for example, by selecting the buffer 33a and sequentially transferring the four 8-bit data latched by the latches 35a, 35b, 35c and 35d, the bus width is changed from 32 bits to 8 bits.
Convert to bits.

A buffer command including information on the buffer to be selected and the length of data to be transferred is transmitted from the DMA controller 20 to the buffer controller 30 before data transfer, and the bus width converter 36 is based on the buffer command. Transfer stream data. Further, the selection of the transfer destination buffer is not necessarily performed in units of 32 bits, but may be performed in units of 8-bit data latched by each latch.

Further, the buffer 33a, the buffer 33
b, BFIFO from buffer 33c or buffer 33d
The transfer of stream data to 23 is easily realized by simply reversing the direction and procedure of data transfer, and a description thereof will be omitted. <Detailed Configuration of Buffer Register 32> FIG. 11 shows a detailed configuration of the buffer register 32 shown in FIG.

The register group includes port number registers 32a, 4 × mode 32b, in / out 32c,
in / out32d, in / out32e, in / ou
It is composed of t32f and data length 32g. The port number register 32a stores the number of the port whose stream data is subjected to bus width conversion.

The 4 × mode 32b is set only at the time of bus width conversion in the quadruple speed mode. in / out32c
Indicates the direction of data transfer to the buffer 33a,
Similarly, in / out 32d indicates the direction of data transfer to the buffer 33b, in / out 32e indicates the direction of data transfer to the buffer 33c, and in / out 32e
out32f indicates the direction of data transfer to the buffer 33d.

[0069] The data length 32g stores the data length of stream data to be subjected to bus width conversion. Each of these registers is set by the buffer command 22p shown in FIG. <Detailed Configuration of Buffer 33a, Buffer 33b, Buffer 33c, and Buffer 33d> FIG. 12 is a diagram showing a detailed configuration of the buffer 33a shown in FIG. The buffer 33b, the buffer 33c, and the buffer 33d have basically the same configuration as the buffer 33a, and a description thereof will be omitted.

Here, the field memory (Field)
-Memory) 34a is used. Note that WD34b is a data bus for writing, RD34c is a data bus for reading, and W is a data reset for writing.
RST34d, WCLK34 which is a write clock
e, read reset RRST 34f, read clock RCLK 34g, BOA 34h, BOB
34i, a gate 34j for switching the write bus, and a gate 34k for switching the read bus are shown in the figure.

The field memory can perform a first-in first-out operation almost like a FIFO memory, but cannot perform complete asynchronous input / output for all of its memory area, and perform data transfer by overlapping write and read at a fixed cycle. There must be. Here, since the data transfer of the continuous stream data is performed, the data is not interrupted, and the data transfer can be performed by overlapping the writing and the reading with the period of the frame pulse.

The field memory 34a reads data written from the WD 34b from the RD 34c. WD
In 34b, the writing position is reset for each frame by the WRST 34d, and data is written according to the WCLK 34e. The read position of the RD 34c is reset for each frame by the RRST 34f.
Data is read according to CLK34g.

The BOA 34h is a buffer controller 3
Connected to 0. The BOB 34i is connected to the I / O controller 40a. The gate 34j and the gate 34k are
Buffer controller 30 and I / O controller 40a
BOA3 to perform data transfer in both directions between
4h and BOB 34i are switched.

As described above, the buffer 33a determines the direction of data transfer by switching the bus, and buffers the data transfer of the continuous stream data between the buffer controller 30 and the I / O controller 40a. It can be carried out. The buffer 33a
Is sufficient for the memory capacity of the field memory 34a for several (2 to 3) frames. Here, the memory capacity of the field memory 34a is 250 Kbytes for two frames.

<Detailed Configuration of FP44a, FP44b, FP44c and FP44d> FIG. 13 is a diagram showing the control line FP44a shown in FIG. FP44b, FP4
4c and the FP 44d have basically the same configuration as the FP 44a, and a description thereof will be omitted. I / O controller 4
0a from the port 41a is transmitted to the DMA controller 20 via the control line FP44a.
And the FP 22o shown in FIG. 6B is set. <Operation> First, in the system shown in FIG.
4a, the operation when the stream data stored in the HDD 14b, the HDD 14c and the HDD 14d is output via the multi-stream interface 15 will be described.

<Operation of CPU 10> FIG. 14 is a diagram showing a flow of a process of transferring stream data in the CPU 10 when the data transfer system according to the present invention is used. The operation will be described below. 1. A transfer request for certain stream data is generated from a certain user (step S1).

2. HDD 14a, HDD 14b, HDD 1
4c or an HDD command for DMA transfer from the HDD 14d to the memory 11 is created and temporarily stored in the memory 11 (step S2). 3. It waits until the SCSI interface 13 can receive the HDD command (step S3).

4. The HDD command created in step S2 is transferred from the memory 11 to the SCSI interface 13 (step S4). 5. The stream data of one frame unit stored in the memory 11 is transmitted from the memory 11 to the specified external device by the DM.
A command for each external device for A transfer and a command list are created and stored in the memory 11 (step S5).

6. The SCSI interface 13 converts one frame unit of stream data into the HDD 14
a, waiting for DMA transfer from the HDD 14b, HDD 14c or HDD 14d to the memory 11 (step S
6). 7. It waits until the multi-stream interface 15 can receive the command for each external device (step S7).

8. The external device-specific command created in step S5 is transferred from the memory 11 to the multi-stream interface 15 (step S8). 9. It is determined whether or not the transfer-requested stream data has been transferred to all frames. If it is determined that all frames have been transferred, the operation is terminated. If it is determined that all frames have not been transferred yet, the process proceeds to step S2. The process returns to the creation of the HDD command (step S9).

The CPU 10 provides, for each connected external device,
Perform the above operations in parallel. Here, the buffer area secured in the memory 11 is indicated by a logical address in the user space, but is indicated by a physical address during data transfer. Therefore, at the time of data transfer, a command list is created based on a state in which the logical address of the buffer area is converted into a physical address and is separated for each data size of 4 KB.

Normally, the data size of the DMA transfer included in the command list is 4 KB for one page, but there is a case where a data size of 4 KB cannot be secured. For example, one frame of stream data is 10, 0
In the case of 00 bytes, since it is divided into three parts of 4096 bytes, 4096 bytes and 1808 bytes, the last 1
808 bytes cannot secure a data size of 4 KB.

Here, this buffer area is an area locked to the OS so as not to be paged out. <Operation of SCSI Interface 13> The SCSI interface 13 transmits the stream data specified by the CPU 10 to the HDD 14a,
A command for DMA transfer from the HDD 14b, HDD 14c or HDD 14d to the memory 11 is transferred, and one frame unit of the stream data is DMA-transferred from the HDD 14a, HDD 14b, HDD 14c or HDD 14d to the memory 11 based on this command. Since the detailed operation of the SCSI interface 13 is the same as that of the conventional DMA transfer device, the description is omitted.

<Multi-Stream Interface 15
Operation> The multi-stream interface 15
The PU 10 transfers a command for DMA transfer of the stream data of one frame unit stored in the memory 11 from the memory 11 to the specified external device and an address of the command list, and based on the command and the address of the command list. The command list stored in the memory 11 is read out, and one frame unit of the stream data is stored in the memory 11 based on the command list.
DMA transfer to the specified external device. The detailed operation of the multi-stream interface 15 will be described later.

Next, a method of managing a buffer in units of frames and a method of managing a buffer area in the memory 11 by a double buffer method, which are used in the above-described DMA transfer, will be described. <Method of Managing Buffer in Frame Unit and Method of Managing Buffer Area in Memory 11 by Double Buffer Method> Video data is composed of a plurality of continuous frames.
Usually, 30 frames correspond to 1 second image. For example, 3
In the case of video data with a data rate of 0 Mbps,
The data size per frame is 125 KB.

The method of managing the buffer in units of frames is to temporarily store one frame of stream data in the buffer area in the memory 11 and transfer this one frame to the multi-stream interface 15.
The method of managing the buffer area in the memory 11 by the double buffer method is to use one of the double buffers in the SCSI interface 1 every cycle of one frame.
3 is used, and the other buffer is used by the multi-stream interface 15, and the processing of the two interfaces can be executed in parallel.

The input of stream data from each port can be easily realized simply by reversing the direction and procedure of data transfer from the output. The stream data taken in from each port is temporarily stored in a buffer area on the memory 11 by the multi-stream interface 15, and is stored in the HDD 14 a, the HDD 14 b, the HDD 14 c or the HDD 14 by the SCSI interface 13.
14d.

Next, the data transfer operation on the system bus 12 will be described. <Operation of Data Transfer in System Bus 12> When, for example, a PCI local bus is used as the system bus 12, memory addresses and data are multiplexed. Therefore, an address is first output on the system bus 12 to specify the location of the memory 11. Data is output following the output of this address, and a plurality of data are sequentially transferred from the location of the memory 11 specified by this address. Such data transfer is called burst transfer. That is, in one burst transfer, it is determined that the head is an address and the rest is data. Therefore, the address at this time is only the head value, and during one bus transaction, it is possible to transfer data from the head value of the address to a continuous address. The length of one burst transfer is, for example, in the case of a PCI local bus, smaller than a value specified by a latency timer specific to a device on the PCI local bus. Here, the capacity of the BFIFO 23 is assumed. Also,
In one burst transfer transaction on the PCI local bus, the device which becomes the bus master issues a bus request (R
EQ) is output, and access is started after the bus use permission (GNT) is returned.

In the normal burst transfer of stream data, for example, when one frame is 125 KB, the area of 125 KB is not DMA-transferred sequentially, but is divided into several to several tens of continuous data units. It is executed in a delimited manner. By doing so, a large number of devices (CPU 10, memory 11, SCSI
Even if the interface 13 or the multi-stream interface 15 is connected, the burst transfer is performed while sequentially assigning the right to use the system bus 12 to the device that has issued the bus request REQ to the system bus 12, thereby efficiently performing the burst transfer. Data transfer can be performed using the system bus 12. This is performed regardless of the input and output of the stream data.

<Multi-stream interface 15
<Detailed Operation of Bus Controller> FIG. 15 is a diagram showing a flow of a process of transferring stream data in the bus controller 21 when the data transfer system according to the present invention is used. Hereinafter, FIG. 1, FIG. 2, FIG. 3, FIG.
The operation will be described with reference to FIGS. 5, 6A, 6B, 8 and 11.

Here, the stream data shown in FIG. 2 and the chain list shown in FIG. 3 are stored in the memory 11 in advance, and the DONE 22m, which is the content of the control register 22g corresponding to the port 41a, is "1". At this time, the command list address A68a of the command list A64a shown in FIG. 3 is transferred to the chain address counter 22c by the CPU 10, and "1" is added to the RUN 221 as the contents of the control register 22g, and D
"0" for ONE22m, "0" for IO22n and FP2
It is assumed that “0” is transferred to 2o.

1. Initialize the port number pn.
The port number pn is a number where 0, 1, 2 and 3 respectively correspond to the port 41a, the port 41b, the port 41c and the port 41d. Here, "0" is substituted as an initial value (step S11). ). 2. The contents of the control register of the port corresponding to the port number pn are RUN = 1, DONE = 0 and FP =
It is determined whether it is 1. Here, RUN = 1 indicates that DMA transfer is started for the corresponding port,
DONE = 0 indicates that DMA transfer to the corresponding port has not been completed, and FP = 1 indicates that a frame pulse has been received from the corresponding port.
When it is determined that none of the conditions is satisfied, the port number pn is incremented. When it is determined that all the conditions are satisfied, the DMA transfer is performed (step S12).

3. If it is determined that at least one of the conditions is not satisfied, the port number pn is used to determine the next port.
Is incremented (step S13). 4. If the port number pn is larger than the maximum port number, the process goes to the initial setting of the port number pn. Here, if it is larger than the maximum port number "3", the process goes to step S11 by substituting the initial value "0", and if not larger than the maximum port number "3", the control register is judged and the process proceeds to step S12. Go to (Step S14).

5. If it is determined in step S12 that all the conditions are satisfied, the command list indicated by the command list address stored in the chain address counter of the port corresponding to the port number pn is obtained, and the start address included in the command list is obtained. The command list is transferred to the DMA address counter, the size of the stream data included in the command list is transferred to the DMA data counter, and the command list address stored in the chain address counter is updated to the next command list address.

Here, for example, if it is determined that all the conditions are satisfied, the command list A64a indicated by the command list address A68a stored in the chain address counter 22c of the port 41a corresponding to the port number pn "0" is read. The acquired start address A65a included in the command list A64a is transferred to the DMA address counter 22a, the data size A67a included in the command list A64a is transferred to the DMA data counter 22b, and the chain address counter 22
c is incremented to the next command list address B68b.
(Step S15).

6. The bus controller 21 determines the port number pn, the contents of the control register of the port corresponding to the port number pn, the memory capacity of the BFIFO 23, and D
A buffer command 22p is generated based on the content of the MA data counter 22b, and the buffer command 22p is transmitted to the buffer controller 30 after the content of the data length 32g becomes "0", and stored in the DMA address counter 22a. The stream data is burst-transferred between the buffer area in the memory 11 indicated by the designated start address and the BFIFO 23, and the start address stored in the DMA address counter 22a is incremented by the amount of the burst transfer, and the DMA data counter 22b is incremented. Decrement the stored data size.
Here, for example, the port number pn “0” and the port 41 a
Of the control register 22g and the BFIFO 23
A buffer command 22p is generated based on the memory capacity of the DMA address counter 22b and transmitted to the buffer controller 30, and the DMA address counter 22
memory 11 indicated by the start address stored in a
The stream data of 32 words is burst-transferred between the buffer area and the BFIFO 23, the content of the DMA address counter 22a is incremented by 32 words, and the content of the DMA data counter 22b is decremented by 32 words (step S16).

7. It is determined whether the data size stored in the DMA data counter 22b is "0". If it is determined that the data size is "0", the process proceeds to the check of the DMA command bit. If it is determined that the data size is not "0", the burst transfer is repeated until the data size becomes "0" (step S17). 8. If the data size is determined to be “0”,
D included in the command list acquired in step S15
The value of the MA command bit is checked to determine the next DMA transfer operation in the following steps. Here, DM
The value of the A command bit A66a is checked (step S18).

9. If the value of the DMA command bit indicates the end 66f of the chain list, DONE is set, an interrupt signal is generated, and the process returns to step S13 to perform DMA transfer to another port (step S19,
Step S20). 10. If the value of the DMA command bit indicates the frame pulse wait 66g, the flow returns to step S13 to reset the FP and perform DMA transfer to another port (steps S21 and S22).

11. If the value of the DMA command bit indicates the same port 66d, the flow returns to step S15 to perform DMA transfer to the same port. If the value of the DMA command bit indicates port switching 66e, the process returns to step S13 to perform DMA transfer to another port (step S23). <Detailed Operation of Buffer Controller 30> FIG.
FIG. 9 is a diagram showing a flow of a bus conversion process of stream data in the buffer controller 30 when the data transfer system according to the present invention is used. Hereinafter, FIG. 5, FIG.
The operation will be described with reference to FIGS.

1. As shown in step S15 of FIG. 15, when the buffer interface 22 receives the buffer command 22p from the bus controller 21 (step S31), the buffer interface 31 stores the M included in the buffer command 22p.
Based on the ODE 22q, the number corresponding to the port is set in the port number register 32a, the direction of data transfer is set to in / out corresponding to the port, and the data length 22r included in the buffer command 22p is set.
Is set based on the data length (step S3).
2).

2. As shown in step S16 in FIG.
When the data is burst-transferred to the FIFO 23 and the BFI 23 stores the stream data, the buffer interface 31 starts bus conversion asynchronously with the DMA controller 20 (step S33). 3. The latches 35a, 35b, 35c, and 35d temporarily hold 8-bit data.
Here, BFIFO2 is connected via a 32-bit bus FDB.
The data transferred from No. 3 is divided into four every eight bits and temporarily latched (step S34).

4. The bus width converter 36 selects a buffer and converts the bus width from 32 bits to 8 bits. Here, for example, the buffer 33a is selected (step S3).
5) The four 8-bit data latched by the latches 35a, 35b, 35c and 35d are
By sequentially transferring, the bus width is converted from 32 bits to 8 bits (steps S36 to S3).
9).

5. When one bus width conversion is completed, the value of the data length 32g is decremented by the transferred data (step S40). 6. It is determined whether or not the value of the data length 32g is “0”. If it is determined to be "0", step S31 is executed to accept the transfer of the new buffer command 22p.
If it is determined that the value is not "0", the process proceeds to step S33 to perform bus conversion of the next 32 bits (step S41).

<Detailed operation of n-times speed input / output> Regarding the n-times speed input / output, FIG. 5 shows the connection of 4xport 42 and the connection of xnmode 43. Is the same as the DMA transfer operation. The difference is that the 4 × mode 32b in the buffer register 32 shown in FIG.
The control signal indicated by e43 is the I / O controller 40a,
I / O controller 40b, I / O controller 40c
Is transmitted to the I / O controller 40d and each port is switched to 4 × port 42.

For example, in the case of input from an external device, 4 ×
The signal from the port 42 is divided into separate I /
It is sequentially input to the O controller. Here, 4
The double speed connection has been described, but if this is connected to two ports, the speed will be twice as fast.
The speed is doubled, and the number of ports to be connected may be determined as needed.

<Simultaneous Operation of Plurality of Ports> FIG. 17 is a diagram showing processing of simultaneous operation of a plurality of ports when the DMA controller 20 according to the present invention is used. FIG. 18 is a diagram showing a chain list for DMA transfer of stream data to the port 41a.

FIG. 19 is a diagram showing a chain list for DMA-transferring stream data to the port 41b. FIG. 20 shows a case where the stream data is
It is a figure showing the chain list for A transfer. FIG.
FIG. 7 is a diagram showing a chain list for DMA-transferring stream data to a port 41d.

Hereinafter, the operation will be described with reference to FIGS. 17, 18, 19, 20, and 21. Note that memory 1
In FIG. 1, it is assumed that the chain lists of FIGS. 18, 19, 20, and 21, and the stream data indicated by these chain lists are stored in advance before the transfer of the DMA transfer command for each port.

1. D to the port 41a by the CPU 10
After the MA transfer command is transferred, the bus controller 2
1 receives the frame pulse 91a from the port 41a (time t1). 2. When the frame pulse 91a is received, the port 41a
Based on the command list AA71a, the DMA transfer A95a of 4096 bytes of stream data starting from the start address AA72a is started (time t1).
~).

3. When the DMA transfer A95a is completed, the value of the DMA command bit AA73a of the port 41a is "00", so that the start address AB72b based on the next command list AB71b of the same port 41a.
DM of stream data of 4096 bytes starting from
The A transfer A 95b is started (time t2). 4. After the CPU 10 transfers the DMA transfer command to the port 41b, the bus controller 21
1b to receive a frame pulse 92a (time t
3).

5. When the DMA transfer A 95b ends, the value of the DMA command bit AB 73b of the port 41a is "01", so that the command list B of the next port 41b is
Based on A76a, DMA transfer B96a of 4096 bytes of stream data starting from start address BA77b is started (time t4). 6. When the DMA transfer B 96a ends, the value of the DMA command bit BA 78a of the port 41b is "00", so the next command list BB 76b of the same port 41b
Starting from the start address BB77b based on
DMA transfer of stream data of 096 bytes B96
b is started (time t5).

7. When the DMA transfer B96b is completed, the value of the DMA command bit BB78b of the port 41b is "01", so that the DMA transfer of the next port is to be started. However, since the DMA transfer command has not been transferred to the ports 41c and 41d, the DMA transfer command is not transferred. Pass and port 41a
Based on the command list AC71c, the DMA transfer A95c of 1808 bytes of stream data starting from the start address AC72c is started (time t6).
~).

8. When the DMA transfer A 95c ends, the value of the DMA command bit AC73c of the port 41a is "11", so that the port 41a waits for the frame pulse A, and the command list BC76c of the next port 41b.
Starting from the start address BC77c based on
DMA transfer of stream data for 808 bytes B96
c is started (from time t7).

9. When the DMA transfer B96c is completed, the value of the DMA command bit BC78c of the port 41b is "11", so that the port 41b waits for the frame pulse B and tries to start the DMA transfer of the next port. Since the DMA transfer command has not been transferred, it is passed, the port 41a is passed because it is waiting for the frame pulse A, and the port 41b is passed because it is waiting for the frame pulse B (time t8).

10. Bus controller 21 is port 41
a to receive a frame pulse 91b (time t
9). 11. The DMA transfer A 95d is started in the same manner as the operation at (time t1) of “2.” (time t9). 12. After the CPU 10 transfers the DMA transfer command to the port 41c, the bus controller 21 receives the frame pulse 93a from the port 41c (time t).
10).

13. When the DMA transfer A95d ends,
In the same manner as the operation at (time t2) of “3.”, DM
The A transfer A 95e is started (time t11 to t11). 14． The bus controller 21 receives the frame pulse 92b from the port 41b (time t12). 15. When the DMA transfer A 95e ends, the DMA transfer B9 is performed in the same manner as the operation of “5.” (from time t4).
6d is started (from time t13).

16. When the DMA transfer B 96d ends,
In the same manner as the operation at (time t5) of “6.”, DM
The A transfer B 96e is started (time t14). 17． When the DMA transfer B 96e ends, the port 41b
Since the value of the DMA command bit BE78e is “01”, 409 starting from the start address CA82a based on the command list CA81a of the next port 41c.
The DMA transfer C97a of 6-byte stream data is started (time t15-).

18. When the DMA transfer C97a ends,
Since the value of the DMA command bit CA83a of the port 41c is “00”, the start address CB82b is determined based on the next command list CB81b of the same port 41c.
DM of stream data of 4096 bytes starting from
The A transfer C97b is started (from time t16). 19. When the DMA transfer C97b ends, the port 41c
Since the value of the DMA command bit CB83b is “01”, the DMA transfer of the next port is to be started. However, since the DMA transfer command has not been transferred, the port 41d is passed, and the command list AF71f of the port 41a is passed.
Starting from the start address AF72f based on
DMA transfer of stream data for 808 bytes A95
f is started (from time t17).

20. When the DMA transfer A95f ends,
In the same manner as the operation at (time t7) of “8.”, the DM
The A transfer B 96f is started (time t18). 21. When the DMA transfer B 96f ends, the port 41b
Since the value of the DMA command bit BF78f is “11”, the port 41b waits for the frame pulse B, and based on the command list CC81c of the next port 41c,
The DMA transfer C97c of 1808 bytes of stream data starting from the start address CC82c is started (time t19).

22. When the DMA transfer C97c ends,
Since the value of the DMA command bit CC83c of the port 41c is "11", the port 41c waits for the frame pulse C and tries to start the DMA transfer of the next port. However, the port 41d has not been transferred because the DMA transfer command has not been transferred. The port 41a is passed because it is waiting for the frame pulse A, the port 41b is passed because it is waiting for the frame pulse B, and the port 41c is passed because it is waiting for the frame pulse C (time t20).

23. After the CPU 10 transfers the DMA transfer command to the port 41d, the bus controller 21 receives the frame pulse 94a from the port 41d (time t21). 24. When receiving the frame pulse 94a, the port 41
Based on the command list DA86a of d, DMA transfer D98a of stream data of 4096 bytes starting from the start address DA87a is started (time t).
21).

25. When the DMA transfer D98a ends,
Since the value of the DMA command bit DA88a of the port 41d is “00”, the start address DB 87b is determined based on the next command list DB 86b of the same port 41d.
DM of stream data of 4096 bytes starting from
The A transfer D98b is started (time t22). 26. When the DMA transfer D98b ends, the port 41d
Since the value of the DMA command bit DB88b is "01", the DMA transfer of the next port is to be started, but the port 41a is passed because the frame pulse A is waiting, the port 41b is passed because the frame pulse B is waiting, and the port 41c is passed. Is passed because it is waiting for the frame pulse C, and starts DMA transfer D98c of 1808 bytes of stream data starting from the start address DC87c based on the command list DC86c of the next port 41d (time t23).

27. When the DMA transfer D98c ends,
Since the value of the DMA command bit DC88c of the port 41d is "11", the port 41d waits for the frame pulse D, and attempts to start the DMA transfer of the next port. Is passed because it is waiting for frame pulse B, port 41c is passed because it is waiting for frame pulse C, and port 41d is passed because it is waiting for frame pulse D (time t24).

28. The DMA transfer A 95g is started in the same manner as the operation at (time t1) of “2.” (time t25). 29. The bus controller 21 receives the frame pulse 93b from the port 41c (time t26). 30. When the DMA transfer A 95g ends, the port 41a
Since the value of the DMA command bit AG73g is "01", the DMA transfer of the next port is to be started. However, the port 41b waits for the frame pulse B and is passed, and the start is performed based on the command list CD81d of the next port 41c. The DMA transfer C97d of 4096 bytes of stream data starting from the address CD82d is started (time t27-).

31. Bus controller 21 is port 41
b to receive the frame pulse 92c (time t2
8). 32. When the DMA transfer C 97d is completed, the DMA transfer C 97d is performed in the same manner as the operation of “17.” (from time t15).
97e is started (time t29). 33. When the DMA transfer C97e ends, the port 41c
Since the value of the DMA command bit CE83e is “01”, the DMA transfer of the next port is to be started. However, since the port 41d is waiting for the frame pulse D, it is passed, and the start is performed based on the command list AH71h of the next port 41a. A DMA transfer A95h of 4096 bytes of stream data starting from the address AH72h is started (time t30).

34. When the DMA transfer A95h ends,
Similarly to the operation at (time t13) of “15.”,
The DMA transfer B 96g starts (time t31 to time t31). 35. When the DMA transfer B 96g ends, the port 41b
Since the value of the DMA command bit BG78g is “01”, it starts from the start address CF82f based on the command list CF81f of the next port 41c.
The DMA transfer C97f of the stream data of 8 bytes is started (time t32-).

36. When the DMA transfer C97f ends,
Since the value of the DMA command bit CF83f of the port 41c is "11", the port 41c waits for the frame pulse C, and tries to start the DMA transfer of the next port. Starting from the start address AI72i based on the command list AI71i of the port 41a, 180
The DMA transfer A95i of stream data for 8 bytes is started (time t33).

37. When the DMA transfer A95i ends,
Since the value of the DMA command bit AI 73i of the port 41a is "10", the port 41a ends the chain list, and starts from the start address BH77h based on the command list BH76h of the next port 41b.
DMA transfer of 96 bytes of stream data B96h
Is started (from time t34).

38. When the DMA transfer B96h ends,
Since the value of the DMA command bit BH78h of the port 41b is "01", DMA transfer of the next port is to be started, but the port 41c is passed because it is waiting for the frame pulse C, and the port 41d is passed because it is waiting for the frame pulse D. Since the port 41a ends the chain list, it is passed, and the command list BI76i of the next port 41b is passed.
Starting from the start address BI77i based on
DMA transfer of stream data for 808 bytes B96
i is started (from time t35).

39. When the DMA transfer B96i ends,
Since the value of the DMA command bit BI78i of the port 41b is "10", the port 41b ends the chain list and attempts to start DMA transfer of the next port.
Since port 41c is waiting for frame pulse C, it is passed,
Since port 41d is waiting for frame pulse D, it is passed,
40. Port 41a is passed because the chain list ends (time t36). (Time t21 to time t of “23. to 27.”
Similarly to the operation of 24), the DMA transfers D98d to D98d
Execute A transfer D98f (time t37 to time t4)
0).

41. (Time t2 of “23. to 27.”
1 to time t24), the DMA transfer C
97g-DMA transfer C97i is executed (time t41)
~ Time t44). 42. (Time t21 to time t of “23. to 27.”
Similarly to the operation of 24), the DMA transfer D98g to DM
Execute A transfer D98i (time t45 to time t4)
8).

As described above, according to the present invention, the CPU
By generating a chain list indicating information necessary for MA transfer for each port, the size of stream data transferred by one DMA transfer for each port and the number of DMA transfers continuously executed on the same port can be determined. It can be set arbitrarily. This chain list for each port is stored in the memory, and the address is transferred to the chain address counter for each port.

Here, when the data transfer request command for each port from the CPU and the frame request signal from each port are transferred to the control register for each port, the data transfer request command and the frame request signal are transferred. The chain list indicated by the address stored in the corresponding chain address counter is acquired and DMA-transferred only to the ports in order, so that the rate of data transfer between the ports can be substantially reduced without synchronization between the ports. As set.

The present invention is, of course, not limited to these embodiments. That is, the DMA of the BFIFO 23
The controller side and the buffer controller side need not have the same bit width, and the bus width of the BFIFO 23 and each buffer may be the same. Also, each buffer is
Bidirectional FIFO or DR instead of ld memory
AM may be used.

Further, the value of the DMA address counter 22a may be generated by adding the base address and the value of the DMA data counter 22b. Here, the value of the DMA data counter 22b is sequentially incremented every data transfer, but the address may be generated by adding this value to the base address. In the case of stream data having a high resolution and a high bit rate, for example, when the size of one frame is 125,000 bytes, the command list for one frame is composed of 31 entries. Will be transferred. Here, regarding one port, the DMA transfer will be performed with almost the same performance regardless of which part of the command list is being executed by the other port.

The direction of the DMA transfer is held in the control register corresponding to each port.
Since switching is performed for each MA command, BFIF
Data of a plurality of ports is not mixed in O23.

[0137]

【The invention's effect】

(Only the structure of the DMA register) As is clear from the above description, the data transfer device according to the present invention is a data transfer device that DMA-transfers stream data between n ports and a memory. Is an integer of 2 or more, at least one set of command lists is stored in the memory in advance, and a memory area for storing stream data is reserved. Each of the command lists is a memory area for storing stream data. And the size of the stream data to be stored, which is also used for the n ports and which is the start of the memory area where the next stream data is DMA-transferred to one of the n ports The address counter for storing the address is also used for the n ports and stored in the address counter. A data counter that stores the size of stream data that is DMA-transferred between the memory area indicated by the head address and one of the n ports, one for each port and one for each port And a chain address counter for storing the address of the memory in which the command list is stored. The command list indicated by the address stored in the specific chain address counter is the head address of the memory area included in the command list. Corresponds to the content of the address counter, the size of the stream data included in the command list corresponds to the content of the data counter, and the data transfer device further includes a port and the address corresponding to the specific chain address counter. Memory indicated by the start address stored in the counter Characterized in that it comprises the stream data transferring means for DMA transferring the stream data stored size to the data counter with the frequency.

As a result, the address counter, the data counter, and the stream data transfer means are shared by a plurality of ports. Therefore, a plurality of stream data can be transferred to a plurality of ports with a relatively small amount of hardware, and expansion is easy. (Addition of command list generating means) Here, the data transfer device further generates a command list, stores the command list in the memory, and stores the address of the command list in a chain address counter corresponding to a port to which stream data is DMA-transferred. It is also possible to provide a command list generating means for transferring.

As a result, a command list can be generated for each port. Therefore, D is equally assigned to each port.
MA transfers can be assigned, or DMA transfers can be assigned to specific ports at a specific rate. (Addition of port selection means and command list transfer means) Further, the data transfer device further includes a port selection means for selecting one port from the n ports, and one port by the port selection means. Every time a port is selected, a command list indicated by an address stored in a chain address counter corresponding to one port selected by the port selecting means is obtained, and a head address of a memory area included in the command list is obtained by the address counter. Command list transfer means for transferring the size of stream data included in the command list to the data counter, and updating the address stored in the chain address counter to the next address. The means is a stream by the command list transfer means. Each time the data size is transferred to the data counter, the data is stored in the data counter between one port selected by the port selection means and the memory area indicated by the head address stored in the address counter. It may also be characterized in that stream data of a different size is DMA-transferred.

As a result, ports can be sequentially selected and DMA transfer can be performed to the selected port. Therefore, a plurality of ports can be arbitrated. (Addition of Command and Limitation of Port Selection Means) Each of the command lists further includes a command indicating whether or not to change a port to be selected next, and the command list transfer means further includes: Every time one port is selected by the selection means, a command list indicated by an address stored in a chain address counter corresponding to the one port selected by the port selection means is acquired, and a command included in the command list is acquired. To the port selecting means, and the port selecting means transfers the next order based on the predetermined order and the command passed to the command list transferring means when the DMA transfer is completed by the stream data transferring means. It is important to select a new port or to reselect the previously selected port. It can also be a.

As a result, the number of consecutive DMA transfers can be set for each port. Therefore, the number of times of DMA transfer can be equally allocated to each port, or the number of times of DMA transfer can be allocated to a specific port at a specific rate. (Addition of transfer request signal) Also, at least one of the n ports outputs a transfer request signal indicating a transfer request for a fixed amount of stream data, and the data transfer device further transfers the transfer request signal for each port. There may be provided receiving means for receiving a request signal, wherein the port selecting means selects only a port for which a transfer request signal has been received by the receiving means when selecting a port.

Thus, DMA transfer can be performed only to the port that has transmitted the transfer request signal. Therefore, DMA transfer can be performed according to a transfer request for each port. (Transfer request signal is received at regular intervals) Also, at least one of the n ports outputs a transfer request signal at regular intervals, and the receiving means further outputs one port to each port. And n request bit storage means for setting a request bit when a transfer request signal is received from the corresponding port by the receiving means, wherein the command changes the next selected port. Indicates that the request bit set in the request bit storage unit corresponding to the selected port is to be cleared, and the port selection unit transmits the command passed to the command list transfer unit. Clears the request bit set in the request bit storage means corresponding to the port selected based on the above or does nothing, and selects the port Request bit in the request bit storing means corresponding to the coupling can also be characterized by selecting only port that is set.

As a result, after clearing the request bit,
DMA transfer can be performed only to the port that transmitted the transfer request signal. Accordingly, DMA transfer can be performed while synchronizing each port. (Addition of bus width conversion means) The data transfer apparatus further includes a port selected each time one port is selected by the port selection means and a size of the stream data stored in the data counter. Bus width conversion command generation means for generating a bus width conversion command based on the command and transmitting the bus width conversion command to the bus width conversion means, wherein the bus width conversion command includes information specifying the port and information specifying the data length of the stream data to be transferred. The data transfer device further includes the bus width conversion between the port and the port while converting the bus width of the port indicated by the bus width conversion command and the bus width of the memory based on the bus width conversion command. A bus width conversion unit for transferring stream data having a data length indicated by the command, wherein the bus width conversion unit is used for n ports. Is, the stream data transfer means may also be characterized by DMA transfers stream data between the bus width converting means instead of one port selected by the port selecting means.

As a result, the bus width can be changed, so that the bus width of each port does not need to match the bus width of the memory. Therefore, ports of various bus widths can be connected. Further, the bus width to each port can be reduced, the wiring is reduced, and the hardware is simplified. (Addition of First Buffer Means) Further, the data transfer apparatus further includes first buffer means for buffering stream data between the memory and the bus width conversion means, and the first buffer means is n. And the stream data transfer means may transfer the stream data to and from the first buffer means by DMA instead of the bus width conversion means.

As a result, the stream data can be buffered, so that it is possible to adjust the difference in the overall transfer rate between each port and the memory due to the difference in the bus width, the difference in the transfer rate at one time, and the like. it can. Therefore, hardware resources such as a memory and a system bus can be effectively used. (Addition of a second buffer means) Further, the data transfer device further buffers stream data between a corresponding port and the bus width conversion means, one for each port. It is also possible to provide n number of second buffer means, wherein the bus width conversion means transfers stream data to and from the second buffer means instead of the port.

As a result, stream data can be buffered, so that fluctuations in DMA transfer can be absorbed by the buffer capacity. Therefore, stable data transfer can be performed to a plurality of ports. (Addition of m-speed port and I / O controller) Further, the data transfer device further DMA-transfers stream data between the m-speed port and the memory, where m is an integer of n or less, and The apparatus further comprises a port corresponding to one of the m second buffer means, a corresponding port or an m × speed port, and a port corresponding to the corresponding second buffer means or an m × speed port. To control the input and output of stream data between
One first I / O controller and one corresponding to one of the (nm) second buffer means other than the m second buffer means, and the corresponding second buffer means And (n-m) second I / O controllers for controlling the input / output of stream data between the I / O port and the corresponding port. Buffering stream data with the I / O controller, the m-times speed port is connected to m first I / O controllers, and the n ports are respectively connected to m first I / O controllers ( (m) second I / O controllers.

Thus, an input / output port of m-times speed can be handled by adding a small amount of wiring on the port side, and the software can be made almost the same. Therefore, the system is very easy to use. (Data transfer system) A data transfer system according to the present invention is a data transfer system for DMA-transferring stream data from a large-scale storage device to n ports, where n is an integer of 2 or more, and , A memory in which an area for storing stream data is secured, and command list generating means for generating a first command list, wherein the first command list is The data transfer system further includes information specifying the stream data stored in the storage device, information specifying the address of the memory area where the stream data is stored, and information specifying the size of the stored stream data. ,
A first data transfer device that DMA-transfers stream data of a specified size from the large-scale storage device to the memory based on the first command list transferred from the command list generation unit, wherein the command list generation unit includes:
Further, the first command list is transferred to the first data transfer device, a second command list is generated and stored in the memory, and the second command list is stored as a start address of a memory area where stream data is stored. The data transfer system further includes a second data transfer device, and a command indicating whether to change a port to be selected next.
The data transfer device is used for n ports, and stream data is transferred to one of the n ports next to the DMA.
An address counter for storing the start address of the memory area to be transferred; and a DMA transfer from the memory area indicated by the start address stored in the address counter to one of the n ports, which is also used for n ports. A data counter for storing the size of the stream data to be transmitted;
And n chain address counters each storing an address of a memory in which a specific second command list is stored, each of which corresponds to one port, and which is stored in the specific chain address counter. In the second command list indicated by the address, the start address of the memory area included in the second command list corresponds to the contents of the address counter, and the size of the stream data included in the second command list corresponds to the contents of the data counter. The second data transfer device further includes: a port selection unit that selects one port from the n ports; and a port selection unit each time one port is selected by the port selection unit. The address stored in the chain address counter corresponding to the selected one port indicates Get the 2 command list its second
The head address of the memory area included in the command list is transferred to the address counter, the size of the stream data included in the second command list is transferred to the data counter, and the command included in the second command list is transferred to the port selection means. Command list transfer means for transferring the address stored in the chain address counter to the next address, and the one selected by the port selection means from the memory area indicated by the start address stored in the address counter. Stream data transfer means for DMA-transferring stream data of the size stored in the data counter to the number of ports,
The port selecting means newly selects a next-order port based on a predetermined order and a command passed to the command list transferring means when the DMA transfer is completed by the stream data transferring means, or The port selected immediately before is again selected, and the stream data transfer means performs the transfer from the memory area indicated by the head address stored in the address counter each time the size of the stream data is transferred to the data counter by the command list transfer means. The stream data of the size stored in the data counter is DMA-transferred to the one port selected by the port selection means, and the command list generation means further has the size specified by the first data transfer device. Stream data to memory D
After the MA transfer, the address of the second command list is transferred to a chain address counter corresponding to the port to which the stream data is DMA-transferred.

Further, the data transfer system according to the present invention is a data transfer system for performing DMA transfer of stream data from n ports to a large-scale storage device, where n is an integer of 2 or more, and A large-scale storage device in which an area for storing stream data is secured, a memory in which an area for storing stream data is secured, and command list generation means for generating a second command list and storing the second command list in the memory; The second command list includes a head address of a memory area in which stream data is stored, a size of the stored stream data, and a command indicating whether to change a port to be selected next, and the data transfer system And a second data transfer device, wherein the second data transfer device is also used for n ports. An address counter for storing a start address of a memory area to which stream data is to be DMA-transferred from one of the ports, and an address counter for one of the n ports which is also used for the n ports. A data counter for storing the size of stream data to be DMA-transferred to the memory area indicated by the head address stored in the address counter;
And an n number of chain address counters each storing an address of a memory in which a specific second command list is stored, and a second command list indicated by the address stored in the specific chain address counter. Indicates that the start address of the memory area included in the second command list corresponds to the contents of the address counter, the size of the stream data included in the second command list corresponds to the contents of the data counter, The apparatus further includes a port selecting means for selecting one port from the n ports, and one port selected by the port selecting means each time one port is selected by the port selecting means. Gets the second command list indicated by the address stored in the chain address counter corresponding to The head address of the memory area included in the second command list is transferred to the address counter, the size of the stream data included in the second command list is transferred to the data counter, and the command included in the second command list is transferred to the address counter. A command list transfer unit that transfers the address stored in the chain address counter to the next address, and a command list transfer unit that transfers the address stored in the chain address counter to the next address; Stream data transfer means for DMA-transferring the stream data of the size stored in the data counter to the memory area indicated by the head address, wherein the port selection means is configured to perform the DMA transfer in advance when the stream data transfer means completes the DMA transfer. Fixed order Based on the command passed to the command list transfer means, a new port in the next order is selected or the port selected immediately before is selected again, and the stream data transfer means sets the stream data by the command list transfer means. Stream data of the size stored in the data counter from one port selected by the port selection means to the memory area indicated by the head address stored in the address counter each time the data size is transferred to the data counter The command list generating means further transfers the address of the second command list to the second data transfer device to generate a first command list and stores the first command list in the memory. Information for specifying the stream data stored in the large-scale storage device; The data transfer system further includes information for specifying an address of a memory area in which the stream data is stored and information for specifying the size of the stored stream data.
A first data transfer device for DMA-transferring the stream data of the specified size from the memory to the large-scale storage device based on the command list, wherein the command list generating unit further specifies the size by the second data transfer device The first command list may be transferred to the first data transfer device after waiting for the transferred stream data to be DMA-transferred to the memory.

As a result, a plurality of ports can be arbitrated, so that a plurality of stream data can be efficiently transferred. Further, transfer to a plurality of input / output devices can be realized with a relatively small amount of hardware, and expansion is easy. Further, the plurality of stream data may be asynchronous, and the DMA transfer can be equally assigned to each asynchronous port, or the DMA transfer can be assigned to a specific port at a specific rate.

Also, stream data can be transferred without being affected by the transfer status of other ports. Therefore, the data of each port is distributed on the system bus in units of burst transfer, and the data transfer of the multiport multidevice can be efficiently executed as the whole system.

[Brief description of the drawings]

FIG. 1 is a diagram schematically illustrating a data transfer system according to an embodiment of the present invention.

FIG. 2 is a diagram showing a buffer area in a memory 11 in which stream data is temporarily stored.

FIG. 3 is a diagram showing a configuration of a command list stored in a memory 11;

FIG. 4 is a diagram showing the contents of a DMA command bit.

FIG. 5 is a diagram showing a detailed configuration of a multi-stream interface 15;

FIG. 6A is a diagram showing a detailed configuration of a DMA register 22; FIG. 6B is a diagram showing a configuration of a bit field inside the control register 22g.

FIG. 7 is a diagram showing a detailed configuration of a bus controller 21.

FIG. 8 is a diagram showing a configuration of a bit field inside a buffer command 22p generated by a buffer command generation unit.

FIG. 9 is a diagram showing a detailed configuration of a BFIFO 23.

FIG. 10 is a diagram showing a detailed configuration of a buffer interface 31.

11 is a diagram showing a detailed configuration of a buffer register 32. FIG.

FIG. 12 is a diagram showing a detailed configuration of a buffer 33a.

FIG. 13 is a diagram showing a control line FP44a.

FIG. 14 is a diagram showing a flow of a stream data transfer process in the CPU 10 when the data transfer system according to the present invention is used.

FIG. 15 is a diagram showing a flow of a process of transferring stream data in the bus controller 21 when the data transfer system according to the present invention is used.

FIG. 16 is a diagram showing a flow of a bus data conversion process of the stream data in the buffer controller 30 when the data transfer system according to the present invention is used.

FIG. 17 is a diagram illustrating a process of simultaneous operation of a plurality of ports when the DMA controller 20 according to the present invention is used.

FIG. 18 is a diagram showing a chain list for DMA-transferring stream data to a port 41a.

FIG. 19 is a diagram showing a chain list for DMA-transferring stream data to a port 41b.

FIG. 20 is a diagram showing a chain list for DMA-transferring stream data to a port 41c.

FIG. 21 is a diagram showing a chain list for DMA-transferring stream data to a port 41d.

FIG. 22 is a diagram schematically showing a conventional data transfer system.

[Explanation of symbols]

10 CPU 11 Memory 12 System Bus 13 SCSI Interface 14a, 14b, 14c, 14d HDD (Hard Disk Drive) 15 Multi-Stream Interface 16a, 16b, 16c Video Monitor 17 Video Cassette Recorder 20 DMA Controller 21 Bus Controller 21a Frame Pulse Receiving Unit 21b Port Selection unit 21c Command list transfer unit 21d Stream data transfer unit 21e Buffer command generation unit 22 DMA register 22a DMA address counter 22b DMA data counter 22c, 22d, 22e, 22f Chain address counter 22g, 22h, 22i, 22j Control register 22k Port number Register 22l RUN (control register configuration required) Element) 22m DONE (Component of control register) 22n IO (Component of control register) 22o FP (Component of control register) 23 BFIFO (Buffer) 24a, 24b I / O port 25a, 25b FIFO (Buffer) 26a Flag EA (control line) 26b flag EB (control line) 26c flag FA (control line) 26d flag FB (control line) 26e FDA (bus) 26f FDB (bus) 30 buffer controller 31 buffer interface 32 buffer register 32a port number register 32b 4 × mode (register) 32c, 32d, 32e, 32f in / out (register) 32g Data length (register) 33a, 33b, 33c, 33d Buffer 34a Field memo 34b WD (data bus for writing) 34c RD (data bus for reading) 34d WRST (control line for writing reset) 34e WCLK (control line for writing clock) 34f RRST (control line for reading reset) 34g RCLK (read clock) Control line) 34h BOA (bus) 34i BOB (bus) 34j, 34k Gate 35a, 35b, 35c, 35d Latch 36 Bus width converter 40a, 40b, 40c, 40d I / O controller 41a, 41b, 41c, 41d Port 424 x port 43 x nmode (control line) 44a, 44b, 44c, 44d FP (control line) 50a, 50b, 50c, 50d Stream interface

Claims (20)

[Claims] 1. A data transfer device for DMA-transferring stream data between n ports and a memory, wherein n is an integer of 2 or more, and the memory has at least one set of commands. A list is stored in advance, a memory area for storing stream data is secured, and the command list includes a start address of a memory area for storing stream data and a size of the stored stream data. An address counter that is also used for n ports and stores a head address of a memory area to which stream data is DMA-transferred next to one of the n ports; Of the memory area indicated by the start address stored in the address counter and the port of the n ports. And a data counter for storing the size of the stream data to be DMA-transferred to and from each of the ports, each of which corresponds to one port and stores the address of a memory in which a specific command list is stored. A command list indicated by an address stored in a specific chain address counter has a head address of a memory area included in the command list corresponding to the content of the address counter. The size of the stream data included in the list corresponds to the content of the data counter, and the data transfer device further includes a port corresponding to the specific chain address counter and a memory area indicated by a head address stored in the address counter. And stored in the data counter. Data transfer apparatus comprising: a stream data transferring means for DMA transferring the stream data sizes. 2. The data transfer device further generates a command list, stores the command list in the memory, and uses the address of the command list as a DMA
2. The data transfer device according to claim 1, further comprising a command list generation unit that transfers the command list to a chain address counter corresponding to the port to which the data is transferred. 3. The data transfer apparatus further comprises: a port selection unit that selects one port from the n ports; and each time the port selection unit selects one port, the port selection unit selects the port. Acquiring a command list indicated by an address stored in a chain address counter corresponding to one port selected by the means, transferring a head address of a memory area included in the command list to the address counter, Transfer the size of the stream data included in the data counter,
A command list transfer unit that updates an address stored in the chain address counter to a next address, wherein the stream data transfer unit transfers the stream data size to the data counter by the command list transfer unit. Each time the stream data of the size stored in the data counter is DMA-transferred between one port selected by the port selection means and the memory area indicated by the head address stored in the address counter. The data transfer device according to claim 1, wherein 4. The data transfer device further generates a command list, stores the command list in the memory, and uses the address of the command list as a DMA
4. The data transfer device according to claim 3, further comprising a command list generation unit that transfers the command list to a chain address counter corresponding to the port to which the data is transferred. 5. The command list further includes a command indicating whether or not to change a port to be selected next, and the command list transfer unit further includes a command for selecting one port by the port selection unit. Each time a port list is selected, a command list indicated by an address stored in a chain address counter corresponding to one port selected by the port selection unit is obtained, and a command included in the command list is sent to the port selection unit. When the DMA transfer is completed by the stream data transfer unit, the port selection unit newly sets a next-order port based on a predetermined order and a command passed to the command list transfer unit. 4. The port according to claim 3, wherein the port selected before is selected again. Over data transfer device. 6. The data transfer device further generates a command list, stores the command list in the memory, and uses the address of the command list as a DMA
6. The data transfer device according to claim 5, further comprising a command list generating unit that transfers the command list to a chain address counter corresponding to the port to which the data is transferred. 7. A transfer request signal indicating a transfer request for a fixed amount of stream data is output from at least one of the n ports, and the data transfer device further outputs a transfer request signal for each port. 6. The data transfer apparatus according to claim 5, further comprising a receiving unit for receiving, wherein the port selecting unit selects only a port for which a transfer request signal has been received by the receiving unit when selecting a port. 8. The data transfer device further generates a command list, stores the command list in the memory, and uses the address of the command list as a stream data in the DMA.
8. The data transfer device according to claim 7, further comprising: a command list generating unit that transfers the command list to a chain address counter corresponding to the port to which the data is transferred. 9. A transfer request signal is output from at least one of the n ports at regular intervals, and the receiving means further comprises one port corresponding to one port, When the transfer means receives a transfer request signal from a corresponding port by the receiving means, the apparatus includes n request bit storage means for setting a request bit, wherein the command indicates that a next selected port is to be changed Further indicates whether to clear the request bit set in the request bit storage means corresponding to the selected port, the port selection means, based on the command passed from the command list transfer means Clears or does not do any request bit set in the request bit storage means corresponding to the selected port, and when selecting a port, Data transfer apparatus according to claim 7, wherein the request bit in the request bit storing means for selects only port that is set. 10. The data transfer apparatus further generates a command list, stores the command list in the memory, and stores an address of the command list in
10. The data transfer device according to claim 9, further comprising a command list generating unit that transfers the command list to a chain address counter corresponding to the port to which the data is transferred. 11. The data transfer apparatus according to claim 1, wherein each time one port is selected by said port selection means, based on the selected port and a size of stream data stored in said data counter. A bus width conversion command generation unit that generates a bus width conversion command and transmits the bus width conversion command to the bus width conversion unit, wherein the bus width conversion command includes information specifying a port and information specifying a data length of stream data to be transferred Wherein the data transfer device further converts the bus width of the port indicated by the bus width conversion command and the bus width of the memory, based on the bus width conversion command, between the port and the port. A bus width conversion unit configured to transfer stream data having a data length indicated by the bus width conversion command; The stream data transfer means transfers the stream data to and from the bus width conversion means by DMA instead of one port selected by the port selection means. 9. The data transfer device according to item 9. 12. The data transfer device further generates a command list, stores the command list in the memory, and uses the address of the command list as a DMA
12. The data transfer device according to claim 11, further comprising a command list generating unit that transfers the command list to a chain address counter corresponding to the port to which the data is transferred. 13. The data transfer device further comprises first buffer means for buffering stream data between the memory and the bus width conversion means, wherein the first buffer means comprises n ports. The stream data transfer means transfers the stream data to and from the first buffer means by DMA instead of the bus width conversion means.
A data transfer device according to claim 1. 14. The data transfer apparatus further generates a command list, stores the command list in the memory, and uses the address of the command list as the
14. The data transfer device according to claim 13, further comprising a command list generation unit that transfers the command list to a chain address counter corresponding to the port to which the data is transferred. 15. The data transfer device according to claim 1, further comprising: one port corresponding to one port; and n ports for buffering stream data between the corresponding port and the bus width conversion means. 14. The data transfer device according to claim 13, further comprising a second buffer unit, wherein the bus width conversion unit transfers stream data to and from the second buffer unit instead of the port. 16. The data transfer device further generates a command list, stores the command list in the memory, and uses the address of the command list as a DMA
16. The data transfer device according to claim 15, further comprising a command list generating unit that transfers the command list to a chain address counter corresponding to the port to which the data is transferred. 17. The data transfer device according to claim 1, further comprising:
M is an integer equal to or less than n, and the data transfer device further has one corresponding to one of the m second buffer means, and the corresponding port or m × speed port Select and corresponding port or m corresponding to the second buffer means
M first I / O controllers for controlling the input / output of stream data between the double speed port and (nm) second I / O controllers other than the m second buffer means
One of the buffer means corresponds to one of the buffer means, and controls input / output of stream data between the corresponding second buffer means and the corresponding port (n
-M) second I / O controllers, wherein the n second buffer means buffers stream data with a corresponding I / O controller instead of a corresponding port, The m-times ports are connected to m first I / O controllers, and the n ports are respectively connected to m first I / O controllers and (nm) second I / O controllers. 2. The method according to claim 1, wherein
6. The data transfer device according to 5. 18. The data transfer apparatus further generates a command list, stores the command list in the memory, and stores an address of the command list in
18. The data transfer device according to claim 17, further comprising a command list generation unit that transfers the command list to a chain address counter corresponding to the port to be transferred. 19. The method according to claim 19, wherein the mass storage device is connected to n ports.
A data transfer system for performing DMA transfer of stream data, wherein n is an integer of 2 or more, and a large-scale storage device in which stream data is stored and an area for storing stream data are reserved in advance. A memory, and a command list generating means for generating a first command list, wherein the first command list includes information specifying stream data stored in the large-scale storage device, and a memory area in which the stream data is stored. The data transfer system further includes: information for specifying the address of the data stream; and information for specifying the size of the stream data to be stored. The stream data of the specified size is DMA-converted from the storage device to the memory. A first data transfer device for transmitting the first command list to the first data transfer device, generating a second command list, storing the second command list in the memory, The second command list includes a start address of a memory area in which stream data is stored, a size of the stored stream data, and a command indicating whether to change a port to be selected next. The system further comprises a second data transfer device, wherein the second data transfer device is also used for n ports, and the stream to be DMA-transferred to one of the n ports, An address counter that stores the start address of the memory area where data is stored. Also used for n ports and stored in the address counter. A data counter for storing the size of the stream data to be MA-transferred from the memory area indicated by the specified start address to one of the n ports, one for each port, and one for each port , An n number of chain address counters storing the addresses of the memories in which the specific second command lists are stored, and the second command list indicated by the addresses stored in the specific chain address counters is the second command list. The head address of the memory area included in the list corresponds to the content of the address counter, the size of the stream data included in the second command list corresponds to the content of the data counter, and the second data transfer device further includes: Port selecting means for selecting one port from the n ports; Every time one port is selected by the stage, a second command list indicated by the address stored in the chain address counter corresponding to the one port selected by the port selecting means is obtained, and the second command list is obtained. The head address of the memory area included in the list is transferred to the address counter, the size of the stream data included in the second command list is transferred to the data counter, and the command included in the second command list is selected by the port selection. Command list transfer means for transferring the address stored in the chain address counter to the next address, and selecting from the memory area indicated by the start address stored in the address counter by the port selection means. One
Stream data transfer means for transferring the stream data of the size stored in the data counter to the plurality of ports by DMA, and the port selecting means determines in advance when the stream data transfer means terminates the DMA transfer. Based on the given order and the command passed to the command list transfer means, a new port in the next order is selected or the port selected just before is selected again, and the stream data transfer means Each time the size of the stream data is transferred to the data counter by the list transfer means, the data counter is transferred from the memory area indicated by the head address stored in the address counter to one port selected by the port selection means. The stream data of the size stored in
A, and the command list generating means further waits for the stream data whose size is specified by the first data transfer device to be DMA-transferred to the memory, and stores the address of the second command list in the stream data. Data transfer to a chain address counter corresponding to a port to which DMA transfer is performed. 20. From n ports to a mass storage device,
A data transfer system that DMA-transfers stream data, wherein n is an integer of 2 or more, and a large-scale storage device in which an area for storing stream data is secured; A secured memory; and a command list generating means for generating a second command list and storing the generated command list in the memory. The second command list includes a head address of a memory area where stream data is stored, The data transfer system further includes a second data transfer device, and a command indicating whether to change a port to be selected next. The stream data is DMA-transferred from one of the n ports to the n ports. An address counter for storing the start address of the memory area to be used, and DMA transfer from one of the n ports to the memory area indicated by the start address stored in the address counter, which is also used for n ports. A data counter for storing the size of stream data to be transmitted, and n chains for storing addresses of memories each storing a specific second command list, one for each port. The second command list indicated by the address stored in the specific chain address counter includes a first address of a memory area included in the second command list, and a second address of the second counter. The size of the stream data included in the command list corresponds to the content of the data counter. The second data transfer device further includes: a port selection unit that selects one port from the n ports; and each time one port is selected by the port selection unit, the port selection unit Obtains the second command list indicated by the address stored in the chain address counter corresponding to the one port selected by the above, transfers the head address of the memory area included in the second command list to the address counter, The size of the stream data included in the second command list is transferred to the data counter, the command included in the second command list is passed to the port selection means, and the address stored in the chain address counter is Command list transfer means for updating to the next address, selected by the port selection means Stream data transfer means for DMA-transferring stream data of the size stored in the data counter from one of the obtained ports to the memory area indicated by the head address stored in the address counter, When the DMA transfer is completed by the stream data transfer means, a port in the next order is newly selected or immediately before, based on a predetermined order and a command passed to the command list transfer means. The selected port is selected again, and the stream data transfer means, each time the size of the stream data is transferred to the data counter by the command list transfer means, from one port selected by the port selection means. Memory area indicated by the start address stored in the address counter The stream data size stored in the data counter DM
A, the command list generating means further transfers an address of the second command list to the second data transfer device, generates a first command list, stores the first command list in the memory, and stores the first command list in the memory. Includes information specifying the stream data stored in the large-scale storage device, information specifying the address of the memory area where the stream data is stored, and information specifying the size of the stored stream data, The data transfer system further includes a first data transfer device that DMA-transfers the stream data of the specified size from the memory to the large-scale storage device based on the first command list transferred from the command list generation unit. The command list generating means further specifies the size by the second data transfer device. Stream data waiting to be DMA transferred to the memory, the data transfer system, characterized in that for transferring the first command list to the first data transfer device.