JP5328833B2 - Direct memory access system and control method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To attain high-function and high-performance direct memory access transfer without increasing load on a CPU or circuit scale. <P>SOLUTION: The system includes a direct memory access unit and a processor unit. The processor unit includes a memory and a processor which writes an instruction to be executed by the direct memory access unit to the direct memory access unit by reading the instruction from the memory and executing it. The direct memory access unit includes: a plurality of program counters, a selection means which successively selects the plurality of program counters, an instruction holding means which holds the instruction written by the processor, an output means which outputs an instruction stored at an address of the instruction holding means indicated by the program counter selected by the selection means; and an execution means which executes data transfer by direct memory access in response to the instruction output by the output means. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a direct memory access system and a control method thereof.

  Various direct memory accesses have been used to realize data transfer between a device that generates data and writes it to memory, or a device that reads data from the memory and processes data without placing a load on the CPU. A device has been proposed. In a typical direct memory access device, the memory address of the transfer destination or transfer source, the transfer direction (device to memory, memory to device), the size of data to be transferred, etc. are set by the CPU in advance and set. The data transfer between the device and the memory is performed without intervention of the CPU until the data of the set size is transferred while sequentially updating the memory addresses. When the data transfer is completed, the direct memory access device notifies the CPU of an interrupt, and the CPU knows the completion of the data transfer and processes the transferred data. Furthermore, another data transfer is continuously set and activated (see Patent Document 1).

  In many cases, data is transferred from the device to the memory using such a direct memory access device, and the transferred data on the memory is further transferred to another device for data processing. That is, the memory is used as a processing speed buffer buffer for two devices, or as a temporary buffer when the data access order of the two devices is different. For example, in the process of compressing and encoding the image captured by the image sensor, the image data captured by the image sensor is transferred to the memory in raster order by the direct memory access device, and the transferred rectangular area data is accessed by a different direct memory access. The data is read out by the apparatus and compressed and encoded. In this case, the image data is temporarily stored in the memory because the data capturing speed of the image sensor is different from the processing speed of the compression encoding apparatus and raster block conversion is necessary.

  In this data transfer example, the setting procedure of the direct memory access device is as follows. The direct memory access device for capturing data in the image sensor is designated as DMA1, and the direct memory access device for transferring compression-coded data is designated as DMA2. Since the memory size for storing image data for all screens is huge and expensive, it is usually possible to transfer data continuously by using a double-buffered memory with a size that can store only a part of the image. To do.

  First, the CPU makes a setting for DMA1 to transfer image data for several rasters from the image sensor to the memory (buffer 1), and starts up. When DMA1 completes the data transfer, it notifies the CPU by an interrupt. The CPU makes a setting for transferring the data for several rasters stored in the buffer 1 to the compression encoding processing unit for the DMA 2, starts up, and sends image data for the next several rasters from the image sensor. A setting for transferring to the memory (buffer 2) is made to DMA1 to start up. In this example, the compression code processing is always faster than the data transfer from the image sensor. As a result, the completion interrupt of DMA2 can be ignored, and every time the completion interrupt of DMA1 is received, the CPU sets DMA1 and DMA2 so that buffers 1 and 2 are used alternately, and starts up. You can take it.

JP-A-5-73477

  However, the double buffer operation by the conventional direct memory access device has a problem that the load on the CPU increases because it is necessary to set and activate the two direct memory access devices by the CPU every time DMA is completed. There is also a problem that the data transfer rate is lowered due to the overhead due to the interrupt latency of the CPU. Further, in the example of the double buffer operation, it is assumed that the compression code processing is always faster than the data transfer from the image sensor. However, if it is uncertain which transfer is faster, the CPU completes the DMA2. Interrupts also need to be processed, and processing must be switched depending on which ended earlier. In this case, the load on the CPU increases more and more.

  In order to reduce the load on the CPU, it is possible to monitor the transfer data amount of each direct memory access device, and to equip the dedicated hardware for interrupting and restarting the data transfer. In order to execute complicated data transfer, there is a problem that the dedicated hardware becomes complicated and the circuit scale increases. In addition, when it becomes necessary to cope with a new access pattern after hardware development, there is a problem that it is necessary to recreate the hardware.

  The present invention has been made in view of the above-described conventional example, and has an object to realize high-function and high-performance direct memory access transfer without increasing the load on the CPU and without increasing the circuit scale. To do.

In order to achieve the above object, in a direct memory access system having a direct memory access unit and a processor unit according to the present invention, the processor unit includes:
A memory and a processor that reads and executes instructions from the memory to write instructions executed by the direct memory access unit to the direct memory access unit, and the direct memory access unit includes a plurality of program counters, A selection means for sequentially selecting the plurality of program counters, an instruction holding means for holding an instruction written by the processor, and an address of the instruction holding means indicated by the program counter selected by the selection means Output means for outputting a stored instruction, and execution means for executing data transfer by direct memory access in accordance with the instruction output by the output means.

  According to the present invention, high-performance and high-performance direct memory access transfer can be realized without increasing the load on the CPU and without increasing the circuit scale. In particular, there is an effect that the performance of the entire system is improved because the CPU is not involved when performing a plurality of data transfers using a double buffer or the like while synchronizing them.

1 is a block diagram of a direct memory access device according to an embodiment of the present invention. FIG. It is a block diagram of an instruction memory. It is a detailed block diagram of a program counter, a program counter selection part, and a program counter update part. It is a detailed block diagram of a program counter selection signal generation unit. It is a figure which shows the relationship between the decoding of a program counter selection permission signal, and a selection signal. It is a figure which shows the decoding of an instruction | indication. It is a figure which shows the meaning of a size field. It is a figure which shows the meaning of the identifier of an internal resource. It is a figure which shows the relationship between size, pos_d / s, and an effective byte lane. It is a figure which shows the relationship between size, pos_d / s, and an effective byte lane. It is a figure which shows the encoding of a special instruction. It is a detailed block diagram of an execution suppression / selection permission signal generation unit. It is a detailed block diagram of a 2nd selection permission signal generation part. It is a timing diagram which shows the direct memory access operation | movement of the direct memory access apparatus of one embodiment of this invention. FIG. 5 is a timing chart showing a suspend / resume operation of the direct memory access device according to the embodiment of the present invention. 1 is a block diagram of a JPEG encoder to which a direct memory access device according to an embodiment of the present invention is applied. FIG. It is a sequence diagram of the direct memory access operation | movement in the JPEG encoder of one embodiment of this invention.

  Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the drawings. However, the constituent elements described in this embodiment are merely examples, and are not intended to limit the scope of the present invention only to them.

(Overview)
The direct memory access device according to the present embodiment is for executing a plurality of complex data transfers with various access patterns in a concurrent manner while synchronizing with a simple configuration.

  For this purpose, a plurality of program counters are provided, and DMA transfers corresponding to a plurality of DMA requests are executed in accordance with data transfer instructions sequentially referred to by the program counters. The data transfer instruction sequence to be referred to is stored in advance in a predetermined memory.

  That is, for one data transfer execution unit, the instruction memory is divided into a plurality of areas, a plurality of independent programs can be stored, a plurality of program counters corresponding to each area are provided, and the progress of each program is independent. To control. Thereby, different access patterns can be programmed for each data transfer request from a plurality of devices. Furthermore, by selecting a plurality of program counters for each data transfer, a plurality of programs can be processed in a time-sharing manner, thereby enabling multitasking.

  When the source or destination of a data transfer instruction referred to by a program counter is a DMA data port and there is no DMA request, this program counter enters a sleep state, and an instruction referred to by another program counter is executed. . When a DMA request event of the DMA data port occurs, the dormant program counter returns to the execution state.

  That is, the transfer request signal from the device subject to direct memory access is monitored to determine whether or not the transfer instruction is possible. If the transfer request corresponding to the transfer instruction is not output from the device, the data transfer is exited. Data transfer to a not-ready device is avoided. Further, in this case, a restriction is also imposed on the entrance side (selection of the program counter) to avoid the execution of useless instructions and improve the overall processing speed.

  Further, in addition to the data transfer instruction, an instruction for explicitly sleeping a specific program counter and an instruction for returning a sleeping program counter to an execution state are provided. That is, program interruption and restart instructions are prepared in advance so as to be programmable, and the selection of the program counter is controlled in accordance with such instructions.

  In this way, it is possible to execute a plurality of data transfers while synchronizing without any involvement of the CPU other than writing the program to the instruction memory. In particular, there is an effect that the performance of the entire system is improved because the CPU is not involved when performing a plurality of data transfers using a double buffer or the like while synchronizing them.

(Specific configuration)
FIG. 1 is a block diagram showing an electrical configuration of a direct memory access apparatus according to an embodiment of the present invention.

  In the notation of lines connecting the blocks, data system connections are indicated by arrows having a width, and control system connections are indicated by arrows having no width. However, not all the connections are illustrated, and only representative connections necessary for the description are illustrated.

  This apparatus is connected to two DMA (direct memory access) devices 101 and 102 that perform data transfer requests, is connected to a CPU bus, stores data, and is a memory 2 that is a data transfer source or data transfer destination, and is being executed Based on three program counters (PCs in the figure) 301, 302, and 303 indicating the addresses of the instructions in the instruction memory 5 and a selection signal, any one of the program counters 301 to 303 is set as one of the program counters. The program counter selection unit 4 that selects the stored value as an address of the instruction memory 5, the instruction memory 5 that stores the data transfer instruction, and the data transfer instruction that is the data output of the instruction memory 5 is decoded to transfer direction and transfer An instruction decoding unit 6 for determining the destination and the source is included. The instruction memory 5 outputs an instruction from the address indicated by the program counter selected by the program counter selection unit 4.

  Also included is a data transfer execution unit 7 that drives the two DMA ports 701 and 702 or the bus IF (interface) 703 according to the decoded instruction to execute data transfer. Further, a transfer source / destination detection unit 801 that detects the transfer source or destination from the output of the instruction decode unit 6, a DMA request detection unit 802 that detects a data transfer request from the DMA device, and a transfer source / destination detection unit 801 are detected. A match determination unit 803 that determines whether the transfer source or destination matches the DMA device that has issued the data transfer request. If the determination results do not match, data transfer of the data transfer execution unit 7 is suppressed. An execution suppression signal generation unit 804 that outputs a signal, and a first selection permission signal generation that generates a first selection permission signal for deselecting the program counter corresponding to the currently executing instruction if the determination results do not match A signal generation unit 8 including a unit 805.

  When the transfer request corresponding to the content of the instruction output from the instruction memory 5 is not output from the direct memory access devices 101 and 102, the execution suppression signal generation unit 804 transfers the data that is suppressed by the data transfer execution unit 7 Functions as a suppression unit. In addition, the first selection permission signal generation unit 805 and the selection signal generation unit 10, when a transfer request corresponding to the content of the instruction output from the instruction memory 5 is output from the direct memory access devices 101 and 102, The program counter selection unit 4 permits selection of the program counters 301 to 303 corresponding to the output instruction, and a transfer request corresponding to the content of the instruction output from the instruction memory 5 is output from the direct memory access devices 101 and 102. If not, a selection permitting unit that disallows selection of the program counters 301 to 303 that output instructions by the program counter selecting unit 4 until a transfer request corresponding to the content of the output instruction is output. Function as.

  A second selection signal generation unit 9 that determines whether the output of the instruction decode unit 6 is a suspend instruction or a resume instruction, and generates a second selection permission signal for selecting or deselecting the program counters 301 to 303; A selection signal generation unit 10 that generates a selection signal to be sent to the program counter selection unit 4 for each data transfer execution based on the first and second selection permission signals, and a program counter selected for each data transfer execution based on the selection signal It includes a program counter update unit 11 that updates values one by one, and a CPU 12 that stores instructions in the instruction memory 5 via a data port (not shown) and is connected to a CPU bus that controls the operation of the direct memory access device.

  The second selection signal generation unit 9 and the selection signal generation unit 10 are configured by the program counter selection unit 4 when the instruction output from the instruction memory 5 is an interruption instruction specifying any one of the program counters 301 to 303. When the designated program counters 301 to 303 are not allowed to be selected and the instruction output from the instruction memory 5 is a restart instruction designating one of the program counters 301 to 303, a program counter selection unit 4 functions as a second selection permission unit that permits selection of the designated program counters 301 to 303.

  Here, among the blocks in the apparatus, the reset of the CPU 12 is first released, and the CPU 12 fetches an instruction from the built-in ROM and executes it to control a reset signal (not shown) to sequentially release the reset of each block. Is possible. When all the modules other than the CPU 12 are reset, the CPU 12 first writes a command to be executed by the direct memory access device to the command memory 5.

  FIG. 2 shows the configuration of the instruction memory 5 and the input / output ports used in the present embodiment. The instruction memory 5 is a 2-port (1Read / 1Write) SRAM, and has a data width of 32 bits and a word length of 64. The read address (READ ADDRESS) is 6 bits. When a read enable signal (READ ENABLE) is asserted, 32-bit read data is read from the READ DATA port. In the present embodiment, the read address is supplied from the program counter selection unit 4 and the read data is supplied to the instruction decoding unit 6. The write address (WRITE ADDRESS) is 6 bits, and when the write enable signal (WRITE ENABLE) is asserted, the data driven on the 32-bit write data (WRITE DATA) signal is written to the write address of the SRAM. In this embodiment, both the write address and the write data are supplied from the CPU 12.

  Returning to FIG. 1, when the writing of the instruction data to the instruction memory 5 is completed, the CPU 12 sequentially releases the reset of each block, whereby the direct memory access device starts its operation. The program counters 301, 302, and 303 are each composed of a 6-bit flip-flop, and the initial values at the time of reset are "000000", "010000", and "100,000", respectively. That is, the program counter 301 executes an instruction from address 0x0, the program counter 302 executes an instruction from address 0x10, and the program counter 303 executes an instruction from address 0x20.

  A detailed block diagram of the program counters 301, 302, 303, the program counter selection unit 4 and the program counter update unit 11 is shown in FIG. The output of the selector 1101 is input to the program counter 301. The selector 1101 includes the current value of the program counter, the value obtained by adding 1 to the current value, the value loaded by the LOAD instruction (store_d), the return value of the program counter when looping back by the LOOP instruction (lp_back_pc), JUMP Select and output one of the jump destination addresses (jump_pc) by the instruction. The selector 1102 selects either the output of the program counter itself or the value obtained by adding 1 to the value of the program counter (the output of the +1 adder 1103) based on the program counter selection signal pc_sel. That is, when the program counter is selected in the clock cycle, a value obtained by adding 1 is selected. When the program counter is not selected, the current value is selected. The program counters 302 and 303 have the same configuration, and the program counter is updated. The program counter selection unit 4 outputs the program counters 301 (PC (0)), 302 (PC (1)), and 303 (PC (2)) in response to a 3-bit program selection signal pc_sel [2: 0]. Is selected and output as a read address of the instruction memory. pc_sel [2: 0] is a one-hot signal. When it is “001”, the program counter 301 is selected, when it is “010”, the program counter 302 is selected, and when it is “100”, the program counter 303 is selected. . That is, PC (n) is selected when pc_sel [n] = '1' (where n = 0, 1, 2).

  FIG. 4 shows a detailed block diagram of the selection signal generator 10. The flip-flops 1001, 1002, and 1003 are connected to a clock signal and a reset signal, respectively, and the output is a program counter selection signal. The flip-flop 1001 is set to “1” by reset, the output of the selector 1004 is connected to the D input, and the Q output becomes pc_sel [0]. The flip-flop 1002 is set to “0” by reset, the output of the selector 1005 is connected to the D input, and the Q output becomes pc_sel [1]. The flip-flop 1003 is set to “0” by reset, the output of the selector 1006 is connected to the D input, and the Q output becomes pc_sel [2].

  The decoder 1007 gates the first selection permission signal pc_en1 [2: 0] output from the first selection permission signal generation unit 805 and the second selection permission signal pc_en2 [2: 0] output from the second selection permission signal generation unit 9. The AND operation output pc_en [2: 0] by 1008, 1009, 1010 and the stall signal indicating the instruction execution stall instruction are decoded, and a selection signal is generated for the selectors 1004, 1005, 1006. The decoding method is shown in FIG. The relationship of the selection signal sel_cnt [2: 0], which is an output, with respect to the stall, which is an input, and the logical product operation output pc_en [2: 0] is shown. For example, when the stall is “1”, sel_cnt is all 2 and all flip-flops hold the current value. That is, pc_sel is not updated. When stall is "0" and pc_en = "111", sel_cnt is all 0 and pc_sel operates as a shift register. That is, transition is made from “001” → “010” → “100” → “001”, and PC (0) → PC (1) → PC (2) → PC (0) is selected in this order. When the stall is “0” and pc_en = “011”, sel_cnt = “301” is set so that selection of PC (2) is not permitted, and pc_sel is changed from “001” → “010” → “001” → ” Transition is made to “010” → “001”, and PC (0) → PC (1) → PC (0) → PC (1) → PC (0) is selected in this order.

  The instruction corresponding to the program counter selected by the program counter selection unit 4 is read from the instruction memory 5 and input to the instruction decoding unit 6. The instruction consists of 32 bits and is decoded as shown in FIG.

  When a 32-bit instruction is expressed as Inst [31: 0], when Inst [31:30] = "00", a special instruction (Special Instruction), when "01", a load instruction (Load Instruction), and when "10" A store instruction (Store Instruction) “11” is decoded as an invalid instruction. The load instruction is a data transfer instruction from the memory to internal resources (including the DMA port) of the direct memory access device, and the store instruction is a data transfer instruction from the internal resource to the memory. Special instructions include instructions provided in general processors such as NOP instructions (instructions that do nothing), loop instructions (LOOP), and jump instructions (JUMP).

  Inst [29:27] is a field indicating the data size, and details are shown in FIG. For example, “000” indicates transfer of 1 byte, and “100” indicates transfer of 5 bytes.

  Inst [26:23] is a field indicating the index of the transfer source resource, Inst [22:19] is a field indicating the index of the transfer destination resource, and the identifier (load command) of the internal resource indicated by Inst [18:16] Indicates the transfer destination, and in the case of a store instruction, indicates the transfer source of which internal resource.

  Details of the internal resource identifier are shown in FIG. "000" indicates a PC or program counter, "001" indicates an AR or address register, "010" indicates a GPR or general-purpose register, and "010" indicates an IN / OUT or DMA port ( IN / OUT is identified by whether it is a load or a store), “100” indicates an LP, that is, a loop register, and “101” indicates an OFST, that is, an offset register.

  An internal resource identifier indicating a transfer source in the case of a load instruction and a transfer destination in the case of a store instruction is fixed in an address register, and only an index is designated by each index field.

  Inst [15:13] is a field indicating the valid byte lane of the data transfer source or destination, and indicates how many bytes are transferred to or from which byte lane together with the data size field. 9A and 9B show in detail the byte lanes that are valid depending on the combination of size and byte lane. The data is 64 bits, and the byte lanes are [63:56], [55:48], [47:40], [39:32], [31:24], [23:16], [15: 8]. ], [7: 0] are 8 lanes, and “v” is written in the effective lane. For example, when the size field (size) is “000”, that is, 1 byte, and the byte lane field (pos_d / s) is “011”, that is, the fourth byte lane, 1 byte of data is transferred to the data [31:24]. .

  In order to better understand, some examples of instructions are given.

  When Inst = "01_000_0001_0010_100_001_000000000000", this is a load instruction, and 1-byte data on the memory indicated by the address register AR (1) is loaded into [15: 8] of the loop register LP (2).

  When Inst = "10_111_0001_0010_011_000_000000000000", this is a store instruction, and 8-byte data read from the DMA input port IN (1) is stored in the memory indicated by the address register AR (2).

  FIG. 10 shows the encoding of special instructions.

  EnableThread is an instruction for enabling a specific program counter, and can be used when other program counters other than the program counter are activated.

  DisableThread is a command that disables a specific program counter. When other program counters other than the program counter are put into a sleep state, or when execution of a program is finished, the program is put into a sleep state. Can be used for

  SuspendThread, ResumeThread, WaitTrigger, and EmitTrigger are each an instruction to suspend (execute execution) a specific program counter, an instruction to resume (restart execution) a specific program counter, and wait for a specific trigger event to set its own program counter. This is an instruction to suspend (execute execution) state and an instruction to generate a specific trigger event.

  JUMP is a jump instruction and copies the operand Inst [23:12] to the currently selected program counter. In the present embodiment, since the program counter is 6 bits, Inst [17:12] is actually copied.

  LoadImmidiateByte is an instruction for loading an immediate value into an internal resource, and 1 byte indicated by the operand Inst [7: 0] is copied to the internal resource specified by the other operand.

  ClearResiger is an instruction to clear internal resources to zero.

  LoopIn is a loop entry command, and a loop is realized by a combination of the loop register LP and the offset register OFST specified by LoopIndicator (Inst [22:19]).

  The data transfer execution unit 7 executes data transfer according to the instruction decoding result of the instruction decoding unit 6. In addition, four general-purpose registers GPR, address registers AR, loop registers LP, and offset registers OFST (not shown) are provided as internal resources. Further, the DMA port 701 (IN (0) and OUT (0)) is used for data transfer with the direct memory access device 101, and the DMA port 702 (IN (1)) is used for data transfer with the direct memory access device 102. And OUT (1)) and a bus interface 703 for data transfer with the memory 1.

  The general-purpose register is a register that temporarily holds data. For example, the general-purpose register is used for copying data loaded from a memory to another internal resource for each byte.

  Here, the address register AR generates an address to be output to the bus interface. Similarly to a general processor, a configuration including a mode (automatic update addressing mode) for updating the value of the address register AR for each data transfer is also preferable. The loop register LP indicates the number of instruction loops, and the offset register OFST indicates an instruction address to be looped back. A predetermined value is loaded into the loop register LP and the offset register OFST, and a loop instruction is executed to enter the loop. When the program counter advances and coincides with the value stored in the offset register OFST, the value of the program counter is updated to an address indicating the instruction next to the loop instruction and the value of the loop register is decremented by one. When the loop register LP becomes 0, the loop is exited, that is, only 1 is added to the value of the program counter. A program example using a very simple loop is shown.

================================================== ===========================
Instruction address Instruction 0x00 Load immediate value 0x20 to AR (0) [7: 0] 0x01 Load value in memory indicated by AR (0) to LP (0) (0x20 ground data = 0x20)
0x02 Load immediate value 0x04 to OFST (0) 0x03 LoopIn instruction (indicator 0)
0x04 Stores the data read from DMAPort (0) at the memory address indicated by AR (1) and stores AR (1) ++
0x05 Sleep yourself with DisableThread.
================================================== ===========================
According to the above instruction sequence, a loop is entered by executing an instruction at address 0x03, data is transferred from the DMA port to the memory as described in address 0x04, and loopback is performed because the program counter matches the offset register. Jump to the next address of the instruction, that is, 0x04. This is repeated the number of times LP (0), that is, 32 times, and the process exits from the loop.

  The signal generation unit 8 executes data transfer based on the instruction decode result by the instruction decode unit 4, the direct memory access request of the direct memory access devices 101 and 102, and the program counter selection signal from the program counter selection signal generation unit 10. An execution suppression signal to the unit 7 and a first selection permission signal to the program counter selection signal generation unit 10 are generated.

  FIG. 11 is a block diagram showing the internal configuration of the signal generator 8. Reference numerals 601, 602, 603, 604, and 605 are comparators included in the instruction decode unit 6, but are shown in FIG. 11 for convenience of explanation. Comparator 601 determines whether the instruction is a load instruction. If it is a load instruction, the load signal is asserted. Comparator 602 determines whether the instruction is a store instruction. If it is a store instruction, the store signal is asserted. The comparator 603 determines whether the transfer source or transfer destination index is 0. If the index is 0, the Port0 signal is asserted. The comparator 604 determines whether the transfer source or transfer destination index is 1. When the index is 1, the Port1 signal is asserted. The comparator 605 determines whether the transfer source or transfer destination is a DMA port. If it is a DMA port, the DMA signal is asserted.

  The gates 811, 812, 813, and 814 constitute a transfer source / destination detection unit 801. The gate 811 receives the load, Port0, and DMA signals, and outputs a 3-input AND as the LD_OUT0 signal. The LD_OUT0 signal indicates that an instruction to load data to DMA port 0 has been issued. The gate 812 receives load, Port1, and DMA signals, and outputs a 3-input AND as an LD_OUT1 signal. The LD_OUT1 signal indicates that an instruction to load data to the DMA port 1 has been issued. The gate 813 receives the store, Port0, and DMA signals, and outputs a 3-input AND as the ST_IN0 signal. The ST_IN0 signal indicates that an instruction to read data from the DMA port 0 and store it in the memory has been issued. The gate 814 receives the store, Port1, and DMA signals, and outputs a 3-input AND as the ST_IN1 signal. The ST_IN1 signal indicates that an instruction to read data from the DMA port 1 and store it in the memory has been issued.

  Gates 831, 832, 833, and 834 constitute a coincidence determination unit 803 that detects whether or not a direct memory access request corresponding to the issued instruction is asserted. DMAOReq0 is asserted to "1" when the direct memory access device 101 requests data transfer from the memory, and DMAOReq1 is "1" when the direct memory access device 102 requests data transfer from the memory. DMAIReq0 is asserted to "1" when the direct memory access device 101 is requesting data transfer to the memory, and DMAIReq1 is when the direct memory access device 102 is requesting data transfer to the memory Is asserted to "1". The outputs of the gates 831, 832, 833, and 834 become “0” level when there is no data transfer request from the DMA port to which the issued instruction is to access.

  The gate 841 is a gate constituting the execution suppression signal generation unit 804. When any one of the outputs of the gates 831, 832, 833, and 834 becomes “0”, the output becomes “0”. Therefore, the output of the gate 841 becomes an execution suppression signal (“0” level when it should be suppressed).

  The gates 851, 852, 853, and 854 detect which program counter that issued the direct memory access instruction has received execution suppression when accessing which DMA port. The flip-flops 855, 856, 857, and 858 hold the execution suppression detection result. Gates 821, 822, 823, and 824 constitute a DMA request detection unit 802 that detects that a direct memory access request corresponding to a direct memory access instruction whose execution is being suppressed has occurred. When it is detected that a direct memory access request corresponding to the direct memory access instruction whose execution is being suppressed is generated, the flip-flops 855, 856, 857, and 858 are cleared. Gate 8591 generates an execution suppression state, and gate 8592 generates an execution suppression release state. The gate 8593 generates an execution suppression state of a specific program counter, and outputs this to the program selection signal generation unit 10 as the first selection permission signal pc_en1 [2: 0]. That is, when pc_en1 [n] is “1”, selection is permitted, and when it is “0”, selection is not permitted.

  In FIG. 11, which program counter is indicated by an integer n. Since n is 0, 1, or 2, in this embodiment, the gates 821, 822, 823, 824, 851, 852, 853, 854, 8591, 8592, 8593 and flip-flops 855, 856, 857 are used. 858, the number of program counters, that is, there are three sets, which are not shown.

  The second selection permission signal generation unit 9 is configured to permit the second selection permission to the program counter selection signal generation unit 10 based on the instruction decoding result by the instruction decoding unit 4 and the program counter selection signal from the program counter selection signal generation unit 10. Generate a signal. FIG. 12 is a block diagram showing an internal configuration of the second selection permission signal generation unit 9. Reference numerals 606, 607, 608, 609, and 610 are comparators included in the instruction decode unit 6, and 611, 612, 613, and 614 are gates (logical products) included in the instruction decode unit 6. Therefore, it is shown in FIG. Comparator 606 decodes the most significant 2 bits of the instruction to determine whether the instruction is a special instruction. If it is a special instruction, the special signal is asserted. Comparators 607, 608, 609, and 610 decode the upper 6 bits following the instruction, and the instruction is a suspend instruction (SuspendThread), a resume instruction (ResumeThread), a trigger wait suspend instruction (WaitTrigger), or a trigger generation instruction (EmitTrigger). It is determined whether each output signal is present, and each output signal is ANDed with a special signal by gates 611, 612, 613, and 614, thereby generating a SUSP signal, a RESU signal, a WAIT signal, and an EMI signal, respectively.

  Bits 23 to 8 of the instruction are identifiers indicating which program counter is to be suspended or resumed in the case of a suspend instruction or a resume instruction. In the present embodiment, since three program counters are provided, bit 10 To 8 are valid. Bit 8 (Inst [8]), bit 9 (Inst [9]), and bit 10 (Inst [10]) correspond to the program counters PC (0), PC (1), and PC (2), respectively.

  The logic for generating the selection permission signal by the suspend instruction and the resume instruction is explained below.

  The flip-flop 9-1 holds the operation state (execution state or suspend state) of PC (0), and the initial value at the time of reset is “1”, that is, indicates the execution state. When the suspend instruction is executed (SUSP = '1') and the program counter identifier indicates PC (0) (Inst [8] = '1'), the logical product output of the gate 9-2 is '1'. This drives the clear terminal of the flip-flop 9-1, and the output of the flip-flop 9-1 becomes '0'. That is, one factor for causing the program counter PC (0) to be in the suspended state is generated.

  On the other hand, when the resume instruction is executed (RESU = '1') and the program counter identifier indicates PC (0) (Inst [8] = '1'), the logical product output of the gate 903 is '1'. This drives the set terminal of the flip-flop 9-1, and the output of the flip-flop 9-1 becomes "1". That is, one factor that causes the program counter PC (0) to be executed is generated.

  Similarly, the flip-flop 904 is set or reset by the gates 905 and 906 according to the value of SUSP signal and RESU signal and Inst [9], and controls the execution state of the program counter PC (1).

  In exactly the same manner, the flip-flop 907 is set or reset by the gates 908 and 909 in accordance with the SUSP signal and the RESU signal and the value of Inst [10] to control the execution state of the program counter PC (2).

  Next, the logic for generating the selection permission signal by the trigger wait suspend instruction and the trigger generation instruction will be described.

  The flip-flop group 910 is composed of 8-bit flip-flops that hold a history of trigger generation by a trigger generation instruction, and the initial value at reset is “00000000”. When the trigger generation instruction is executed (EMIT = '1'), the gate 911 maintains the value as it is when the trigger is already held, and the trigger identifier Inst [23 when the trigger is not held. : 16] is loaded.

  The flip-flop 912 holds the operation state (execution state or suspend state) of PC (0), and the initial value at the time of reset is “1”, that is, indicates the execution state. When the trigger wait suspend instruction is executed (WAIT = '1') and the program counter selection signal from the program counter selection signal generator 10 indicates PC (0) (pc_sel [0] = '1'), the gate The logical product output of 913 becomes “1”. Further, the trigger history held by the flip-flop group 910 and the standby trigger identifier Inst [23:16] of the trigger wait suspend instruction are compared by the gates 914 and 915, and if there is no bit that is both “1” ( The output of the gate 915 = “0”), it is determined that a trigger has not been issued before the execution of the trigger wait suspend instruction, and a clear signal for the flip-flop 912 is generated by the gate 916. As a result, the output of the flip-flop 912 becomes “0”, and one factor that causes the program counter PC (0) to be in the suspended state is generated. At this time, the wait trigger identifier Inst [23:16] of the trigger wait suspend instruction is loaded into the flip-flop group 917. Note that the initial value when the flip-flop group 917 is reset is “00000000”. As a result of comparison by the gates 914 and 915, if there is a bit that is both “1”, it is determined that the trigger has been issued before the trigger wait suspend instruction is executed, and the flip-flop 912 is not cleared. That is, no transition is made to the suspended state (corresponding to claim 2).

  When the trigger generation instruction is executed (EMIT = '1'), the output of the trigger identifier Inst [23:16] and the flip-flop group 917 as the standby trigger is compared by the gates 918 and 919, and 1 bit is obtained. However, if there are both “1” bits, the output of the gate 920 becomes “1”. At this time, if the output of the flip-flop 912 is “0”, that is, the program counter PC (0) is in the suspended state, the flip-flop 912 is set by the gate 921 and one factor for causing the program counter PC (0) to be in the execution state. Generate. At the same time, the flip-flop group 910 is cleared and the trigger history is reset.

  The program counters PC (1) and PC (2) operate in exactly the same way as PC (0), and one factor is generated that causes the program counter to be in an execution state. 910 to 921 in PC (0) correspond to 922 to 934 in PC (1), respectively, and correspond to 934 to 945 in PC (2), respectively.

  A signal that controls the execution state of each program counter generated by the flip-flops 901, 904, and 907, and a signal that controls the execution state of each program counter generated by the flip-flops 912, 924, and 936, respectively. Are generated by the gates 947, 948, and 949 to form the second selection permission signal pc_en2 [2: 0] and output to the program selection signal generator 10.

  Based on the operation description of each block described above, the overall operation of the direct memory access device of the present embodiment will be described.

  First, an example of a general direct memory access operation that does not involve suspend and resume operations will be described with reference to a timing chart shown in FIG. Basically, the program indicated by the program counter PC (0) (instructions at addresses 0x03 and 0x05) transfers data to the direct memory access device 101, and the program indicated by the program counter PC (1) (instructions at addresses 0x12 and 0x16) ) Is set to perform data transfer of the direct memory access device 102.

  In clock cycle 0, the reset signal is asserted ("1") and is in a reset state. In the reset state, the program counter selection signal pc_sel outputs “001”, and the program counter selection permission signal pc_en outputs “111”. The initial values of the program counter are PC (0) = 0x0, PC (1) = 0x10, and PC (2) = 0x20. In clock cycle 1, the reset is released. First, the program counter PC (0) is selected (selected PC = PC (0)), and the instruction is executed. In clock cycle 2, pc_sel becomes “010” and PC (1) is selected, and in clock cycle 3, pc_sel becomes “100” and PC (2) is selected. In this way, PC (0) → PC (1) → PC (2) → PC (0) is sequentially selected and the instruction is executed. In clock cycle 4, the data transfer request DMAReq1 of the direct memory access device 102 is asserted ("1"). However, since the data transfer command for the device is not executed, the transfer response signal DMAAck1 is not asserted. In clock cycle 6, PC (1) becomes 0x12, and this program counter indicates a data transfer instruction to the direct memory access device 102. What is actually executed is clock cycle 8 in which pc_sel becomes “010” next, and DMAAck1 is asserted in this cycle.

  On the other hand, a data transfer instruction to the direct memory access device 101 indicated by the program counter PC (0) is issued in the clock cycle 10, but since DMAReq0 is not asserted in this cycle, the instruction indicated by the program counter PC (0) Execution is suppressed. That is, the value of pc_en is “110”, and PC (0) remains 0x03 and is not updated. Until the clock cycle 14 in which DMAReq0 is asserted, the programs indicated by the program counters PC (1) and PC (2) are executed in order. When DMAReq0 is asserted in clock cycle 14, pc_en is updated to "111", and PC (0) is selected and executed in clock cycle 15. That is, the transfer response signal DMAAck0 is asserted to complete the data transfer.

  In clock cycle 19, a data transfer instruction indicated by PC (1) = 0x16 is issued, but since DMAReq1 is not asserted in this cycle, pc_en becomes "101" and instructions indicated by PC (0) and PC (2) Are sequentially executed. In clock cycle 21 while execution of PC (1) is suppressed, a data transfer instruction indicated by PC (0) = 0x05 is issued. In this cycle, DMAReq0 is already executed because it is already asserted, and DMAAck0 Is asserted. When DAMReq1 is asserted in clock cycle 23, pc_en returns to "111", a data transfer instruction is executed in clock cycle 24, and DMAAck1 is asserted.

  As can be easily understood from the above description, when the data transfer request rate of each direct memory access device is two cycles, data transfer can be performed every clock cycle if two program counters are enabled. In other words, since the instruction decode unit and the data transfer execution unit can share data with the direct memory access device in an interleaved manner, it is possible to perform efficient data transfer without increasing the circuit scale. . In addition, since the memory address generation patterns of the two direct memory accesses can be set to be completely different, very flexible data transfer is possible. For example, if one program counter refers to image data in the x direction and the other program counter refers to data in the y direction, the rotation operation can be performed while performing data processing.

  Next, an operation example focusing on the suspend and resume operations will be described with reference to the timing chart shown in FIG.

  The operations from cycle 0 to cycle 7 are the same as the operations shown in FIG. 13 except that the data transfer request DMAReq1 is not asserted. In cycle 8, the instruction executed by the program counter PC (1) is a suspend instruction (SUSP0) for PC (0). As a result, in cycle 9, pc_en transits from “111” to “110”. Then, in cycle 10, if PC_en is "111", PC (0) that should have been executed is not executed, but the instruction of PC (1) is executed instead. In cycle 12, the program counter PC (1) executes an instruction (RESU0) for resuming PC (0). As a result, pc_en transits from “110” to “111” in cycle 13, and the instruction of PC (0) suspended in cycle 14 is executed.

  Next, in cycle 16, the program counter PC (2) waits for the trigger identifier 1 and executes an instruction to suspend itself, that is, a trigger wait suspend instruction (WAIT1). As a result, in cycle 17, pc_en transits from “111” to “011”. Then, in cycle 19, if PC_en is "111", PC (2) that should have been executed is not executed, but the instruction of PC (0) is executed instead. The instruction of PC (0) executed in this cycle 19 is a trigger generation instruction (EMIT1) that generates a trigger with a trigger identifier 1. As a result, in cycle 20, pc_en transitions from “011” to “111”. Then, in cycle 21, the suspended instruction of PC (2) is executed.

  Further, the instruction executed by PC (0) in cycle 22 is a trigger generation instruction (EMIT2) that generates a trigger with trigger identifier 2. Since there is no program counter suspended by the trigger wait suspend instruction at this time, “00000100” is loaded to the flip-flop groups 910, 922, and 934 in the second selection permission signal generation unit 9. In the cycle 24, the program counter PC (2) waits for the trigger identifier 2 and executes an instruction to suspend itself, that is, a trigger wait suspend instruction (WAIT2). Prior to the trigger wait suspend instruction (cycle 22), Since the identifier trigger generation instruction is executed, the trigger wait suspend instruction (WAIT2) in cycle 24 is invalidated, and pc_en remains "111". As a result, in the cycle 27, the instructions of the program counter PC (2) are executed in order.

  As can be easily understood from this description, one trigger generation instruction can resume two or more program counters in a suspended state by a trigger wait suspend instruction.

(Concrete example)
As an application example of the direct memory access device of this embodiment, a block diagram of a JPEG encoder device is shown in FIG. The JPEG encoder module 13 is applied as an actual example of the direct memory access device. A DMA port 701 is connected to the input section of the encoder module 13, and a DMA port 702 is connected to the output section. A memory-mapped storage 14 is connected to the CPU bus, and JPEG compressed data can be stored. In the case of such a configuration, the program counter PC (0) executes a sequence for reading image data from the memory 2 and inputting it to the JPEG encoder 13. The JPEG encoder 13 compresses input image data by JPEG, generates compressed code data having a data rate different from the data rate of the input data, and asserts a data transfer request. In response to this request, the program counter PC (1) is activated to transfer the code data to the memory 2. Since the access speed of the storage 14 may be slower than the memory 2, the sequence controlled by the program counter PC (2) transfers the code data to the storage 14 in the background using a double buffer. In such an operation, the program counter PC (0) loads and accesses the image data on the memory in units of 8 × 8 blocks, and the program counter PC (1) stores and accesses the code data to the continuous address, and the program counter The PC (2) loads and accesses the code data from the continuous address, and stores and accesses the fixed address which is the storage data port.

  What is important in data transfer as described above is the synchronization between data transfers. For example, the sequence controlled by the program counter PC (2) (transfer of the code data on the memory 2 to the storage 14) is controlled by the sequence controlled by the program counter PC (1) (the generated code data on the memory 2). Cannot be overtaken). In other words, data greater than the generated data should not be transferred to the storage. Conversely, the sequence controlled by the program counter PC (1) (transfer of the generated code data to the memory 2) must not generate / transfer data beyond the free capacity of the reserved memory area. . That is, code data should not be generated / transferred to a memory area that has not been transferred to the storage.

  FIG. 16 is a sequence diagram of the program counters PC (0), PC (1), and PC (2) for realizing the above-described double buffer synchronization control by the trigger wait suspend instruction and the trigger generation instruction. As for the program counter PC (0), if the code data output unit is stopped by suspending the program counter PC (1), the data transfer request signal of the image data input unit of the JPEG encoder 13 is not asserted, so that signal generation is performed. The program counter is automatically suspended by the action of the unit 8. The description of this operation is omitted from the sequence diagram.

  First, the default program counter PC (0) is activated, and the program counter PC (1) is enabled (ENABLE PC1). Next, direct memory access transfer for transferring the image data on the memory to the JPEG encoder 13 is executed according to the data transfer request signal ((1) in the sequence diagram).

  The activated program counter PC (1) transfers the code data generated by the JPEG encoder 13 to the memory area A according to the data transfer request signal ((2) in the sequence diagram). When the data transfer to the memory area A is completed, the program counter PC (2) is enabled (ENABLE PC2), and the code data generated by the JPEG encoder 13 is subsequently transferred to the memory area B in response to the data transfer request signal (sequence). (3) in the figure).

  When the program counter PC (2) is activated, it starts to transfer the code data in the memory area A to the storage 14 ((4) in the sequence diagram). When the program counter PC (1) completes the transfer of the code data to the memory area B, it issues a trigger generation instruction with the trigger identifier 0 (EMIT0). At this point, there is no program counter in the trigger wait suspend state. The program counter PC (1) continues to issue a trigger wait suspend instruction with a trigger identifier 1 (WAIT1) and transitions to the suspend state itself.

  When the program counter PC (2) finishes transferring the code data in the memory area A to the storage 14, it issues a trigger generation command for trigger identifier 1 (EMIT1), and then issues a trigger wait suspend command for trigger identifier 0. (WAIT0) tries to transition to the suspend state by itself, but since the trigger generation instruction with the trigger identifier 0 has already been issued by the program counter PC (1), the suspend is canceled and the code data in the memory area B is continuously stored. Transfer to the storage 14 is started ((5) in the sequence diagram).

  The suspended program counter PC (1) is resumed by the trigger of the trigger identifier 1 issued by the program counter PC (2), and the code data generated by the JPEG encoder 13 is transferred to the memory area A according to the data transfer request signal. (Sequence diagram (6)). When the program counter PC (2) finishes transferring the code data in the memory area B to the storage 14, the program counter PC (2) issues a trigger generation instruction for the trigger identifier 1 (EMIT1), and then issues a trigger wait suspend instruction for the trigger identifier 0. (WAIT0) transitions to the suspend state by itself.

  When the program counter PC (1) finishes transferring the code data generated by the JPEG encoder 13 to the memory area A in response to the data transfer request signal, the program counter PC (1) issues a trigger generation instruction for the trigger identifier 0 (EMIT0), and then triggers The trigger wait suspend instruction with identifier 1 is issued (WAIT1), and it tries to transition to the suspend state by itself, but the suspend is canceled because the trigger generation instruction with trigger identifier 1 has already been issued by the program counter PC (2). Subsequently, transfer of the code data generated by the JPEG encoder 13 to the memory area B is started in response to the data transfer request signal ((7) in the sequence diagram).

  The suspended program counter PC (2) is resumed by the trigger with the trigger identifier 0 issued by the program counter PC (1), and the transfer of the code data in the memory area A to the storage 14 is started ((8) in the sequence diagram). ).

  Similarly, transfer to the memory area A by the program counter PC (1) ((9) in the sequence diagram) and transfer from the memory area B by the program counter PC (2) ((10) in the sequence diagram) The memory areas A and B are sequentially accessed while being alternately synchronized.

  In the example of this sequence diagram, the transfer time of the code data to the memory area varies depending on the input image data, and on the other hand, the transfer time to the storage also varies depending on the status of the storage. It is uncertain which of the two transfers will end earlier. Even in such an example, by applying the present apparatus, it is possible to transfer data while using the double buffer to synchronize very easily.

  As described above, three types of data transfer each having a different data rate and access pattern can be executed while being synchronized in parallel according to each data transfer request. In addition, since the instruction decoding unit and the data transfer execution unit can be operated in a time-sharing manner, it is possible to realize efficient and complicated data transfer with an access pattern with a relatively small circuit scale.

  In the above embodiment, three program counters are provided in the DMA device. However, the present invention is not limited to this, and a DMA device provided with two or four or more program counters falls within the scope of the present invention. Can be included. However, it is desirable to provide more program counters than the number of DMA ports.

101, 102 ... Direct memory access device 2 ... Memory 301, 302, 303 ... Program counter 4 ... Program counter selection unit 5 ... Instruction memory 6 ... Instruction decode unit 601, 602, 603, 604, 605, 606, 607, 608, 609, 610... Comparators 611, 612, 613, 614... Gate 7... Data transfer execution unit 8. 801: Block for detecting the transfer source or destination from the output of the instruction decode unit 802: Block for detecting a data transfer request from the direct memory access device 803: The device issues a data transfer request Block 804... That outputs a signal for suppressing data transfer of the data transfer execution unit Block 805 ... Blocks for generating signals for deselecting the program counter 811, 812, 813, 814 ... Gates 821, 822, 823, 824 ... Gates 831, 832, 833, 834. ..Gate 841 ... Gates 851, 852, 853, 854 ... Gates 855, 856, 857, 858 ... Flip-flops 8591, 8592, 8593 ... Gate 9 ... Second selection permission signal generation Part 901, 9-4, 9-7, 912, 924, 936... Flip-flop 910, 917, 922, 929, 934, 941... Flip-flop group 902, 903, 905, 906, 908, 909 ..Gates 911, 913, 914, 915, 916, 918, 919, 920, 921 Gates 923, 925, 926, 927, 928, 930, 931, 932, 933 ... Gates 935, 937, 938, 939, 940, 942, 943, 944, 945 ... Gates 946, 947, 948,. Gate 10: Program counter selection signal generator 1001, 1002, 1003 ... Flip-flops 1004, 1005, 1006 ... Selector 1007 ... Decoder 1008, 1009, 1010 ... Gate 1100 ... Program Counter update unit 1101, 1102... Selector 1103... +1 adder 12.
13 ... JPEG encoder 14 ... Storage device

Claims (17)

In a direct memory access system having a direct memory access unit and a processor unit,
The processor unit is
Memory,
A processor that reads and executes an instruction from the memory to write an instruction to be executed by the direct memory access unit to the direct memory access unit;
The direct memory access unit
Multiple program counters,
Selecting means for sequentially selecting the plurality of program counters;
Instruction holding means for holding an instruction written by the processor;
Output means for outputting the instruction stored at the address of the instruction holding means indicated by the program counter selected by the selection means;
And an execution means for executing data transfer by direct memory access in accordance with an instruction output by the output means. When a request corresponding to the command is not output from the device related to the command output from the command holding unit by the output unit, execution of the command by the execution unit is suppressed and a corresponding request is not output 2. The direct memory access system according to claim 1, wherein the direct memory access unit further includes control means for restricting selection of the program counter indicating an instruction by the selection means. When the request corresponding to the content of the instruction output from the instruction holding means by the output means is output from the device, the control means includes a program counter for holding the instruction for which the corresponding request is output. When selection by the selection unit is permitted and a request corresponding to the content of the output command is not output from the device, a request corresponding to the content of the output command is output from the device 3. The direct memory access system according to claim 2, wherein the selection unit restricts selection of a program counter corresponding to the instruction. 4. When the instruction output from the instruction holding means by the output means is an interruption instruction that interrupts the program counter indicated by the instruction, the control means selects the program counter indicated by the interruption instruction by the selection means. If the instruction output from the instruction holding means is a restart instruction that restarts the program counter indicated by the instruction, the selection means permits the selection of the program counter indicated by the restart instruction. The direct memory access system according to claim 2 or 3, wherein The control means, when the instruction output from the instruction holding means by the output means is a trigger wait interruption instruction for interrupting the program counter indicated by the instruction until the trigger instruction indicated by the instruction is generated, When the trigger is not issued before the wait interruption instruction, the selection means limits the selection of the program counter indicated by the trigger wait interruption instruction, and when the trigger is issued before the trigger wait interruption instruction The direct memory access system according to claim 4, wherein selection of a program counter indicated by the trigger wait interruption instruction by the selection means is not limited. The execution means includes a register, and when the instruction output from the instruction holding means by the output means is a store instruction, the execution means transfers data held in the register to an external memory, and the output 6. The method according to claim 1, wherein when the instruction output from the instruction holding means by the means is a load instruction, the execution means transfers the data held in the external memory to the register. The direct memory access system according to item. When the instruction output from the instruction holding means by the output means is a loop instruction, the execution means repeatedly executes the instruction stored in the range indicated by the loop instruction by the instruction holding means. The direct memory access system according to any one of claims 1 to 6. 8. The direct memory access unit further includes a program counter update unit that updates a value of a program counter indicating an instruction related to the data transfer each time the execution unit executes data transfer. The direct memory access system according to any one of the above. 5. The direct memory access according to claim 4, wherein when the restart instruction is executed prior to an interruption instruction specifying a program counter indicated by the restart instruction, the execution unit invalidates the interruption instruction. system. The instruction holding means has a plurality of areas, stores an independent program in each of the plurality of areas,
The direct memory access system according to any one of claims 1 to 9, wherein the plurality of program counters count programs in different regions among the plurality of regions. The output means includes
11. The direct memory access system according to claim 1, wherein the instruction from the instruction holding unit is interpreted, and a signal indicating a processing content indicated by the instruction is output to the execution unit. . When the data transferred by the execution means is image data, the image data is referred to in the x direction by one of the plurality of program counters, and the image data is referred to in the y direction by one of the other program counters. The direct memory access system according to any one of claims 1 to 11, wherein the image data is rotated together with the data transfer by the execution means. The direct memory access system according to claim 2 or 3, wherein the device is an encoder for compressing data transferred by the execution means. In a direct memory access system having a direct memory access unit and a processor unit,
The processor unit is
Memory,
A processor that reads and executes an instruction from the memory to write an instruction to be executed by the direct memory access unit to the direct memory access unit;
The direct memory access unit
A double buffer having a first region and a second region;
Instruction holding means for storing a plurality of instructions;
Among the instructions stored in the instruction holding means, a first transfer instruction for transferring data from an external device to the first area or the second area, and a transfer indicating the transfer indicated by the first transfer instruction are completed. A first program counter sequentially indicating a 1 transfer completion instruction and a first interruption instruction that transitions to a suspended state until a second transfer completion instruction is issued;
Of the instructions stored in the instruction holding means, the second transfer instruction for transferring the data stored in the first area or the second area to the storage device and the transfer indicated by the second transfer instruction are completed. A second program counter sequentially indicating a second transfer completion instruction indicating a second interruption instruction that transitions to a suspended state until the first transfer completion instruction is issued;
If the instruction indicated by the first or second program counter is time-sharing processed and the first and second interruption instructions are processed, a transfer completion instruction corresponding to the first and second interruption instructions is not issued The corresponding program counter is shifted to the suspended state, and if the transfer completion instruction corresponding to the first and second suspension instructions is issued when the first and second suspension instructions are processed, the corresponding program counter is suspended. A direct memory access system comprising: an execution means that does not shift to a state. A third program counter indicating a third transfer instruction for transferring data processed by an external device to the external device, and a first activation instruction for activating the first program counter, among the instructions stored in the instruction holding means; In addition,
The first program counter indicates a second start instruction for starting the second program counter,
The execution means starts the first program counter and executes the second start instruction instead of the first transfer completion instruction when the first transfer instruction is executed. Direct memory access system. A processor unit including a memory and a processor that reads and executes an instruction from the memory to write an instruction to be executed by the direct memory access unit into the direct memory access unit;
A direct memory access system control method comprising: a plurality of program counters; and a direct memory access unit including an instruction holding unit that holds an instruction written by the processor,
A selection step of sequentially selecting the plurality of program counters;
An output step of outputting an instruction stored in an address of the instruction holding means indicated by the program counter selected in the selection step;
A control method for a direct memory access system, comprising: an execution step of executing data transfer by direct memory access in accordance with an instruction output in the output step. A processor unit including a memory and a processor that reads and executes an instruction from the memory to write an instruction to be executed by the direct memory access unit into the direct memory access unit;
A double buffer having a first area and a second area; an instruction holding means for storing a plurality of instructions; and instructions stored in the instruction holding means for receiving data from an external device in the first area or the second area A first transfer instruction to be transferred to the area, a first transfer completion instruction indicating that the transfer indicated by the first transfer instruction has been completed, and a first interruption that transitions to a suspended state until a second transfer completion instruction is issued A first program counter sequentially indicating instructions; a second transfer instruction for transferring data stored in the first area or the second area to a storage device among the instructions stored in the instruction holding unit; A second program count sequentially indicating the second transfer completion instruction indicating that the transfer indicated by the second transfer instruction has been completed, and a second interruption instruction that transitions to a suspended state until the first transfer completion instruction is issued. When a control method for a direct memory access system having a direct memory access unit and a running unit,
When the execution means processes the instruction indicated by the first or second program counter in a time-sharing manner and processes the first and second interruption instructions, a transfer completion instruction corresponding to the first and second interruption instructions is received. If not issued, the corresponding program counter is shifted to the suspended state, and if the first and second suspended instructions are processed, the transfer completion instruction corresponding to the first and second suspended instructions is issued. The direct memory access system control method is characterized in that the program counter to be executed is not shifted to the suspended state.

Images