JP2008234270A - Information processing device and controlling method of information processing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power saving type information processing device which makes detailed power control in command code units without using a part of command codes in power mode designation. <P>SOLUTION: The information processing device is provided with; an address converting part 30 which converts logical addresses to physical addresses; a command acquiring part 40 which refers to positions indicated by the physical address converted by the address converting part 30 to acquire command codes; a command interpreting part 42 which interprets the command codes acquired by the command acquiring part 40; a command executing part 50 which executes the commands interpreted by the command interpreting part 42; and a power controlling part 60 which controls power. The address converting part 30 not only executes the address conversion but also indicates power modes to the power controlling part, the power mode being to be applied when commands relating to command codes stored in positions which the address-converted physical addresses indicate, are executed. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

The present invention relates to an information processing apparatus having a low power consumption mode, and more particularly to an MMU (Memory).
The present invention relates to an information processing apparatus such as a CPU (Central Processing Unit) having a Management Unit.

By using part of the CPU instruction code for the purpose of specifying the power mode as a technology for automatically switching the power mode when the processor executes an instruction without executing the sequence for specifying the power mode each time. There is a technology that realizes switching of power modes in accordance with CPU instruction execution (see Patent Document 1).
JP 2003-196085 A

  2. Description of the Related Art Conventionally, it is required to reduce power consumption in a built-in microprocessor, particularly in a portable device, in order to extend the life of a battery that is a power source. In stationary devices as well, heat generation from processors has become a problem in recent years, and it is also required to reduce power consumption.

  Here, generally, the power consumption of the processor tends to increase in accordance with the execution speed of the processor. Also, in normal equipment use, it is not necessary for the embedded processor to always operate at maximum speed. Therefore, power consumption can be reduced by switching the power mode (operating frequency and operating voltage) to a power mode such as high speed and high power consumption, or low speed and low power consumption according to the situation. Is possible.

  More specifically, the processor may operate at a low speed in a state where there is no instruction from the user after the system is started, for example, in a state where the input of an instruction by pressing a button or the like is waited. In this case, power consumption can be suppressed by setting a power mode that is low speed and low power consumption. On the other hand, when an instruction input from the user occurs, for example, when an input for instructing the operation of the application program such as pressing of an application start button is performed, the processor operates at high speed and consumes a large amount of power. By setting the mode, you can achieve the performance required for the system.

  Conventionally, switching of the power mode that affects the speed and power consumption is realized by controlling the power management unit with software. However, in this method, it is necessary to execute a sequence for switching the power mode every time control is required, and it is difficult to perform fine power control (for example, switching the power mode for each application).

  In addition, as a method for switching the power mode without software control, there is a method in which a part of the instruction code of the CPU is used for specifying the power mode (see Patent Document 1). However, in this method, since the power mode is specified using a part of the field of the instruction code, it is necessary to develop a CPU having a completely new instruction set and cannot be applied to a CPU having an existing instruction set. For this reason, it is necessary to newly develop both the OS (Operating System) and applications for the software to be executed. It is also necessary to newly develop software development tools (assembler, compiler, etc.) used for this development. is there.

  In view of the above-described problems, the present invention has an object to provide a low power consumption information processing apparatus capable of performing fine power control without using a part of an instruction code for the purpose of specifying a power mode. To do.

  In order to solve the above-described problem, the present invention specifies the power mode corresponding to the converted physical address and controls the power of the information processing apparatus along with the address conversion when acquiring the instruction code. Therefore, it is possible to provide a low power consumption information processing apparatus capable of performing fine power control without using a part of the instruction code for the purpose of designating the power mode.

  Specifically, the present invention includes an address conversion unit that converts a logical address into a physical address, an instruction acquisition unit that acquires an instruction code by referring to a position indicated by the physical address converted by the address conversion unit, An instruction interpreter that interprets an instruction code acquired by the instruction acquirer; an instruction execution unit that executes an instruction interpreted by the instruction interpreter; and a power controller that performs power control, the address conversion In addition to the address conversion, the unit instructs the power control unit to determine a power mode to be applied when an instruction related to the instruction code stored at the position indicated by the address-converted physical address is executed. This is an information processing apparatus.

  An information processing apparatus according to the present invention is an information processing apparatus that acquires an instruction code (instruction fetch), interprets the acquired instruction code (instruction decode), and executes the interpreted instruction. In addition, this information processing apparatus employs virtual addresses for address designation, and performs address conversion from logical addresses to physical addresses when acquiring instruction codes. According to the present invention, in accordance with this address conversion, a power mode to be applied when an instruction indicated by the converted physical address is executed is specified, and the power of the information processing apparatus is controlled. .

  Here, the power mode indicates a method for controlling the power consumption of the information processing apparatus. The power control unit controls the power consumption of the information processing apparatus by switching the power supply voltage or the clock frequency, for example. However, the objects controlled to control the power consumption are not limited to the power supply voltage and the clock frequency. All targets that affect the power consumption of the information processing apparatus can be controlled by the power control unit.

  In addition, the information processing apparatus according to the present invention should be applied when an instruction related to a correspondence relationship between a logical address and a physical address and an instruction code stored at a position indicated by the physical address and the physical address is executed. A storage unit configured to store a correspondence relationship with the power mode, wherein the address conversion unit refers to the storage unit to instruct the power control unit according to the address conversion and the power mode; May be.

  In this case, the address conversion unit performs address conversion based on the correspondence relationship between the logical address and the physical address stored in the storage unit, and further specifies the power mode based on the correspondence relationship between the physical address and the power mode.

  In the present invention, the storage unit stores a conversion table in which a correspondence relationship between a logical address and a physical address and a correspondence relationship between a physical address and a power mode are recorded, and the address conversion unit By referring to the conversion table, an instruction may be given to the power control unit according to the address conversion and the power mode.

In this case, the address translation unit identifies an entry in the translation table based on the logical address that is the target of address translation, and extracts a physical address and a power mode corresponding to the logical address from this entry.

  Further, in the present invention, the storage unit is a logical address register that holds a logical address, and a register that is paired with the logical address register, the physical address that holds a physical address and a power mode corresponding to the physical address. The address conversion unit may instruct the power control unit according to the address conversion and the power mode by referring to the logical address register and the physical address register.

  In this case, the address conversion unit specifies a logical address register holding a logical address to be subjected to address conversion, and acquires a physical address and a power mode from the physical address register paired with the logical address register.

  According to the present invention, it is possible to provide a low power consumption information processing apparatus capable of performing fine power control without using a part of an instruction code for specifying a power mode.

  An embodiment of an information processing apparatus according to the present invention will be described with reference to the drawings.

<Configuration>
FIG. 1 is a diagram showing a principle configuration of an information processing apparatus 1 in the present embodiment. The information processing apparatus 1 includes a bus interface 20 connected to the main memory 80 and the like via the external bus 70, an address conversion unit 30, an instruction unit 40 (corresponding to an instruction acquisition unit and an instruction interpretation unit of the present invention), An execution unit 50 (corresponding to an instruction execution unit of the present invention) and a power control unit 60 are provided.

  The instruction unit 40 includes an instruction register 41 that stores the fetched instruction code, and an instruction decoder 42 that decodes the instruction code stored in the instruction register and generates a control signal 43 for the execution unit 50. Further, the instruction unit 40 passes the logical address of the instruction code to be executed next to the address conversion unit 30.

  The address conversion unit 30 corresponds to a so-called MMU, and monitors access to the main memory 80. Further, in the present embodiment, the address conversion unit 30 refers to the storage unit 31 to identify a physical address corresponding to the logical address passed from the instruction unit 40, and performs address conversion from the logical address to the physical address. Do. Then, the address conversion unit 30 accesses the main memory 80 via the bus interface 20 and the external bus 70 and reads the instruction code stored in the physical address output from the address conversion unit 30. The read instruction code is stored in the instruction register 41 via the bus interface 20 and the address conversion unit 30.

  The execution unit 50 is based on a control signal 43 generated by the instruction decoder 42 and includes various hardware such as a register 51 and an ALU (Arithmetic and Logical Unit) 52 connected via the internal bus 53 in the execution unit 50. The instruction indicated by the instruction code is executed by controlling the operation.

The power control unit 60 controls the clock frequency, the power supply voltage, and the like based on the power mode designation signal 61 to control the power inside the information processing apparatus 1. Here, the power mode designation signal 61 is generated by the address conversion unit 30. When performing address conversion, the address conversion unit 30 refers to the storage unit 31 to identify a power mode and generates a power mode designation signal 61. The target controlled by the power control unit 60 for reducing power consumption is not limited to the clock frequency and the power supply voltage.

  FIG. 2 is a diagram more specifically showing the configuration of the information processing apparatus in the present embodiment. Here, the components corresponding to the components shown in FIG.

  In this embodiment, a segment method is adopted as a method for realizing a virtual address. The segment table 81 is a table in which 4096 entries are collected as 32 bit entries in which information for associating logical addresses with physical addresses is recorded, and is stored in the main memory 80.

  The conversion table base register 32 is a register that holds the start address of the segment table 81 (see FIG. 3). The address conversion unit 30 accesses the segment table 81 in the main memory 80 by referring to the conversion table base register 32.

  A TLB (Translation Look-aside Buffer) 311 (corresponding to the storage unit 31 shown in FIG. 1) is a buffer that extracts a part of the contents of the segment table 81 and holds it as a cache for the purpose of speeding up the address conversion process. is there. In this embodiment, the TLB 311 has eight cache areas each having a 32-bit length.

  FIG. 3 is a diagram showing the configuration of the segment table 81 and logical addresses in the present embodiment.

  The segment table 81 is a table in which information for associating a logical address with a physical address is recorded. The segment table 81 is a set of entries that hold the upper part of the physical address of each segment. For the purpose of converting a logical address into a physical address for each segment and designating a cache mode, access control, and power mode for the segment. Used. In the present embodiment, it is assumed that the physical address upper part of the segment is recorded in the physical address upper field 811 (bit 31 to bit 20) of the entry. Each entry has a cache mode designation field (bit 19 to bit 16) 812 for designating a cache mode for each segment (instruction cache ON / OFF, data cache OFF / Write Through / Copy Back, etc.) 812, access permission for each segment (Read enable / disable, Write enable / disable, execute enable / disable) access control field (bit 15 to bit 8) 813, unused reserved field (bit 7 to bit 4), and power mode specification field ( Bit 3 to bit 0) 814.

  Bits 31 to 20 of the logical address are entry designation fields indicating entry numbers in the segment table 81. The address conversion unit 30 refers to this entry designation field and identifies the segment to which the logical address corresponds. Bits 19 to 0 indicate an intra-segment offset (lower physical address). That is, the entry of the corresponding segment is identified from the segment table 81 based on the entry number, and the 32-bit length obtained by concatenating the upper 12 bits of the physical address of the corresponding segment set in this entry and the 20 bits of the intra-segment offset The value of is a physical address.

A configuration characterizing the segment table 81 according to the present embodiment is a power mode designation field 814. In the power mode designation field 814, a power mode designated by the power control unit 60 while the program in the corresponding segment is being executed is set.

  FIG. 4 is a diagram illustrating the meanings of specific values set in the power mode designation field 814 in the present embodiment. In the present embodiment, the field length of the power mode designation field 814 is 4 bits, of which 2 bits are used as a field for controlling the power supply voltage and the remaining 2 bits are used as a field for controlling the clock frequency. In this embodiment, four values that can be expressed using a 2-bit area for each of the power supply voltage and the clock frequency are assigned to three modes of High, Middle, and Low, and the remaining one value is not used. . However, the size of the power mode designation field 814, the object controlled by the value set in the power mode designation field 814, and the content of the control are not limited to those shown in the present embodiment.

<Process flow>
At the time of system initialization, the OS performs setting for associating a physical address with a logical address for each program such as an OS kernel, an interrupt handler, and each application. Even after the system initialization is completed, every time a program such as an application is started, the OS secures an area in which the program is loaded on the main memory 80, and associates a physical address and a logical address in this area. Set up. At this time, the OS in this embodiment sets the power mode to be selected when each program is executed, together with the setting of the correspondence between the physical address and the logical address.

  This power mode is set according to the contents of the system parameter set by the user at the time of system generation, for example. The system parameter has a configuration that can specify a power mode for each program to be executed. For example, a table for designating the power mode for each program may be held as a system parameter, and the power mode for each program may be set according to this table. The process priority and the power mode assigned to this priority May be held as system parameters, and the power mode for each program may be set according to the priority of the process.

  FIG. 5 is a flowchart showing the flow of the segment table setting process when the OS starts the program in the present embodiment. The processing shown in this flowchart is started when an instruction to start the program is given by an input from the user or a call from another program.

  In step S101, a memory area for loading the program is secured. The information processing apparatus 1 secures a memory area (segment) corresponding to the size of the program, associates the physical address and logical address of this area, and sets this correspondence in the physical address upper field 811 of the segment table 81. Thereafter, the process proceeds to step S102.

  In step S102, the program is loaded into the main memory 80. The information processing apparatus 1 reads a program from an auxiliary storage device or the like (not shown) connected to the external bus 70, and expands (loads) the program in the memory area secured in step S101. Thereafter, the process proceeds to step S103.

In step S103, the power mode corresponding to the program is determined. The information processing apparatus 1 determines the power mode when the program is executed with reference to the OS setting area, the contents of the program, and the like. Specifically, it is determined whether the power supply voltage is High, Middle, or Low, and whether the clock is High, Middle, or Low. As a method for determining the power mode at the time of program execution, a power mode adopted for each program is set in advance in the OS setting area, and a method for referring to this is stored or stored in the program in advance. There are a method of determining by referring to information, a method of determining and determining which power mode the OS adopts based on the type of program, and the like. Thereafter, the process proceeds to step S104.

  In step S104, the power mode is set. The information processing apparatus 1 sets the power mode determined in step S103 in the power mode designation field 814 of the segment table 81. Thereafter, the process proceeds to step S105.

  In step S105, the program is activated. The information processing apparatus 1 starts executing the program loaded in the main memory 80. Thereafter, the processing shown in this flowchart ends.

  FIG. 6 is a flowchart showing the flow of the power mode designation process in the present embodiment. When the instruction is executed, the information processing apparatus 1 performs an instruction fetch while performing an address conversion process in the address conversion unit 30. At this time, in parallel with the instruction fetch, the information processing apparatus 1 specifies the power mode set for the segment to which the instruction belongs, and passes the power mode designation signal 61 to the power control unit 60, thereby Take control. The details of the flow of the power mode designation process will be described below with reference to the flowchart.

  In step S201, the logical address of the instruction code is passed to the address conversion unit 30. The instruction unit 40 passes the logical address indicating the storage position of the instruction code to be executed next to the address conversion unit 30. Thereafter, the process proceeds to step S202.

  In step S202, it is determined whether or not an entry for address translation exists in the TLB 311. The address conversion unit 30 determines whether or not the entry cache for converting the logical address passed from the instruction unit 40 into the physical address in the TLB 311 in the address conversion unit 30 in step S201. If the TLB 311 has a cache of the corresponding entry, the process proceeds to step S204. If the TLB 311 does not have a cache for the entry, the process proceeds to step S203.

  In step S203, the corresponding entry is acquired from the segment table 81. The address conversion unit 30 accesses the head address of the segment table 81 recorded in the conversion table base register 32, and selects an entry indicated by the entry designation field of the logical address. The selected entry is read out by a hardware table walk mechanism (not shown) in the address conversion unit 30 and stored in the TLB 311.

  In step S204, address conversion is performed. The address conversion unit 30 acquires the physical address upper part of the corresponding segment from the TLB 311 and specifies the physical address by concatenating with the intra-segment offset in the logical address. Thereafter, the process proceeds to step S205.

  In step S205, the power mode is designated. The address conversion unit 30 identifies the power mode setting corresponding to the segment by referring to the power mode designation field 814 of the entry referenced in step S203, and outputs the power mode designation signal 61 based on the identified power mode. The generated power mode designation signal 61 is passed to the power control unit 60. Thereafter, the process proceeds to step S206.

In step S206 to step S208, instruction fetch, instruction decode, and instruction execution are performed. The instruction unit 40 reads the instruction code from the physical address specified in step S204 and writes it in the instruction register 41 (step S206). Next, the instruction decoder 42 decodes the instruction code written in the instruction register 41, generates a control signal 43, and passes it to the execution unit 50 (step S207). Then, the execution unit 50 including the register 51, the ALU 52, and the like executes the instruction indicated by the instruction code by operating based on the control signal 43 (step S208). Thereafter, the processing shown in this flowchart ends.

  In other words, in the present embodiment, the power mode is specified together with the address conversion accompanying the instruction fetch, and the power mode designation signal 61 is passed to the power control unit 60. The power control unit 60 controls the power supply voltage control circuit 62 and the clock control circuit 63 in accordance with the power mode indicated by the power mode designation signal 61 (for example, switching control of a frequency dividing circuit provided in a PLL (Phase-Locked Loop)). The power supply voltage and clock frequency supplied to the information processing apparatus 1 are switched.

<Effect>
In the present embodiment, at the time of the address conversion process, the power mode to be selected by each program is specified at the same time, and the power control unit 60 executes the switching of the power mode. That is, according to the present embodiment, it is not necessary to designate a power mode each time an individual program is executed, and the information processing apparatus 1 can be operated in an optimum power mode prepared in advance only by executing each program. It becomes possible. This power mode can be switched at least for each program portion, such as a segment unit. Further, according to this embodiment, the power mode can be set when a physical memory area for loading a program to be executed is secured.

  Further, the information processing apparatus 1 according to the present embodiment does not need to prepare a CPU having a new instruction set. That is, the information processing apparatus 1 according to the present embodiment can execute existing software (OS, application program, etc.). When a CPU having an existing instruction set is adopted, the existing binary can be used as it is without recompiling the program. This also means that software development tools (assembler, compiler, etc.) can use existing products. Of course, the present invention can be applied to a CPU having a new architecture.

<Others>
In the above-described embodiment, the segment method is employed as a method for realizing the virtual address. However, the present invention can also be applied to an information processing apparatus that employs a paging method that uses a page table. Further, the table reference method at the time of address conversion is not a one-stage system as in the above-described embodiment, but may be a system in which addresses are converted by referring to a table of a plurality of stages. In addition, the address conversion method may be an address map register format including registers that hold a logical address and a physical address in pairs, instead of the table reference method.

  The power control unit 60 may control the power of the entire information processing apparatus such as an LSI as in the above-described embodiment, but controls the power individually for each block included in the information processing apparatus. It is good. In this case, by extending the size of the power mode designation field, a different power mode can be designated for each block.

Further, the present invention includes the following additional items.
(Appendix 1)
An address conversion unit that converts a logical address into a physical address;
An instruction acquisition unit that acquires an instruction code by referring to a position indicated by the physical address converted by the address conversion unit;
An instruction interpretation unit for interpreting the instruction code acquired by the instruction acquisition unit;
An instruction execution unit for executing an instruction interpreted by the instruction interpretation unit;
A power control unit for performing power control;
With
In addition to the address conversion, the address conversion unit indicates to the power control unit a power mode to be applied when an instruction related to an instruction code stored at a position indicated by the physical address subjected to the address conversion is executed. An information processing apparatus characterized by: (1)
(Appendix 2)
A memory for storing a correspondence relationship between a logical address and a physical address, and a correspondence relationship between a physical address and a power mode to be applied when an instruction related to an instruction code stored at a position indicated by the physical address is executed Further comprising
The information processing apparatus according to claim 1, wherein the address conversion unit performs an instruction to the power control unit according to the address conversion and the power mode by referring to the storage unit. (2)
(Appendix 3)
The storage unit stores a conversion table in which a correspondence relationship between a logical address and a physical address and a correspondence relationship between a physical address and a power mode are recorded,
The information processing apparatus according to appendix 2, wherein the address conversion unit performs an instruction to the power control unit according to the address conversion and the power mode by referring to the conversion table. (3)
(Appendix 4)
The storage unit includes a logical address register that holds a logical address, and a physical address register that is paired with the logical address register and holds a physical address and a power mode corresponding to the physical address,
The address conversion unit performs an instruction to the power control unit according to the address conversion and the power mode by referring to the logical address register and the physical address register. Information processing device. (4)
(Appendix 5)
The power control unit controls power consumption of the information processing apparatus by switching a power supply voltage or a clock frequency.
The information processing apparatus according to any one of appendix 1 to appendix 4.
(Appendix 6)
An address conversion step for converting a logical address into a physical address;
An instruction acquisition step of acquiring an instruction code by referring to a position indicated by the physical address converted in the address conversion step;
An instruction interpreting step for interpreting the instruction code acquired in the instruction acquiring step;
An instruction execution step for executing the instruction interpreted in the instruction interpretation step;
A power control step for performing power control;
With
In the address conversion step, in addition to the address conversion, determine the power mode to be applied when the instruction related to the instruction code stored at the position indicated by the physical address subjected to the address conversion is executed,
In the power control step, the power is controlled according to the power mode. (5)

It is a figure which shows the principle structure of the information processing apparatus in embodiment. It is a figure which shows more concretely the structure of the information processing apparatus in embodiment. It is a figure which shows the structure of the segment table and logical address in embodiment. It is a figure which shows the meaning of the specific value set to the electric power mode designation | designated field in embodiment. It is a flowchart which shows the flow of the segment table setting process at the time of OS starting a program in embodiment. It is a flowchart which shows the flow of the electric power mode designation | designated process in embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Information processing apparatus 20 Bus interface 30 Address conversion part 31 Memory | storage part 32 Conversion table base register 40 Instruction unit 41 Instruction register 42 Instruction decoder 43 Control signal 50 Execution unit 51 Register 52 ALU (Arithmetic and Logical Unit)
53 Internal Bus 60 Power Control Unit 61 Power Mode Specification Signal 62 Power Supply Voltage Control Circuit 63 Clock Control Circuit 70 External Bus 80 Main Memory 81 Segment Table

Claims (5)

An address conversion unit that converts a logical address into a physical address;
An instruction acquisition unit that acquires an instruction code by referring to a position indicated by the physical address converted by the address conversion unit;
An instruction interpretation unit for interpreting the instruction code acquired by the instruction acquisition unit;
An instruction execution unit for executing an instruction interpreted by the instruction interpretation unit;
A power control unit for performing power control;
With
In addition to the address conversion, the address conversion unit indicates to the power control unit a power mode to be applied when an instruction related to an instruction code stored at a position indicated by the physical address subjected to the address conversion is executed. An information processing apparatus characterized by: A memory for storing a correspondence relationship between a logical address and a physical address, and a correspondence relationship between a physical address and a power mode to be applied when an instruction related to an instruction code stored at a position indicated by the physical address is executed Further comprising
The information processing apparatus according to claim 1, wherein the address conversion unit instructs the power control unit according to the address conversion and the power mode by referring to the storage unit. The storage unit stores a conversion table in which a correspondence relationship between a logical address and a physical address and a correspondence relationship between a physical address and a power mode are recorded,
The information processing apparatus according to claim 2, wherein the address conversion unit instructs the power control unit according to the address conversion and the power mode by referring to the conversion table. The storage unit includes a logical address register that holds a logical address, and a physical address register that is paired with the logical address register and holds a physical address and a power mode corresponding to the physical address,
3. The address conversion unit performs an instruction to the power control unit according to the address conversion and the power mode by referring to the logical address register and the physical address register. Information processing device. An address conversion step for converting a logical address into a physical address;
An instruction acquisition step of acquiring an instruction code by referring to a position indicated by the physical address converted in the address conversion step;
An instruction interpreting step for interpreting the instruction code acquired in the instruction acquiring step;
An instruction execution step for executing the instruction interpreted in the instruction interpretation step;
A power control step for performing power control;
With
In the address conversion step, in addition to the address conversion, determine the power mode to be applied when the instruction related to the instruction code stored at the position indicated by the physical address subjected to the address conversion is executed,
In the power control step, the power is controlled according to the power mode.

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