JPH11338735A - System lsi - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a system LSI equipped with a function capable of accessing respective block parts at high speed by acquiring the operating states of respective block parts through a processor core. SOLUTION: A processor core 4 is provided with a state supervisory and control register composed of state bits for reading and storing operation information stored in a peripheral control register at each part inside a peripheral block part 9 and a system LSI 1 acquires and controls changes in the processing states of respective parts inside the peripheral block part 9 while referring to the contents of the state supervisory corresponding to the execution of a control register transfer instruction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system which comprises a processor core for controlling the entire system and a peripheral block for controlling various exclusive controls, and performs high-speed communication between the processor core and the peripheral block. It relates to an LSI.

[0002]

2. Description of the Related Art In a computer system, when data communication is performed between a central processing unit (CPU) and an input / output device, it is determined whether or not the CPU can execute the next input / output operation. The polling method of making a determination by periodically checking the status bits of the above, and the interrupt method of informing the CPU of the timing at which the input / output processing should be started by the input / output device side are conventionally used. As a matter of course, the operating speed of the CPU is much higher than that of the input / output device.
This wastes a lot of PU time. Further, in the case of the interrupt method, it is necessary to hold the state of the CPU before the interrupt every time the interrupt processing occurs, so that overhead such as saving and restoring various register values occurs.

[0003] In recent years, the technological innovation of semiconductor processes has been remarkable, and a computer system which has conventionally been constituted by a plurality of LSIs has been integrated into a single LSI. By the improvement of the integration technology, a processor core for controlling the entire system, dedicated hardware for performing various dedicated processes, and a large-capacity memory for storing instructions and data can be integrated in a single LSI. Integrated system LSIs have been commercialized and widely supplied to the market.

In these system LSIs, by providing a host interface (I / F), a host processor manages the entire system including the system LSI, and dedicated hardware incorporated in the system LSI becomes independent. Then, when the processing of the own block is completed, control is performed such that the whole block is controlled by activating the next block. Further, even when the CPU in the system LSI performs overall control, transmission of information for notifying the completion of processing of peripheral dedicated hardware is performed based on conventional interrupt processing and polling processing.

FIG. 24 is a block diagram showing the basic configuration of a conventional system LSI. In the figure, reference numeral 1000 denotes a system LSI, which includes a processor core 1001, an internal instruction RAM 2, an internal data RAM 3, a system bus I
/ F 1002 and a peripheral block unit 1003.

Next, the operation will be described. An instruction address bus 20 for transmitting an instruction address output from the processor core 1001 is connected to the internal instruction RAM 2 and the system bus I / F 1002. A data address bus 21 for transmitting a data address output from the processor core 1001 is connected to the internal data RAM 3.

When the access-symmetric data area is for the system bus I / F 1002 and the peripheral block 1003, the data address is output to the system bus I / F 1002 and the peripheral block 1003 via the address bus 26. The data specified by the address is transferred via the data bus 27.

The peripheral block unit 1003 has a built-in status register 1004 indicating a processing status, and the contents of the status register 1004 can be read from the processor core 1001 via the above-mentioned address bus 26 and data bus 27. . Further, an interrupt signal 1005 is output from the peripheral block unit 1003 to the processor core 1001. In the processor core 1001, when the interrupt signal 1005 becomes active, the interrupt control unit 1006 starts interrupt processing, and the processor The core 1001 operates.

The processor core 1001 has an internal instruction RA
An instruction address is output to M2 and the system bus I / F 1002 via the instruction address bus 20. If the instruction address is transmitted to the system bus I / F 1002, the system bus I / F unit 1010
02 fetches an instruction code from an external memory (not shown) through the bus 50 and transfers the instruction code to the processor core 1001 through the bus 24.

When the instruction address bus 20 is for the internal instruction RAM 2, the internal instruction RAM 2
Transfers the instruction code to the processor core 1001 through the bus 23. The processor core 1001 is connected to the bus 23
And the bus 24 is selected, and an instruction code to be processed next is obtained through the bus 25.

The instruction code transferred into the processor core 1001 is decoded, the operation execution unit is controlled based on the decoded result, and the operation target data is read from a general-purpose register (not shown). Then, the operation execution result is stored in the general-purpose register. If the data for the operation does not exist in the general-purpose register, the internal data RAM 3 is accessed through the data address bus 21 and the necessary data is obtained through the bus 22. Alternatively, the system bus I / F 1002 is accessed through the address bus 26. The system bus I / F 1002 transfers necessary data to the processor core 1001 through the data bus 27 after obtaining necessary data from an external memory via the bus 50.

The operation result is stored in an external memory (not shown).
When it is desired to store the information in the processor core 1001,
An address and data are transmitted to the system bus I / F 1002 through each of the buses 26 and 27. System bus I / F 1002 receiving these addresses and data
Stores data as a calculation result in a target address area in the external memory through the bus 50.

As described above, the processor core 1001 causes the peripheral block unit to execute various dedicated processes while executing the target application. At this time, the processor core 1001 writes a command into a control register (not shown) in the peripheral block unit 1003, and starts the processing of the peripheral block unit 1003. Peripheral block part 1
In step 003, the progress of the process activated by the processor core 1001 is written in the built-in status register 1004. In other words, data necessary for processing is fetched from the internal data RAM 3 via the processor core 1001, the processed data is processed, and then stored in the internal data RAM 3.

Normally, data transfer performed between the peripheral block unit 1003 and the internal data RAM 3 is performed independently of the operation of the processor core 1001. This data transfer is performed by Direct Memory Acc.
This is called ess (DMA) transfer.

The processor core 1001 performs necessary processing at any time while reading data stored in the status register 1004, that is, while performing polling processing. Thus, the peripheral block unit 10
03 incorporates the status register 1004 because the peripheral block unit 1003 can have accurate temporal and status information. The peripheral block unit 10
In 03, the interrupt signal 1005 is activated when the processing started by the processor core 1001 is completed. Upon receiving this interrupt signal, the interrupt control unit 1006 in the processor core 1001 activates the interrupt processing, and the processor core 1001 executes the interrupt processing.

FIG. 25 shows a processor core 1001, an internal instruction RAM 2 and an internal data RAM 3, a peripheral block section 1003 and a system bus I / F 1002.
FIG. 3 is a block diagram illustrating a transfer circuit that transfers addresses and data between the transfer circuits. Conventional system LSI shown in FIG.
As described with reference to 1000, the processor core 1001 and the internal instruction RAM 2 are connected via the instruction address bus 20 and the data bus 22,
2 are output to the processor core 1001 via the bus 23.

The processor core 1001 and the internal data RAM 3 are connected via a data address bus 21 and a data bus 22. The processor core 1001 and the peripheral block unit 1003 are connected via an address bus 26 and a data bus 27.

In order to execute an instruction fetch, an instruction address held in the instruction register 30 is output to the instruction address bus 20 via a selector 88 in the processor core 1001. When receiving the instruction address held in the instruction register 30 via the instruction address bus 20, the internal instruction RAM 2 outputs the instruction code stored in the address specified by the instruction address onto the bus 23.

In the conventional system LSI 1000, instruction fetch is processed in units of 64 bits.
Once the instruction fetch is executed, the incrementer 31
Adds 8 to the value of the instruction address, and the added instruction address is used for the next instruction fetch. The data address added by the adder 33 for address calculation is output to the data address bus 21 for performing data access via the latches 34 and 35 and the three-state buffer 66. When the data access is a data read process, the internal data RAM 3
Desired data is transferred to the bus 22 via the state buffer 62.
Output to the top.

The processor core 1001 fetches data from the bus 2 via the sign extension unit (OP4) 37.
If the data access is a data write process, the processor core 1001
5) The data is output onto the bus 22 via the 36 and the 3-state buffer 39. And the internal data RAM 3
The data on the bus 22 is stored in a storage area indicated by a predetermined address via the three-state buffer 63.

The address data on the data address bus 21 is not only output to the internal data RAM 3 but also
It is also output to the bidirectional buffer unit 1020 to access the peripheral block unit 1003. The output data address is output to the address bus 26 connected to the peripheral block unit 1003 via the three-state buffer 1022. When the data access to the peripheral block unit 1003 is a data read process for a control register or the like, the data stored in the state register 1004 read via the bus 27 is transferred to the bus 22 via the three-state buffer 1024. Output to

The processor core 1001 fetches the data via the sign extension unit 37 inside the processor core 1001. If the data access to the peripheral block unit 1003 is a data write process to a control register or the like, the processor core 1001
The data output onto the bus 22 via the 6- and 3-state buffers 39 is output onto the bus 27 via the 3-state buffer 1023 and stored in a predetermined control register.

When the processor core 1001 reads out an instruction code from the internal instruction RAM 2 as data or stores the instruction code in the internal instruction RAM 2, the data address is first transmitted via the path 87 and the selector 88. And outputs it to the internal instruction RAM2. And
If the access is a data read process, the bus 22
The instruction code output above is transferred to the three-state buffer 6
It is taken into the sign extension unit 37 via 0,65. Also,
When the access is a data write process, the instruction code output onto the bus 22 via the data integer value part 36 and the three-state buffer 39 is transferred to the three-state buffer 64,
61, and is stored at a predetermined position in the internal instruction RAM 2.

Further, when the peripheral block unit 1003 directly accesses an area in the internal data RAM 2, that is, in the case of a DMA transfer, the peripheral block unit 1003
After acquiring the right of the data address bus 21 and the data bus 22 from the processor core 1001 (right to use the bus freely and preferentially), the DMA transfer process is started.

The data address output from the peripheral block unit 1003 onto the address bus 26 is output onto the data address bus 21 via the three-state buffer 1021 and transferred to the internal data RAM 3. If the DMA transfer is a data read process, the internal data RAM 3
Are output onto the bus 22 via the three-state buffer 62 and are output onto the data bus 27 via the three-state buffer 1023 in the processor core 1001. The output data is transferred to the peripheral block unit 1003 via the data bus 27.

When the DMA transfer is a data write process, data output from the peripheral block unit 1003 to the data bus 27 is output to the bus 22 via the three-state buffer 1024. In the internal data RAM 3, data on the bus 22 is stored at a predetermined position via the three-state buffer 63. This DMA transfer is often used to transfer a large amount of data at a high speed, and usually accesses a continuous area in the internal data RAM 3. In that case, the peripheral block unit 1003 needs to output the address of the continuous area.

FIG. 26 shows a case where the processor core 1001 performs a read / write process on a control register (not shown) in the peripheral block unit 1003 and a case where the peripheral block unit 1003 performs DMA data transfer on the internal data RAM 3. 9 is a timing chart showing a case where a read / data write process is performed. In the figure, (a) shows a signal output from the processor core 1001 to the peripheral block unit 1003, (b) shows a signal output from the peripheral block unit 1003 to the processor core 1001, ( c) shows a signal output from the processor core 1001 to the internal data RAM 3.

When the processor core 1001 accesses a control register in the peripheral block unit 1003,
First, a control register request signal and a control register write signal, which are control signals, are output. When the control register write signal is at a low level (L level), it indicates that the access is a data read process. When the control register write signal is at a high level (H level), the access is a data write process. Indicates that

As shown in FIG. 26, the processor core 10
When 01 issues a control register read request at clock (1), the access address A1 is output on the data address bus 21 and immediately the access address A1 is output to the peripheral address bus 26.

The peripheral block unit 1003 receives the access address A1, reads data D1 from a control register (not shown) specified by the access address A1, and reads the data D1 onto the peripheral data bus 27 at a clock (3). The data D1 is output. This data D1
Is the clock (4) one clock after, and the data bus 22
Transferred up. The clocks (1) to (4) are the read period of the control register, and the processor core 100
1 stops its operation for three clock cycles (wait processing).

When the processor core 1001 issues a control register write request at clock (5), the access address A2 is output on the data address bus 21 and immediately the access address A2 is also output on the peripheral address bus 26. Is done. Also, during the same clock (5) period, the write data D2 is also transmitted to the data bus 22.
Output to the top.

The write data D2 is transferred onto the peripheral data bus 27 at a clock (6) after one clock. The peripheral block unit 1003 receives the address A2 and the data D2, and stores the data in a predetermined control register. The clocks (5) to (8) are the data write period for the control register, and the processor core 100
No. 1 stops its operation for three cycle periods (wait processing).

As described above, the processor core 1001
Control register (not shown) in peripheral block unit 1003
, The ordinary processor core 1001 needs to perform wait processing. Processor core 1001
While the internal control register and the internal data RAM 3 can be accessed at high speed, the access to the peripheral block unit 1003 must be performed at low speed. In other words, it is necessary to stop the operation of the processor core 1001 until the access to the peripheral block unit 1003 is completed, so that there is a problem that the processing cycle of the processor core 1001 is wasted.

The peripheral block 1003 stores the internal data R
When performing a DMA transfer to the AM 3, the peripheral block unit 1003 sends the DM to the processor core 1001.
Assert the A request signal.

When the address bus and the data bus inside and around the processor core are not used, the processor core 1001 generates and returns an acknowledge signal for the request signal. The period in which both the request signal and the acknowledge signal are asserted indicates that the peripheral block unit 1003 can perform DMA transfer.

The peripheral block unit 1003 outputs a DMA address valid signal and a DMA write signal one clock after receiving the DMA acknowledge signal transmitted from the processor core 1001. While the DMA address valid signal is asserted, the peripheral block unit 100
3 outputs the address incremented every clock to the peripheral address bus 26.

The peripheral block unit 1003 also asserts the DMA write signal. When the DMA write signal is at the L level, the peripheral block unit 1003 executes data read processing from the internal data RAM 3, and conversely, when the DMA write signal is at the H level. Performs a write process to the internal data RAM 3.

As shown in FIG. 26, the peripheral block unit A asserts a DMA request signal to the processor core 1001 at the clock (9), and outputs the DM request signal at the clock (10).
When the A acknowledgment signal is returned from the processor core 1001, the peripheral block unit A performs clock (11) to clock (11).
Until (16), the DMA address valid signal, the write signal, and the addresses A31 to A36 are output.

When the DMA write signal is at the L level, data read processing for the internal data RAM 3 is executed. That is, the address A on the peripheral address bus 26
31 to 36 are the data address bus 21 after one clock.
Transferred up. Data D31 to D31 for that address
36 is the data bus 22 according to the data RAM output signal.
The data is output to the peripheral data bus 27 after one clock.

The clocks (12) to (17) are a DMA read period for the internal instruction RAM 2 and the internal data RAM 3. Further, even if the peripheral block unit B asserts the DMA request signal to the processor core 1001 at the clock (12), the peripheral block unit A executes the DMA transfer.
The MA acknowledge signal is returned.

The peripheral block section B outputs a DMA address valid signal, a write signal, and addresses A41 to A45 from the clock (20) one clock after this. DM
Since the A write signal is at the H level, the internal data RAM
Is performed. That is, the peripheral address bus 2
6 are transferred to the data address bus 21 one clock later. Write data D41 to D45 are output onto the peripheral data bus 27 at the same time as the address.
2 is transferred.

The processor core 1001 outputs a data RAM write signal and stores the write data D41 to D45 in the internal data RAM3. As described above, in the DMA transfer processing, the processor core 1001 and the peripheral blocks A and B
Although a wait period occurs in the transfer of addresses and data between the two, a large amount of data can be accessed in a continuous memory area, and high-speed large-volume data transfer can be performed in parallel with the processing of the processor core 1001. .

FIG. 27 shows that the processor core 1001 reads the data stored in the status register 1004 in the peripheral block unit 1003 and monitors the progress of processing.
That is, it is a timing chart showing the case of the polling process, in which (a) shows the processor core 1001.
2 shows signals output from the peripheral block unit 1003 to the processor core 1001. FIG.

Normally, the processor core 1001 activates the processing to the peripheral block unit 1003, and notifies the completion of this processing to the status register 1 in the peripheral block unit.
Check in the polling processing bit area in 004.
As shown in FIG. 27, first, the processor core 1001
At the clock (1), a control register write request is asserted to the peripheral block unit A, and a processing command is written to the control register in the peripheral block unit A.

The procedure of the control register write process is the same as that described with reference to FIG. In this processing command writing processing, the processing in the peripheral block unit is started, and the peripheral block unit A performs the requested processing over the period of clocks (5) to (15). When the peripheral block unit B independent of the peripheral block unit A outputs a DMA request from the clock (13) and performs the DMA transfer processing until the period of the clocks (14) to (19), the processor core 100
Even if 1 wants to know the completion state of the peripheral block part A,
During the DMA transfer period of the peripheral block section B, it is impossible to perform the status register read processing.

[0046]

SUMMARY OF THE INVENTION Conventional system LSI
Since the CPU 1000 is configured as described above, the processor core 1001 may start the status register read processing for the status register 1004 only after the clock (21) at which the DMA transfer period of the peripheral block B ends. it can. Thus, the peripheral block unit 1003
In the polling process of the status register 1004, not only the access is slow, but also the operation of the processor core 1001, which can be executed at a high speed, is performed by a process such as a DMA transfer executed by another bus user. There was a problem that it was not rare in many cases.

Further, the peripheral block unit A receives the clock (1
Even if an interrupt signal is asserted to the processor core 1001 after the processing is completed in 5), an interrupt routine for the interrupt processing is in an external memory (not shown), or a register save processing or the like is required at the beginning of the interrupt routine. And the processing cycle of the processor core 1001 is suspended.
There is a problem that the consumption of the processing cycle cannot be avoided.

The present invention has been made to solve the above-mentioned problems, and has a register for storing data indicating the operation state of each block unit incorporated in a peripheral block unit. An object of the present invention is to obtain a system LSI having a function capable of accessing each block unit at high speed by acquiring the operating state of each block unit.

[0049]

A system LSI according to the present invention includes a processing unit, an internal memory unit, and a peripheral block unit. The processing means includes: an instruction decoder for decoding an instruction; a control register for storing information for controlling the execution of the instruction; a plurality of registers for storing data; an arithmetic circuit for performing an arithmetic operation; An instruction execution unit for executing an instruction in accordance with an output of an instruction decoder, wherein the arithmetic circuit or the like decodes and executes a plurality of instructions described in the program by the instruction decoder to execute data processing according to the program And
Also, a control register transfer instruction for reading out the control information stored in the control register and updating the control information is provided. The internal memory means includes an internal instruction RAM for storing the instruction, and an internal data RAM for storing a processing result of the instruction. Peripheral block means is provided with a peripheral control register connected to the processing means and the internal data RAM in the internal memory means and capable of reading data and updating data by the processing means, independent of the operation of the processing means. And a plurality of peripheral block units for performing data transfer with the internal memory means and performing dedicated processing on the data. Further, the processing means includes a status monitoring control register comprising status bits for reading and storing operation information of the peripheral block portion stored in the peripheral control register in the peripheral block means, Executes the control register transfer instruction, refers to the contents of the state monitoring control register, and detects a change in the processing state of each of the plurality of peripheral block units.

[0050] In the system LSI according to the present invention, the processing means includes a status monitoring control register comprising status bits indicating the processing status of each peripheral block in the peripheral block means, and an interrupt valid bit corresponding to the status bits. And an interrupt enable control register configured to execute an interrupt process for the peripheral block corresponding to the status bit when the interrupt enable bit is set.

[0051] In the system LSI according to the present invention, the processing means further includes a bidirectional buffer unit connected to an address bus and a data bus for accessing the internal data RAM. The peripheral block unit is connected to the processing unit via the bidirectional buffer unit, and data stored in a peripheral control register of each peripheral block unit in the peripheral block unit is read and updated by the processing unit. Each of the peripheral block units in the peripheral block unit executes a memory transfer directly with the internal data RAM via the bidirectional buffer unit independently of the processing unit, and reads the data by the memory transfer. In the memory transfer in which dedicated processing is performed on the read data and the data is written to the internal data RAM, information indicating the processing state of the peripheral block is added subsequent to the final data. The bidirectional buffer unit includes a status register for holding the processing status information on a data transfer path in the bidirectional buffer unit, and the processing unit is stored in the status register in the bidirectional buffer unit. The processing state information of the peripheral block is read out.

In the system LSI according to the present invention, when each of the plurality of peripheral block units in the peripheral block unit directly performs memory transfer with the internal data RAM, the bidirectional buffer unit stores the data in the internal data RAM. It further comprises an address register capable of specifying an address to be output to the processing means by the processing means, and an address adding mechanism capable of adding the value of the address register. The processing means may include a start bit for storing data for activating reading of data from the internal data RAM in the memory transfer performed by the plurality of peripheral block units directly with the internal data RAM. Is provided. In addition, the processing unit writes the address for the memory transfer into the address register in the double-sided buffer unit, and updates the start-up bit using a control register transfer instruction to correspond to the start-up bit. The peripheral block section executes the memory transfer operation with the internal data RAM.

[0053] In the system LSI according to the present invention, the processing means further includes a bidirectional buffer unit connected to an address bus and a data bus for accessing the internal data RAM. Then, the peripheral block unit is connected to the processing unit via the bidirectional buffer unit, and the data stored in the peripheral control register provided in each of the plurality of peripheral block units in the peripheral block unit is: It is read and updated by the processing means. Each of the peripheral block units in the peripheral block unit is connected to the internal data R independently of the processing unit via the bidirectional buffer unit.
A memory transfer is directly performed with the AM, a dedicated process is performed on the data read by the memory transfer, and the first data of the data read by the memory transfer is fetched. Dedicated processing is performed on data read subsequent to the head data.

[0054]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. First, the basic configuration of a system LSI having the high-speed communication means of the present invention will be described. The system LSI includes a processor core (processing means) 4, an internal instruction RAM (internal memory means) 2, an internal data RAM (internal memory means) 3, and a peripheral block section (peripheral block) including a plurality of block sections for performing various dedicated controls. Means 9). The processor core 4 includes a core data path unit 5,
A system including a core control unit 6, a bidirectional buffer unit 8, an instruction decoder for decoding instructions, a control register for storing information for controlling the execution of instructions, a data register for storing data, and an arithmetic circuit for executing arithmetic operations Performs overall control.

Hardware Configuration FIG. 1 is a block diagram showing the overall configuration of a system LSI according to the present invention. In FIG. 1, reference numeral 1 denotes a system LSI. This system LSI 1 is an MPEG2 (Moving P
It has a function of real-time decoding of high-compression moving image data conforming to the "ictureExpert Group 2) standard. In the figure, the system LSI 1
Are internal instruction RAM 2, internal data RAM 3, processor core 4, system bus I / F unit 10, VLCD
(Huffman code encoding / decoding processing) section 11, DRAM I /
F section 12, video output section 13, audio output section 14,
The peripheral block unit 9 includes a block loader unit 15, an input unit 16, and a CRC unit 17.

The processor core 4 includes an instruction decoder, a control register, a data register, an arithmetic circuit, a core control unit 6 having a built-in peripheral control unit 7, a core data path unit 5, a bidirectional buffer unit 8, and the like. ing. The peripheral control unit 7 in the core control unit 6 includes a plurality of processing units 10 to 17 via dedicated signal lines 40 a to 40 h for exchanging information.
Is connected to the peripheral block section 9 composed of

The processor core 4 stores the instruction address bus 20 in the internal instruction RAM 2 and the system bus I / F unit 10.
Is output. The address is the system bus I / F unit 10
The system bus I / F unit 10
Fetches an instruction code from an external memory (not shown) via the bus 50 and transfers the instruction code to the processor core 4 via the bus 24. The instruction address bus 20
Is for the internal instruction RAM 2, the internal instruction RAM 2 transfers the instruction code to the processor core 4 via the bus 23.

The processor core 4 selects one of the buses 23 and 24 and acquires an instruction code to be processed through the bus 25. The processor core 4 performs a decoding process on the transferred instruction code, controls the operation execution unit from the decoded result, and
The data to be calculated is read out from the memory (not shown in FIG. 1 and described in detail in FIGS. 10 to 14). Then, the result of the operation is stored in the general-purpose register 300. For example, if the data used in the above operation does not exist in the general-purpose register 300, the data address bus 2
1 to access the internal data RAM 3 and acquire necessary data from the internal data RAM 3 via the bus 22.

Alternatively, the processor core 4 accesses the system bus I / F unit 10 via the address bus 26 connected to the peripheral block unit 9. System bus I
The / F unit 10 obtains necessary data from an external memory (not shown) via the bus 50, and then transfers the data obtained via the data bus 27 to the processor core 4.

When the processor core 4 wants to store the operation result in the external memory, the address and the data are transferred to the system bus I / F via the buses 26 and 27, respectively.
Hand over to part 10. The system bus I / F unit 10 receiving these data stores the data as the operation result in the area in the external memory indicated by the target address via the bus 50.

The VLCD unit 1 in the peripheral block unit 9
1, DRAM I / F unit 12, video output unit 13, audio output unit 14, block loader unit 15, input unit 16,
If the data address output from the processor core 4 via the bus 26 is for the own block, each of the CRC units 17 also reads data from the peripheral control register in the own block for that address, and Store the data in the peripheral control register.

When the processor core 4 writes a command in the peripheral control register in the peripheral block section 9, various processes are started in the peripheral block section 9.
Each part in each peripheral block part 9 is a processor core 4
Directly with the internal data RAM 3 without going through the programming process. That is, D
MA transfer is possible. By this DMA transfer, the internal data R is transferred between the processor core 4 and the peripheral block 9.
Data can be efficiently exchanged via the AM3, and high-performance system processing can be performed.

Next, in order to decode MPEG2 which is a moving picture standard in real time, each peripheral block 9
An outline of the processing of each unit built in the unit will be described.
The CRC unit 17 has a Cyclic Redundancy.
This is a block for performing checks. That is, it is a block for detecting a data error occurring during data transfer. In particular, in the case of audio data that has been subjected to high compression encoding, if a data error occurs even for one bit, poor quality speech is decoded. Therefore, the CRC unit 17 detects a data error of the audio data, and if the error can be repaired, repairs it.

The input section 16 is a block provided with an external interface for receiving a bit stream highly compressed according to the MPEG2 standard.

The block loader unit 15 has a DRAM I / F
The unit 12 is a block for efficiently controlling the transfer of video block data between a frame memory (not shown) accessed via the external bus 51 and the internal data RAM 3.

The audio output unit 14 converts the decoded audio data stored in the external frame memory into
This is a block provided with an external interface for reading out via the RAM I / F section 12 and outputting the read out audio data to the outside.

The video output unit 13 converts the decoded video data stored in the external frame memory into a DRA.
This is a block provided with an external interface for reading via the MI / F unit 12 and outputting the read video data to the outside.

The DRAM I / F unit 12 includes a block loader unit 15, an audio output unit 14, and a video output unit 1.
3 is a block for receiving a request output from the external frame memory 3 and controlling access to an external frame memory according to the request.

The VLCD unit 11 is a variable L
This block is a block that decodes a Huffman code, which is a variable-length code required for high compression, in the length code decode unit, and performs a code process on the Huffman code.

The system bus I / F unit 10 is a block that controls an interface of a system bus to which an external memory or the like is connected.

FIG. 2 is a flowchart showing an image decoding process by the system LSI 1 shown in FIG. The input data coded into the variable length code is serially input from the bus 54, the input unit 16 converts the input data into 32-bit parallel data, and converts the converted data into the DM data.
The data is written into the internal data RAM 3 by the A write transfer (step ST20).

Next, the data written in the internal data RAM 3 is read out by the processor core 4, separated into video data and audio data of variable length code, and the separated variable length video data is written in the internal data RAM 3. Return (step ST21).

The VLCD unit 11 reads the separated variable-length video data by DMA read transfer, decodes one pixel into fixed-length data of 8 bits per pixel, and performs DMA write transfer as the video data of the block to store the internal data RA.
Write back into M3 (step ST22).

The processor unit 4 reads the block-length pixel data decoded to a fixed length, and performs an inverse quantization process on the read pixel data (step ST).
23). In the inverse quantization process, in step ST23, each pixel data is multiplied by two pixels, and a matrix block in which the index values are in a zigzag order is a standard index order in which the pixels in n rows and m columns have the index values (8n + m). It is converted to a matrix block.

The inversely quantized block-by-block pixel data is held in the general-purpose register 300 in the processor core 4 and used for the next inverse DCT process (step ST24).

In the inverse DCT process ST24, a two-dimensional block consisting of 8 × 8 pixels is converted at high speed using an eight-point one-dimensional inverse DCT high-speed algorithm. Next, it is determined whether the addition to the prediction data is to be performed on the pixel data subjected to the inverse DCT processing based on the modification information of the block (step ST25). When performing addition with the prediction data, the block loader unit 15
, The data of the prediction target block of the adjacent frame is read from the external frame memory, and the data of the prediction target block is written to the internal data RAM 3 using DMA write transfer.

In addition, in the moving picture data of the MPEG standard, the necessity of addition to the prediction data is indicated by modification information attached to every six block data. Therefore, the reading of the prediction target block data by the block loader 15 can be started simultaneously with the start of the decoding processing of the block data. In the system LSI 1 according to the first embodiment, the reading processing of the prediction data by the block loader unit 15 is performed. Is an inverse quantization process performed by the processor core 4 (step S
T23) and the inverse DCT process (step ST24).

Next, the processor core 4 transmits the internal data RA
The prediction data is read from M3, added to the data after the inverse DCT processing (step ST24) is completed, and written back into the internal data RAM 3 (step ST27). The addition result, which is decoded data, is sent to the block loader unit 1
5 writes back into the external frame memory via the DRAM I / F unit 12 (step ST28).

If the addition with the prediction data is not performed (step ST25), the block loader unit 15
The pixel data subjected to the processing (step ST24) is written into the external frame memory as decoded data as it is (step ST28).

The decoded video data written in the external frame memory is read out by the video output unit 13 via the DRAM I / F unit 12 on a frame basis and output to an external image display device via the bus 52. (Step ST29).

Processing Step ST Performed by Processor Core 4
The compressed audio data separated at 21 and stored in the internal data RAM 3 is read by the processor core 4 and subjected to an unpacking process (step ST30). The data after this unpacking process is
Held in the general-purpose register 300 of the processor core 4,
Subsequently, fast Fourier transform processing is performed, and the data is written back into the internal data RAM 3 as decoded audio data (step ST31).

The decoded audio data is
The data is read out by the DMA read transfer executed by the block loader unit 15 and stored in the external frame memory via the DRAM I / F unit 12. The decoded audio data written in the external frame memory is read out by the audio output unit 14 via the DRAM I / F unit 12 and is supplied via the bus 53 to an external audio generator (not shown).
Output to

In the processing shown in the flowchart of FIG. 2, the processor core 4 determines the processing enclosed by a thick frame (steps ST21, ST23, ST24, ST27, ST30, ST3).
1), and the peripheral block unit 9 executes other processes (steps ST20, 22, 25, 26, 28, 29, 32). All the processes executed by the peripheral block unit 9 are started when the processor core 4 activates, and thereby the sequence control of the entire image processing is performed.

The peripheral block unit 9 starts various exclusive processes according to the activation process by the processor core 4. In the system LSI 1 that performs such image processing in real time, the processor core 4 that manages the entire sequence and performs high-speed data processing and the peripheral block unit 9 that performs various dedicated processes need to operate in cooperation. The high-speed communication means used for transmitting and receiving data to and from the processor core 4, the peripheral block unit 9, and other external devices is indispensable.

Instruction Set and Register FIG. 3 is an explanatory diagram showing a format of an instruction executed by the processor core 4 in the system LSI 1 of the present invention. In the figure, 101 designates two operations by one instruction. A two-operation instruction format 102 is a one-operation instruction format in which one instruction specifies one operation.

The two-operation instruction format 101 includes a format field including a format field 103 and a format field 104, two operation fields 106 and 107, and an execution condition field 105 attached to each operation field. The format of one operation instruction includes a format field including a field 103 and a field 104, a field 1
08, a field 109 and a field 110, and an execution condition field 105 attached to this field.

FIG. 4 shows a format field (FM).
It is an explanatory view showing the detailed contents of 103 and 104. In the figure, when the value of the format fields 103 and 104 is FM = 00, this instruction is a two operation instruction, and the operation_0 indicated in the operation field 106
Operation and the operand indicated by the operation field 107
The operation of the timing_1 is executed in parallel in the clock cycle immediately after decoding.

When FM = 01, this instruction is a two-operation instruction, and the instruction indicated by the operation
operation_ion_0 is executed in the clock cycle immediately after decoding, and the operation
The operation of ratio_1 is executed with a delay of one clock cycle from the operation of operation_0.

When FM = 10, this instruction is a two-operation instruction, and the instruction
operation_1 is executed in the clock cycle immediately after decoding, and the operation indicated by operation field 106
The operation of the operation_0 is executed one clock cycle later than the operation of the operation_1.

When FM = 11, this instruction is one operation instruction, and one operation specified in operation fields 108, 109 and 110 is executed in the clock cycle immediately after decoding.

FIG. 5 shows the execution condition field (CC) 10
5 is shown below. Execution condition field (CC) 105
Are the state flags F0 and F of the processor core 4 described later.
The operation of operation_0 and the operation indicated by operation fields 106 and 107, respectively, depending on the value of 1
operation_1 and operation fields 108 and 10
Determines whether the operations indicated by 9 and 110 are valid or invalid.

The operation is valid when the operation result is reflected in the register, the memory, and the flag, and the operation result defined by the operation remains. When the operation is invalid, the operation result is stored in the register. Not reflected in memory and flags,
This means that the same result as an invalid operation (NOP: no operation) remains in a register or a flag irrespective of a predetermined operation type.

When the value of the execution condition field 105 is CC = 0
At 00, the operation is always valid regardless of the values of the flags F0 and F1. When CC = 001, the operation is valid only when F0 = true regardless of the value of F1. CC = 01
When 0, the operation is valid only when F0 = false regardless of the value of F1. When CC = 011, the operation is valid only when F1 = true regardless of the value of F0.

When CC = 100, the operation is valid only when F1 = false regardless of the value of F0. CC = 101
, The operation is valid only when F0 = true and F1 = true. When CC = 110, the operation is F0 = true and F1 =
Valid only when false. The operation when CC = 111 is undefined, and this value is not used in the instruction.

FIG. 6 is an explanatory diagram showing the details of short operation fields 106 and 107 represented by 28 bits and long operation fields (108, 109 and 110) represented by 54 bits. It is. In the figure, the short calculation field has seven formats 111, 11
2, 113, 114, 115, 116, 117,
The long operation field has one format 118.

The format 111 includes a field 120 for specifying the operation content, two fields 121 and 122 for specifying the register number, a field 123 for specifying the register number or a 6-bit immediate value, and a field 1.
23 comprises a field 124 for designating whether to indicate a register number or an immediate value. This format 11
1 is used for a memory access operation of register indirect addressing.

The format 112 includes a field 120 for designating the operation contents, two fields 121 and 122 for designating a register number, a field 123 for designating a register number or a 6-bit immediate value, and a field 1.
23 comprises a field 125 for designating whether to indicate a register number or an immediate value. This format 11
2 is used for arithmetic operations, logical operations, shift operations, and bit operations.

The format 113 is composed of a field 120 for specifying the operation content and a field 126 for specifying the register number. This format 113 is used for jump and branch instructions by register designation.

The format 114 is composed of a field 120 for designating the operation content and a displacement field 127 having a length of 18 bits. This format 114 is used for jump and branch instructions.

The format 115 includes a field 120 for specifying the operation content, a field 121 for specifying the register number, a field 128 for specifying the register number or the immediate value of 12-bit length, and whether the field 128 indicates the register number or the immediate value. Field 12 to specify
9. A field 130 for specifying whether the field 121 performs a conditional jump and a conditional branch based on a zero determination.
Consists of This format 115 is used for conditional jump and conditional branch instructions.

The format 116 includes a field 120 for specifying the operation content, a field 121 for specifying the register number, a field 128 for specifying the register number or the immediate value of 12-bit length, and whether the field 128 indicates the register number or the immediate value. Field 12 to specify
9 is comprised. This format 116 is used for a conditional jump, a conditional branch instruction, and a repeat instruction.

The format 117 includes a field 120 for specifying the operation content, a field 128 for specifying the register number or a 12-bit immediate value, and a field 128.
129 designates a register number or an immediate value, and a field 131 designates a delay value of a delayed instruction. This format 11
Reference numeral 7 is used for delayed jump and delayed branch instructions.

The format 118 is composed of a field 120 for specifying the operation content, two fields 121 and 122 for specifying the register number, and a field 132 for specifying a 32-bit immediate value. The arithmetic operation of the format 118 includes a complicated arithmetic operation, an arithmetic operation using a large immediate value, a memory access operation of register indirect addressing with a large displacement, a branch operation of a large branch displacement, and a jump operation to an absolute address.

The format 119 includes a field 120 for designating the operation content, two fields 121 and 122 for designating the register number, a field 132 for designating a 32-bit immediate value, and a field 132 in which conditional jumping and conditional branching by zero judgment are performed. Field 133 for designating whether or not to perform. This format 119 is used for a conditional jump or conditional branch instruction having a large branch displacement.

FIG. 7 is a diagram showing the configuration of various registers built in the processor core 4. In the figure, a processor core 4 has 64 32-bit general-purpose registers 30.
There are 0, 18 control registers 150, and 2 accumulators 18. The register (R0) 140 in the general-purpose register 300 is always 0 when read, and writing is ignored.

The register (R6) in the general-purpose register 300
3) is a stack pointer, and the user stack pointer (SPU) 141 or the interrupt stack pointer (SPI) 142 operates depending on the value of the SM field of the processor status flag 10. The control register 150 includes a program counter 151, a processor status flag 10, and various dedicated registers.

In the calculation of the format 112, each of the 64 general-purpose registers 300 can be divided into upper 16 bits and lower 16 bits and can be accessed separately. Further, the two accumulators 18 can separately access the upper 32 bits and the lower 32 bits, respectively.

FIG. 8 is an explanatory diagram showing the details of the processor status flag 10. In the figure, the upper 16 bits 170 of the processor status flag 10 include an SM field 171 for switching a stack pointer, an EA field 172 indicating detection of a software debugger trap (SDBT), and a DB field 1 for designating permission of the SDBT.
73, DS field 174 for specifying debug interrupt permission, IE field 17 for specifying interrupt permission
5. RP field 17 specifying permission of repeat operation
6. There is an MD field 177 that specifies permission for modulo addressing.

The lower 16 bits are in the flag field 180
It is. The flag field 180 has eight flags. Among them, the F0 flag 181 and the F1 flag 182 control the validity / invalidity of the operation. The value of each flag changes depending on the result of the comparison operation or the arithmetic operation, and also changes by initializing by a flag initialization operation or writing an arbitrary value to the flag field 180 by a flag value writing operation. Further, the value of the flag field 180 can be read by the flag value read operation.

The system LSI 1 of the present invention, that is, a list of instructions of the microprocessor is shown below. A. MCU function instructions A-1.Load / Store instructions LDB Load one byte to a register with sign extension LDBU Load one byte to a register with zero extension LDH Load one half-word to a register with sign extension LDHH Load one half- word to a register high with sign extension LDHU Load one half-word to a register with zero extension LDW Load one word to a register LD2W Load two words to registers LD4BH Load four bytes to four half-word in two registers with sign extension LD4BHU Load four bytes to four half-word in two registers with zero extension LD2H Load two half-word to two word in two registers with sign extension STB Store one byte from a register STH Store one half-word from a register STHH Store one half-word from a register high STW Store one word from a register ST2W Store two words from registers ST4HB Store four bytes from four half-word from two registers ST2H Store two half-word from two registers MODDEC Decrement a register value by a 5-bit immediate value MODINC Increment a register value by a 5-bit immediate value

A-2. Transfer instructions MVFSYS Move a control register to a general purpose register MVTSYS Move a general purpose register to a control register MVFACC Move a word from an accumulator MVTACC Move two general purpose registers to an accumulator

A-3. Compare instructions CMPcc Compare cc = EQ, NE, GT, GE, LT, LE, PS (both positive), NG (both negative) CMPUcc Compare unsigned cc = GT, GE, LT, LE

[0113]

A-5. Arithmetic operation instructions ABS Absolute ADD Add ADDC Add with carry ADDHppp Add half-word ppp = LLL, LLH, LHL, LHH, HLL, HLH, HHL, HHH ADDS Add register Rb with the sign of the third operand ADDS2H Add sign to two half-word ADD2H Add two pairs of half-words AVG Average with rounding towards positive infinity AVG2H Average two pairs of half-words rounding towards positive infinity JOINpp Join two half-words pp = LL, LH, HL, HH SUB Subtract SUBB Subtract with borrow SUBHppp Subtract half-word ppp = LLL, LLH, LHL, LHH, HLL, HLH, HHL, HHH SUB2H Subtract two pairs of half-words

A-6. Logical operation instructions AND logical AND OR logical OR NOT logical NOT XOR logical exclusive OR ANDFG logical AND flags ORFG logical OR flags NOTFG logical NOT a flag XORFG logical exclusive OR flags

A-7.Shift operation instructions SRA Shift right arithmetic SRAHp Shift right arithmetic a half-word p = L (0), H (1) SRA2H Shift right arithmetic two half-words SRC shift right concatenated registers SRL Shift right logical SRLHp Shift right logical a half-word p = L (0), H (1) SRL2H Shift right logical two half-words ROT Rotate right ROT2H Rotate right two half-words

[0117]

A-9. Branch instructions BRA Branch BRATZR Branch if zero BRATNZ Branch if not zero BSR Branch to subroutine BSRTZR Branch to subroutine if zero BSRTNZ Branch to subroutine if not zero DBRA Delayed Branch DBRAI Delayed Branch immediate DBSR Delayed Branch to subroutine DBSRI Delayed Branch immediate to subroutine DJMP Delayed Jump DJMPI Delayed Jump immediate DJSR Delayed Jump to subroutine DJSRI Delayed Jump immediate to subroutine JMP Jump JMPTZR Jump if zero JMPTNZ Jump if not zero JSR Jump to subroutinee JSRTZR Jump to subroutine if zero JSRTNZ Jump to subroutine if not zero NOP No operation

A-10. OS-related instructions TRAP Trap REIT Return from exception, interrupts, and traps

B. DSP function instructions B-1. Arithmetic operation instructions MUL Multiply MULX Multiply with extended precision MULXS Multiply and shift to the right by one with extended precision MULX2H Multiply two pairs of half-words with extended precision MULHXpp Multiply two half- words with extended precision pp = LL, LH, HL, HH MUL2H Multiply two pairs of half-words MACa Multiply and add a = 0, 1 MACSa Multiply, shift to the right by one, and add a = 0, 1 MSUBa Multiply and subtract a = 0, 1 MSUBSa Multiply, shift to the right by one, and subtract a = 0, 1 SAT Saturate SATHH Saturate word operand into high half-word SATHL Saturate word operand into low half-word SATZ Saturate into positive number SATZ2H Saturate two half-words into positive number SAT2H Saturate two half-word operands

B-2. Repeat instructions REPEAT Repeat a block of instructions with immediate

Pipeline Operation FIG. 9 is an explanatory diagram showing a pipeline process in which each process performed by executing one instruction is assigned to four pipeline stages. In the figure, a processor core 4 of a system LSI 1 normally executes an IF, D / A, E
Execution is performed in four pipeline stages of / M and W.

Since the pipeline stages of sequentially issued instructions can overlap and be executed in parallel, recent high-performance microprocessors always use this pipeline method. Each pipeline stage is composed of registers synchronized with a high level (H level) period (first half) and a low level (L level) period (second half) of a clock, and various processes are executed between these registers. . Therefore, the processing of each pipeline stage can be considered separately in the first half and the second half.

First, an instruction fetch is executed in the IF stage, and the instruction is decoded in the D / A stage. Then, data read processing from the general-purpose register 300 is started in the first half of the D / A stage, and operand address calculation for data access is performed in the second half.

In the E / M stage, operation and data memory access are executed. Then, in the latter half of the W stage, the operation result is written into the general-purpose register 300. This is an outline of a pipeline-like process for executing one instruction.

The control registers CR0 to CR1 shown in FIG.
7 is performed in the latter half of the E / M stage.

Detailed Block Diagram of Processor Core 4 FIGS. 10 to 14 show the system LS of the present invention shown in FIG.
FIG. 2 is a block diagram showing a detailed block configuration centered on a processor core 4 in I1. FIGS. 10 to 14 mainly show detailed block configurations in the core data path unit 5 and the core control unit 6 in the processor core 4 shown in FIG. The core control unit 6 has a built-in peripheral control unit 7, which is one of the features of the present invention.

The data path unit 5 is a block for executing an instruction based on the four pipeline stages (IF, D / A, E / M, W) shown in FIG. Figures 10-14
12 is a memory access unit for performing memory access control and program control on the left side of the general-purpose register 300 (FIGS. 12 and 13), and on the right side of the general-purpose register 300. The part (FIG. 14) is an integer operation unit that performs all integer operations including all multiplication instructions. In these memory access unit and integer operation unit, two sub-instructions included in the instruction code shown in FIG. 3 are executed in parallel.

The memory access unit shown in FIGS. 12 and 13 includes an ALU 301 and a shifter 302. In addition, various arithmetic units and registers for performing memory access control, program control, and the like are included. 30 is
An instruction register that outputs an instruction address to the instruction RAM via the instruction address bus 20 during instruction fetch processing.

When the instruction fetch is completed in the IF stage, the instruction is incremented by 8 bytes by the incrementer 31, and the instruction register 30 is updated via the register 32.

Numeral 36 denotes a data integer section for performing integer adjustment of stored data when performing a store process to a memory. 37 and 38 are sign extension units for sign extension of load data from the memory.

Reference numeral 303 denotes an incrementer for performing post-increment / decrement processing at the time of executing load and store instructions used in modulo addressing using a memory area as a circular buffer. 33 is
This is an adder for calculating the data address of the load / store processing and the jump address of the branch instruction.
Further, CR0 to CR17 are the control registers shown in FIG. 7, and a part of the control registers CR0 to CR17 is built in the core control unit 6.

Reference numeral 304 denotes an incrementer for incrementing the program counter CR0. Reference numeral 305 denotes an adder for calculating the value of the repeat count register CR6 and the value of the repeat end address register CR8 when executing a repeat instruction or a delayed branch instruction. 306 is a decrementer for decrementing the value of the repeat count register. A 32-bit comparator 310 compares the value of the instruction break address register CR11 with the value of the program counter CR0, and outputs a coincidence signal if the values are the same.

Reference numeral 311 denotes a repeat count register CR.
If the value of 6 is 0 or more, a signal that becomes valid is output 32
It is a bit comparator. Numeral 312 is a 32-bit comparison for comparing the value of the repeat end address register CR8 with the value of the instruction register 30 and outputting a coincidence signal if the values are the same. A 32-bit comparator 313 outputs a coincidence signal if the value of the modulo end address register CR10 is equal to the value of the incrementer 303.

Reference numeral 314 denotes a 32-bit comparator which outputs a signal which becomes valid if the value of the register e1rminc holding the address incremented / decremented next is 0. 315 is
This is a 32-bit comparator for outputting a signal that becomes valid if the value of the D1S6BUS bus is 0.

The integer operation unit shown in FIG. 14 includes a multiplication unit 320 for executing a multiplication instruction and an ALU 32
1, a shifter 322, and an operation unit 323 for performing a saturation operation. Also, A0 and A1 are two accumulators for performing cumulative addition and the like when performing the product-sum operation and the like shown in FIG.

D1S1BUS, D1S2BUS,
D1S3BUS, D1S4BUS, D1S5BUS, D
1S6BUS is a read bus from the general-purpose register 300, and D1 of D1S1BUS indicates that the bus is driven in the first half of the D stage. These buses with D1 at the beginning are called a D1 synchronous bus group.

Also, W1W1BUS, W1W2BUS,
W1W3EBUS and W1W3OBUS are write buses to the general-purpose register 300, and W1 of W1W1BUS indicates that the bus is driven in the first half of the W stage. These buses with W1 at the top
One synchronous bus group.

Further, D2S1BUS, D2S2BUS,
D2S3BUS, D2S4BUS, D2S5MBUS,
D2S5IBUS and D2S6BUS are buses that output values obtained by taking data of the D1 synchronous bus group into registers synchronized with the period of the L level of the clock, and the buses are driven in the latter half of the D stage.

Further, E2D1BUS, E2D3BUS,
E2D4BUS is a bus that outputs the value of the control register and the value of the register that holds the value of the arithmetic unit to the latter half of the E stage. Data exchange between these stages and the different buses in the first half and the second half thereof is performed via a register for adjusting timing.

Reference numeral 330 denotes immediate data cut out from the instruction code by the core control unit 6. Reference numeral 43 denotes a path for reading the value of the PSW register CR1 in the core control unit to the E2D1BUS. 47 is a path for writing the value of E1CRBUS to a control register in the core control unit. Similarly to the control registers in the core data path unit, these control registers in the core control unit 6 can perform read / write processing without waiting by using the control register access dedicated instructions MVFSYS and MVTSYS instructions.

Reference numerals 340 to 349 denote paths for performing bypass processing for avoiding the wait of pipeline processing due to data interference occurring between consecutive processing instructions. The various operation results of the preceding instruction are written back to the general-purpose register 300, and are simultaneously output to the D2 bus synchronization group for use in the subsequent instruction.

The core control unit 6 decodes the instruction code output from the instruction bus 25, and
Various control signals for performing the control are generated. The instruction code input from the instruction bus 25 is selected by the selector 350 and is transferred to a predecode unit 352 that generates a control signal for generating an immediate value or reading / writing the general-purpose register 300. At the same time, it is taken into the instruction register 351,
The memory access unit shown in FIGS.
4 are output to the decoder units 353 and 354 of the respective D stages for the integer operation unit.

As shown in FIG. 3, when the FM bit of the instruction code is FM = 01 or FM = 10, each of the two sub-instructions included in the instruction code is serially executed. In order to perform this control, an instruction register 355 for serial execution is provided. During serial execution, a sub-instruction to be executed second is once held in the register 355, and feedback control is performed on the selector 350 through the path 356. Also provided is an instruction register 357 for pipeline interlock processing for avoiding data interference occurring between successive processing instructions by pipeline weight processing, and also performs feedback control of the instruction code during execution of this processing.

The core control unit 6 incorporates not only the instruction decoding unit but also the peripheral control unit 7 shown in FIG. The peripheral control unit 7 includes a peripheral state register 45 and an interrupt valid register (interrupt valid control means) 44. The state bit signal 41 obtained from the peripheral block unit 9 is input to the peripheral state register (state monitoring control register) 45. The peripheral state register 45 and the interrupt enable register 44 include other control registers CR1, CR3, CR
Similarly to 5, the value of E1CRBUS in the core data path can be written via the bus 47, and one of these control registers can be selected and read from the bus 43 to the E2D1BUS in the core data path.

The access to these control registers is performed by the control register access dedicated instructions MVFSYS, MVTSYS.
This is possible without a wait using an instruction.

FIG. 15 is a block diagram showing the details of the peripheral state register 45 shown in FIGS. 10 to 14. In the figure, the peripheral state register 45 can be read out by a control register transfer instruction, and has 32 bits. It is configured. Bits 0 to 11 of the peripheral status register indicate status bit values indicating the operation status of each unit in the peripheral block unit 9. The fifteenth bit (SEI) indicates the value of the external interrupt signal. After the reset, the units 10 to 17 in the peripheral block unit 9 are in an idle state unless the processor core writes a command to the peripheral control register of each unit in each peripheral block unit and starts any processing. Indicates a completed state, the status bit of which is 1
It is. That is, SB, SL0, SL1, SV, SA,
The SS0, SS1, ST, and SH bits are 1.

When the processor core 4 writes a command to the peripheral control register of each unit in the peripheral block unit 9 and starts the process, each status bit in the peripheral status register shown in FIG. It is shown that. When the dedicated processing corresponding to each unit in the peripheral block unit 9 is completed, these status bits become 1, indicating that the dedicated processing is completed.

SHE becomes 1 when an error occurs in the Huffman code decoding process in the VLCD unit. SMT becomes 1 when the MUTE # signal is asserted. SVD becomes 1 when writing of VO_NPB is valid.

FIG. 16 is an explanatory diagram showing details of the interrupt enable register in the system LSI 1 shown in FIGS. 10 to 14. In the figure, the interrupt enable register 44 can be read by a control register transfer instruction. Consists of bits. 0 to 1 of the interrupt enable register 44
One bit has an interrupt valid bit, and these values correspond to bits 0 to 11 of the peripheral status register, respectively. That is, when the interrupt bit of the interrupt enable register is 1 and the status bit corresponding to the interrupt bit in the peripheral status register is 1, an interrupt process occurs in the processor core 4.

After the reset of the interrupt enable register shown in FIG. 16, the interrupt bit of the interrupt enable register is 0 and the status bit of the peripheral status register is 1, but no interrupt occurs. If it is desired to cause an interrupt process at the time of completion of the dedicated processing of each unit in the peripheral block unit 9, the processor core 4 activates the dedicated processing to the peripheral block unit 9 and then sets the state of the peripheral block unit 9. It is necessary to set 1 to the interrupt bit corresponding to the bit.

FIG. 17 is a block diagram of the processor core 4.
FIG. 4 is a block diagram showing a detailed configuration of a peripheral control unit 7 having a built-in interrupt enable register and a peripheral state register. In the figure, reference numeral 44 denotes an interrupt enable register, and 45 denotes a peripheral state register.

The peripheral status register 45 is connected to a dedicated signal line 41 to which the value of the status bit of the peripheral control register of each of the units 10 to 17 in the peripheral block unit 9 is transferred.
The value of the dedicated signal line 41 is taken into the status bit value holding register 77. The interrupt enable register 44 includes an interrupt register 76 corresponding to the status bit holding register. The interrupt register 76 includes a bus 47 to which the value of the E1CRBUS bus is transferred as described with reference to FIGS. The processor core 4 can write a value by executing a dedicated instruction for access to the control register through the CPU.

The value of the interrupt register 76 in the interrupt enable register 44 and the value of the status bit value holding register in the peripheral status register 45 are changed by the dedicated instruction for access to the control register of the processor core 4 via the selector 70 via the bus 43. To the E2D1BUS bus.

The selector 70 has a control register CR1,
The values of CR3 and CR5 can be similarly read out via the bus 78. As described above, the processor core 4 executes the dedicated instruction for access to the control register without waiting for the pipeline and reads the value of the state bit indicating the operation state of each unit in the peripheral block unit 9. The processor core 4 can start processing immediately corresponding to the processing status of the block unit 9.

The value of the interrupt enable register 76 and the value of the status bit value holding register 77 are
And the output 72a, which is the processing result,
The OR gate 73 outputs the signal as an interrupt signal. OR
The gate 73 outputs to the signals 72b, 72b, the AND values of the other interrupt register values and the status bit value holding registers.
72c is also input. By controlling the value of the interrupt valid register 44 in this way, it is possible to easily control whether or not an interrupt has occurred based on a change in the state of the peripheral block unit 9.

FIG. 18 is a timing chart showing a communication procedure between the processor core 4 and the peripheral block unit 9 using the peripheral state register.
The signal output from the processor core 4 to the peripheral block unit 9 is shown, and (b) shows the signal output from the peripheral block unit 9 to the processor core 4.

At clock (1), the processor core outputs a control register write request to a certain block section (A) in the peripheral block section 9, and the peripheral block section (A)
Write a command to the peripheral control register inside the device. The procedure of data write processing to the control register is the same as that described with reference to FIG. 26 showing the case of the conventional example.

The operation of the peripheral block (A) starts from the clock (5) after the completion of the control register write processing, and the state bit of the peripheral control register in the peripheral block (A) becomes L level. The period during which this status bit is at the L level coincides with the operation period of the peripheral block unit A.
The case where the other peripheral block unit (B) is performing the DMA transfer to the internal data RAM around the clock (16) at which the operation period of the peripheral block unit (A) ends is shown in the case of the conventional example. As described with reference to FIG. 27, the processor core 4 cannot access the peripheral control register in the peripheral block (A).

However, if the peripheral state register 45 located in the processor core control unit 6 is accessed by a dedicated instruction,
At the highest speed, that is, when this instruction is issued at the clock (14), it is possible to detect that the status bit is at the H level at the E stage of the pipeline. Accordingly, the processor core 4 can immediately start the processing in consideration of the processing completion of the peripheral block unit (A), and smoothly perform the system processing performed mainly by the processor core 4. Is possible. In particular, in the system LSI 1 according to the first embodiment, which performs a moving image decoding process requiring a high-performance process such as the MPEG2 standard in real time, all processes can be efficiently performed only with the performance of the processor core 4.
It is impossible to execute at high speed, and it is indispensable to incorporate the peripheral block unit 9 for performing dedicated processing.

In the system LSI having the above-described configuration and performing real-time processing, the processor core 4 and the peripheral block unit 9 transfer the internal data R by DMA transfer processing.
Data can be exchanged at a high speed via the AM 3 and the processor core 4 can grasp the processing status of each unit in the peripheral block unit 9 at a high speed.

As described above, according to the first embodiment, the processor core 4 and the peripheral block 9 complete the dedicated processing executed by each of the blocks 10 to 17 in the peripheral block 9. , That is, a status bit reflecting the status of the dedicated processing in the peripheral block unit 9 is taken into a peripheral status register 45 which is a control register in the processor core 4 via a dedicated signal line, and the processor core 4 performs control. By executing a dedicated instruction for reading the contents of the register 45, for example, a control register transfer instruction, it is possible to obtain data indicating the operation status of the peripheral block portion stored in the control register 45, The processor core 4 does not wait for the pipeline operation,
This has the effect that it can be grasped immediately. Further, data indicating that the dedicated processing executed in the peripheral block unit has been completed, that is, a status bit reflecting the dedicated processing status of the peripheral block unit is transmitted to the control register in the processor core 4 via the dedicated signal line. A value corresponding to the value in the peripheral state register 45, that is, the value in the interrupt valid register 44, Is configured to set a value in the interrupt register 76 of the peripheral block unit 9 so that an interrupt process or the like can be immediately started in accordance with the exclusive processing status of the peripheral block unit 9. This has the effect that the situation can be immediately grasped and controlled at high speed.

Embodiment 2 FIG. 19 is a block diagram showing a system LSI according to the second and third embodiments of the present invention.
2, the internal data RAM 3 is shown. In the system LSI according to the second embodiment shown in FIG. 19, high-speed communication between the processor core 4 and the peripheral block unit 9 is realized. The processor core 4 has a peripheral status register (PS
T2, a state monitoring control means) 89, and a high-speed data transfer with the peripheral block unit 9 is carried out. The other components are the same as those of the system LSI according to the first embodiment, and thus the same reference numerals are used and the description thereof will be omitted.

The system LSI according to the second embodiment includes a bidirectional buffer unit 8 for controlling data transfer between the processor core 4, the internal data RAM 3, and the peripheral block unit 9.
A register for holding information indicating the state of each unit in the peripheral block unit 9 is incorporated in -1. Then, by adding the status information of each unit in the peripheral block unit 9 to the end of the write data of the DMA write transfer from the peripheral block unit 9 to the internal data RAM 3, the peripheral block unit 9 ending with the DMA write transfer process is completed. This is to execute the situation of the processor core 4 for the processing at a high speed.

The system LS of the first embodiment shown in FIG.
As described in I1, the processor core 4 and the internal instruction R
AM2, the instruction address bus 20 and the data bus 2
2 and the read instruction code is
3 is output. The processor core 4 and the internal data R
The data address bus 21 and the data bus 22 are connected to AM3. The processor core 4 and the peripheral block unit 9 are connected by an address bus 26 and a data bus 27.

The instruction address held in the instruction register 30 is output to the instruction address bus 20 via the selector 88 in order to perform the instruction fetch. Upon receiving the instruction address, the internal instruction RAM 2 outputs an instruction code to the bus 23. Since the instruction fetch is performed in units of 64 bits, once the instruction fetch is performed, 8 is added to the instruction address by the incrementer 31, and the added instruction address is used for the next instruction fetch.

The data address added by the address calculation adder 33 is output to the address bus 21 for performing data access via the latches 34 and 35 and the three-state buffer 66.

When the data access is a read process, the internal data RAM 3 outputs desired data to the bus 22 via the three-state buffer 62. The processor core 4 captures the data via the sign extension units 37 and 38.

When the data access is a write process, the processor core 4 outputs the data to the bus 22 via the data adjustment unit 36 and the three-state buffer 39.
The internal data RAM 3 stores the data at a predetermined address position via the three-state buffer 63.

The data address bus 21 is connected to the internal data R
Not only is output to the AM 3, but also to the bidirectional buffer unit 8-1 to access the peripheral block unit 9. The data address is output to the address bus 26 of the peripheral block unit 9 via the three-state buffer 82. If the data access to the peripheral block unit 9 is a read operation of a control register or the like, the contents of the control register read via the bus 27 are output to the bus 22 via the three-state buffer 68.

The processor core 4 includes the sign extension units 37 and 3
8 to fetch the data. When the data access to the peripheral block unit 9 is a write process of a control register or the like, the data output from the processor core 4 to the bus 22 via the data integer unit 36 and the three-state buffer 39 is transmitted to the three-state buffer 69. Peripheral data bus 2 via
7 and stored in a predetermined control register.

Further, the processor core 4 has an internal instruction RAM.
When the instruction code is read as data from or the instruction code is stored in the instruction code, the data address is first output to the internal instruction RAM 2 via the path 87 and the selector 88. If the access is a read operation,
The instruction codes output to the bus 22 via the three-state buffers 60 and 65 are fetched from the sign extension units 37 and 38.

When the access is a write process, the instruction code output to the bus 22 via the data integer value unit 36 and the three-state buffer 39 is transferred to the instruction RAM 2 via the three-state buffers 64 and 61. Stored in the position of.

Further, when the peripheral block unit 9 directly performs the DMA transfer to the area in the internal data RAM 3, the peripheral block unit 9 transfers the bus right of the address bus 21 and the data bus 22 from the processor core 4. Processing is started after the acquisition.

The data address output from the peripheral block unit 9 to the bus 26 is output to the data address bus 21 via the path 87, the register 87 and the three-state buffer 81, and is transferred into the internal data RAM 3. When the DMA transfer is a read process, the data output from the internal data RAM 3 to the bus 22 via the three-state buffer 62 is output to the data bus 27 via the three-state buffer 69 and transmitted to the peripheral block unit 9. Will be transferred.

When the DMA transfer is a write process, data output from the peripheral block unit 9 to the data bus 27 is output to the bus 22 via the three-state buffer 68. The internal data RAM 3 stores the data at a predetermined position via the three-state buffer 63. When performing this DMA transfer write processing, information on the processing status of the peripheral block unit 9 is taken into the peripheral state register (PST2) 89.

The bidirectional buffer section 8-1 including the peripheral state register (PST2) 89 is located between the processor core 4 and the peripheral block section 9 and executes a process of reading a control register in the peripheral block section 9. It is possible to access at higher speed.

The DMA read / write transfer is often used to transfer a large amount of data at high speed, and usually, a continuous area in the data RAM 3 is often accessed. In this case, the adder 80 performs the address addition of the continuous area, and the address adding mechanism in the bidirectional buffer 8-1 operates the peripheral block 9
Output consecutive addresses instead of.

FIG. 20 is a timing chart showing a communication procedure between the processor core 4 and the peripheral block unit 9 when the peripheral state register (PST2) 89 in the bidirectional buffer 8-1 is used. 5A shows a signal output from the processor core 4 to the peripheral block unit 9, and FIG. 6B shows a signal output from the peripheral block unit 9 to the processor core 4.

The processor core 4 issues a control register write process at the clock (1), and issues a control block write process to the peripheral block (A).
The command for starting the dedicated processing is written in the control register of. This control register write processing is performed from clock (1) to
This is performed during the period (4), and is performed in the same manner as the procedure described in the conventional example shown in FIG.

In the peripheral block (A), when the dedicated processing is started from the processor core 4, the operation period for performing the dedicated processing from the clock (5) is started. Then, in the peripheral block (A), the purposed exclusive processing is executed, and the obtained processing result is written into the internal data RAM 3.
A DMA write transfer processing request is output from the clock (14).

In response to the DMA transfer request, the processor core 4 transmits a DMA acknowledge signal to the peripheral block unit 9 from the clock (15). In the peripheral block section (A), D
An MA address valid signal and a DMA write signal are output, and an address A21 and a DM
The A-write data D21, D22, D23, and D24 are output. These DMA write transfer addresses are incremented by the address addition mechanism of the bidirectional buffer section 8-1, and output to the core address bus during the clock (17) to (20). And DMA
Data for write transfer is also output to the core data bus and written to a predetermined address area in the internal data RAM 3.

Compared with the case of the conventional example shown in FIG. 26, the procedure of the DMA write transfer in the case of the system LSI of the second embodiment shown in FIG. The signal is a clock (2
0), the DM from the peripheral block A
This is because the A write request also keeps asserting the clock (20). At this clock (20), the peripheral block unit (A) also outputs data PST indicating the processing status to the peripheral data bus 27. That is, the processing status data PST is added to the DMA write transfer processing data.

At the clock (21), the processor core 4 asserts the PST2 register write signal, and stores the processing status data in the peripheral status register (PST2) 89 of the bidirectional buffer 8-1. In the clock (22) in which the DMA write transfer of the peripheral block unit (A) is completed, the processor core 4 transmits the bidirectional buffer unit 8-1.
Performs a control register read access to the peripheral status register inside the device. This access can be performed without wait processing, so that the processor core 4 can execute a read operation during the clock (22).

Normally, in the peripheral block unit 9, after the processor core 4 is activated, a predetermined dedicated process is performed, and then the processing result is often stored in the internal data RAM 3 by DMA write transfer. In such a case, the peripheral processing status data is added after the transfer data of the DMA write transfer procedure, and the data is stored in the peripheral status register 89 in the bidirectional buffer unit 8-1 from which the processor core 4 can read the data without waiting. And the like, the processor core 4
The dedicated processing status of each unit in the peripheral block unit 9 can be immediately grasped, and the processing corresponding thereto can be started. The peripheral processing status data includes the currently performed DM
There is information such as in which peripheral block portion the A write transfer was executed, what number of DMA write transfer was performed, and whether peripheral processing was completed.

As described above, according to the second embodiment, in the communication procedure between processor core 4 and peripheral block unit 9, processor core 4 and internal data RAM
3. A peripheral state register that holds data indicating the operation state of each of the blocks 10 to 17 in the peripheral block 9 in a bidirectional buffer 8-1 that controls data transfer to and from the peripheral block 9. 89 and the peripheral block 9
At the end of the write data in the DMA write transfer executed between the
In addition, the processor core 4 has the effect of being able to immediately and quickly grasp the status of processing such as DMA write transfer in each peripheral block unit.

Embodiment 3 Hereinafter, a system LSI according to the third embodiment of the present invention will be described. In the system LSI of the third embodiment, as shown in FIG. 19 and FIGS.
And high-speed communication between the peripheral block unit 9 and the peripheral block unit 9. That is, in the system LSI according to the third embodiment, an address register writable from the processor core in the bidirectional buffer unit 8-1 for controlling data transfer between the processor core 4, the internal data RAM 3, and the peripheral block unit 9. And a peripheral activation control register 90 for activating the peripheral block unit 9 in the processor core control unit 6.
The DMA read transfer from the internal data RAM 3 to the peripheral block unit 9 is started at a high speed. The other components are the same as those of the system LSI according to the second embodiment, and the description thereof will be omitted using the same reference numerals.

Further, processing mode information for performing dedicated processing in the peripheral block unit 9 is added to the head data of the DMA read transfer, and each unit in the peripheral block unit 9 adds the processing mode information as the head data. By providing a mechanism to determine the processing mode for subsequent data based on
The procedure for starting processing in the peripheral block unit 9 is also to speed up.

FIG. 19 is a block diagram showing a bidirectional buffer unit 8-1 having an address register and an address addition mechanism and a data transfer path in the system LSI according to the second and third embodiments. In the bidirectional buffer unit 8-1 shown in FIG. 19, when performing DMA transfer from the peripheral block unit 9 to the internal data RAM 3, like the bidirectional buffer unit 8-1 in the system LSI of the second embodiment, The head address output to the address bus 26 is stored in the register 8
3 and successive addresses are added to the address adder 80.
A built-in address addition mechanism that increments with. In the bidirectional buffer unit 8-1 according to the third embodiment,
Further, an input path from an address transfer path 88 for the processor core 4 to directly set an address is provided for an address register 83 as a register for storing the head address. As a result, the processor core 4 can write the address of the core address bus 21 via the path 88 to the address register 83 in the bidirectional buffer unit 8-1, which can be accessed without waiting processing.

FIG. 21 is a block diagram showing a peripheral start control register provided with a mechanism for activating a process in each unit in the peripheral block unit 9. In FIG. 21, reference numeral 90 denotes a peripheral start control register, and 44 denotes an interrupt. This is a valid register. The interrupt enable register 44 has the same configuration as the interrupt enable register 44 in the peripheral control unit 7 incorporated in the processor core 4, as described with reference to FIG. Similarly, the peripheral start control register 90 is incorporated in the peripheral control unit 7.

The interrupt enable register 44 and the activation register 90 are controlled by the control register transfer dedicated instruction.
The contents of the CRBUS can be written into the interrupt register 76 and the activation bit register 91 via the bus 47, respectively. Further, the contents of the interrupt register 76 and the activation bit register 91 are transferred from the selector 70 via the bus 43 by the control register transfer dedicated instruction.
The data can be read out onto the E2D1BUS bus in the system LSI described in 14.

The selector 70 can also read out the values of other control registers in the core control unit 6 via the path 78. When a value is set from the processor core 4 to the start bit register 91, the start signal line 48 connected to the peripheral block unit 9 is asserted, and the dedicated processing in each unit in the peripheral block unit 9 is started.

State bit signal line 4 in peripheral block section 9
1 is connected to the clear terminal of the activation bit register 91. When the status bit signal line 41 is asserted, the value of the activation bit register is negated. The inverted signal of the output of the activation bit register 91 is AND-processed with the value of the interrupt enable register 76 by the AND gate 71, and the output 72a is input to the OR gate and output as the interrupt signal 74.

The OR gate 73 outputs the output of the other interrupt enable register and the inverted output of the activation bit register 91.
When the ND processing results 72b and 72c are input and the interrupt signal 74 is asserted, an interrupt processing occurs in the processor core 4.

FIG. 22 shows a communication procedure between the processor core 4 and the peripheral block unit 9 when the address register and the address addition mechanism 80 in the bidirectional buffer unit 8-1 and the activation bit register 91 are used. FIG. 4A is a timing chart illustrating a signal output from the processor core 4 to the peripheral block unit 9 in FIG.

In the communication procedure in the system LSI of the third embodiment, the processor core 4
When starting a dedicated process in which processing is started by MA read transfer, first, the processor core 4
Issues a control register write request and stores the address A11 in the address register 83 in the bidirectional buffer unit 8-1 in one clock cycle.

Next, at clock (4), the processor core 4 stores PG, which is the processing mode information of the peripheral block unit 9, in the address A11 of the internal data RAM 3 by using a store process. Further, at clock (5), the processor core 4 sets the start-up bit register in the start-up register in the peripheral control unit 7 with a dedicated instruction for control register access. When the activation bit is set in the activation register in the peripheral control unit 7, the activation signal for the peripheral block unit 9 is asserted for the peripheral block unit 9.

Upon receiving this start signal, the peripheral block unit 9 issues a DMA read transfer request from the clock (6). When the peripheral block unit 9 receives the DMA read transfer acknowledge signal at the clock (7), the peripheral block unit 9 outputs a high-speed DMA address valid signal. When performing the DMA read transfer with this signal, the peripheral block unit 9 does not output the head address of the DMA read transfer, and the bidirectional buffer unit 8-1 outputs the address A11 instead of the peripheral block unit 9. , And the subsequent address increment processing is also performed.

Internal data RAM in DMA read transfer processing
Is the processing mode information PG set by the processor core 4 at the clock (4), and the data D11 to D15 to be processed follow this. In the DMA read processing transfer, processing mode information is embedded at the head of a series of read data groups, and the subsequent data groups become data to be processed by the peripheral block unit 9.

FIG. 23 is a block diagram showing a peripheral block unit 200 provided with a mechanism for determining a processing mode based on the leading data of DMA transfer data. The peripheral block unit 200 according to the third embodiment includes a peripheral block control unit 201 including a peripheral control register and the like and a peripheral data processing unit 202 in each of the block units 10 to 17 in the peripheral block unit 9 shown in FIG. Is built-in.

The peripheral block control unit 201 has a processor core interface including a peripheral start signal 48, a peripheral state signal 41, a group of DMA transfer signal lines, and a peripheral address bus 26. Further, the peripheral block control unit 201 has a data input path 20 from the peripheral data bus.
3 and a control signal line 2 for controlling the peripheral data processing unit
04 and the external address bus 210 are connected.

The peripheral processing data section 202 is connected to the peripheral data bus 27 and the external data bus 211. When the processing mode information is added to the head of the data transferred in the DMA read processing as in the processing start procedure transmitted from the processor core 4 shown in FIG. 22, the peripheral block (A) 200 transmits the processing mode information to the peripheral block control unit 20 via the path 203.
Take it into 1. Then, the peripheral block part (A) 200
Performs processing of the transferred subsequent data based on information obtained by interpreting the fetched processing mode information.

As described above, according to the third embodiment, in the data communication procedure between processor core 4 and peripheral block unit 9, processor core 4, internal data RA
M3, a bidirectional buffer 8-1 for controlling data transfer between the peripheral block 9 and a writable address register 83 by the processor core 4 and an address adder 80 for incrementing this address, and In the processor core control unit 6, a peripheral start control register 90 for storing data for starting in the peripheral block unit is provided, and DMA read transfer between the internal data RAM 3 and the peripheral block unit 9 can be performed at high speed without waiting. There is an effect that can be started. In addition, each block unit in the peripheral block unit 9 starts processing such as DMA read transfer in response to activation of processing by the processor core 4, and
The processing mode for performing the dedicated processing in the peripheral block added to the leading data of the read transfer is changed to the peripheral block 9
Since the processing mode of the subsequent data is determined based on the leading data, the processing start procedure in the peripheral block unit 9 can be started at high speed.

[0204]

As described above, according to the present invention, the processor core and the peripheral block are provided with data indicating the completion of the dedicated processing executed in each block in the peripheral block, that is, in the peripheral block. The status bits reflecting the special processing status are taken into a peripheral status register which is a control register in the processor core via a dedicated signal line, and the processor core executes a special instruction such as a control register transfer instruction for reading the control register. Since the configuration is such that the value stored in the peripheral state register is read out and obtained, there is an effect that the processor core can quickly grasp the dedicated processing status of each peripheral block unit without waiting.

According to the present invention, the processor core and the peripheral block unit transmit the data indicating the completion of the dedicated processing in the peripheral block unit, that is, the status bit reflecting the state of the dedicated processing in the peripheral block unit, to the dedicated signal line. Through the peripheral state register, which is a control register in the processor core, and further, using a dedicated instruction or the like for writing data to the control register, the processor core responds to the value in the peripheral state register. Since the value is set in the interrupt register in the interrupt enable register, an interrupt processing can be generated according to the dedicated processing status of the peripheral block unit.

According to the present invention, in the data communication between the processor core and the peripheral block, the bidirectional buffer for controlling the data transfer between the processor core, the internal data RAM, and the peripheral block is provided. A peripheral state register for holding data indicating the operation state in the peripheral block is provided, and data indicating the operation state of the peripheral block is added to the end of write data of DMA write transfer from the peripheral block to the internal data RAM. With this configuration, the processor core has an effect that the operating state such as the DMA write transfer in the peripheral block unit can be quickly grasped without any wait.

According to the present invention, in the data communication between the processor core and the peripheral block, the bidirectional buffer for controlling the data transfer between the processor core, the internal data RAM, and the peripheral block is provided by the processor core. It has a writable address register and an address adding mechanism for incrementing this address, and
In the processor core control unit, a peripheral start control register for storing data for starting in the peripheral block unit is provided, so that DMA read transfer from the internal data RAM to the peripheral block unit can be performed at high speed without waiting. There is an effect that can be started.

According to the present invention, each of the block units in the peripheral block unit receives D from the processor core.
Processing such as MA read transfer is started, and a processing mode for performing dedicated processing in the peripheral block added to the head data of the DMA read transfer is fetched into the peripheral block controller in the peripheral block, and Since the configuration is such that the processing mode of the subsequent data is determined based on this, there is an effect that the processing start procedure in the peripheral block can be started at high speed.

[Brief description of the drawings]

FIG. 1 shows a system LS according to a first embodiment of the present invention.
It is a block diagram which shows I.

FIG. 2 is a flowchart showing MPEG2 standard image decoding processing in the system LSI according to the first embodiment shown in FIG. 1;

FIG. 3 is an explanatory diagram showing an instruction format executed by a processor core.

FIG. 4 is an explanatory diagram showing an instruction format executed by a processor core.

FIG. 5 is an explanatory diagram showing an instruction format executed by a processor core.

FIG. 6 is an explanatory diagram showing an instruction format executed by a processor core.

FIG. 7 is an explanatory diagram showing a register configuration of a processor core.

FIG. 8 is an explanatory diagram showing a register configuration of a processor core.

FIG. 9 is an explanatory diagram showing pipeline processing executed by a processor core.

FIG. 10 is a circuit diagram showing a detailed configuration of a processor core.

FIG. 11 is a circuit diagram showing a detailed configuration of a processor core.

FIG. 12 is a circuit diagram showing a detailed configuration of a processor core.

FIG. 13 is a circuit diagram showing a detailed configuration of a processor core.

FIG. 14 is a circuit diagram showing a detailed configuration of a processor core.

FIG. 15 is an explanatory diagram showing a detailed configuration of a peripheral state register.

FIG. 16 is an explanatory diagram showing a detailed configuration of an interrupt enable register.

FIG. 17 is a block diagram illustrating a detailed configuration of a peripheral control unit.

FIG. 18 is a timing chart showing a communication procedure using a peripheral state register.

FIG. 19 is a block diagram mainly showing a detailed configuration of a bidirectional buffer unit in a system LSI according to the second and third embodiments of the present invention;

FIG. 20 is a timing chart showing a communication procedure between a processor core and a peripheral block unit using a peripheral state register in the bidirectional buffer unit.

FIG. 21 is a block diagram mainly showing peripheral activation control registers and the like in a system LSI according to a third embodiment of the present invention;

FIG. 22 is a timing chart showing a communication procedure between a processor core and a peripheral block unit which is executed using an address register, an address addition mechanism, and a start register in a bidirectional buffer.

FIG. 23 is a block diagram mainly showing peripheral block units in a system LSI according to a third embodiment of the present invention;

FIG. 24 is a block diagram showing a conventional system LSI.

FIG. 25 shows a conventional processor core and an internal instruction RAM.
FIG. 4 is a diagram showing a data transfer path executed between an internal data RAM and a peripheral block unit.

FIG. 26 is a timing chart of a conventional typical data transfer executed using the data transfer path shown in FIG. 25;

FIG. 27 is a timing chart showing a conventional communication procedure between a processor core and a peripheral block unit.

[Explanation of symbols]

2 internal instruction RAM (internal memory means), 3 internal data RAM (internal memory means), 4 processor core (processing means), 9 peripheral block section (peripheral block means),
45 peripheral status register (status monitoring control register), 8
0 address adder, 90 peripheral start control register,
201 Peripheral block control unit (peripheral control register).

Claims (5)

[Claims] An instruction decoder for decoding an instruction; a control register for storing information for controlling the execution of the instruction; a plurality of registers for storing data; an arithmetic circuit for performing an arithmetic operation; An instruction execution unit that executes an instruction in accordance with an output of the instruction decoder, wherein the arithmetic circuit and the like decode and execute a plurality of instructions described in the program with the instruction decoder, thereby performing data processing according to the program. A processing unit having a control register transfer instruction for executing, reading control information stored in the control register, and updating the control information; an internal instruction RAM for storing the instruction; and a processing result of the instruction. An internal memory means comprising an internal data RAM; a processing means; and an internal data RAM in the internal memory means. A peripheral control register capable of reading data and updating data by the processing means, and performing data transfer with the internal memory means independently of the operation of the processing means; A peripheral block unit having a plurality of peripheral block units for performing dedicated processing on data, wherein the processing unit reads and stores operation information of each of the plurality of peripheral block units stored in the peripheral control register. A status monitor control register configured with status bits of the above, executing the control register transfer instruction, referring to the contents of the status monitor control register, and determining a change in the processing status of each of the plurality of peripheral block units A system LSI characterized by detecting. 2. The processing means further comprises an interrupt enable control register including an interrupt enable bit corresponding to the status bit for reading and storing operation information of each of the plurality of peripheral block units, and 2. The system LSI according to claim 1, wherein when the valid bit is set, interrupt processing for the peripheral block corresponding to the status bit is executed. 3. The processing unit further includes a bidirectional buffer unit connected to an address bus and a data bus for accessing an internal data RAM, and the peripheral block unit includes:
The data stored in the peripheral control registers of each of the plurality of peripheral block units in the peripheral block unit, which is connected to the processing unit via the bidirectional buffer unit,
Each peripheral block in the peripheral block is read and updated by the processing unit, and the internal data R is independent of the processing unit via the bidirectional buffer unit.
A memory transfer is directly performed with the AM, a dedicated process is performed on the data read by the memory transfer, and a data write to the internal data RAM is performed. Subsequently, information indicating a processing state of the peripheral block unit is added, and the bidirectional buffer unit includes a state register for holding the processing state information on a data transfer path in the bidirectional buffer unit, 2. The system LSI according to claim 1, wherein the processing unit reads processing status information of the peripheral block unit stored in the status register in the bidirectional buffer unit. 4. The bi-directional buffer section outputs an address to be output to the internal data RAM when each of the plurality of peripheral block sections in the peripheral block means directly performs memory transfer with the internal data RAM. Further comprising an address register that can be designated by a processing means, and an address addition mechanism that can add the value of the address register, wherein the processing means allows the plurality of peripheral block units to directly communicate with the internal data RAM. The memory transfer to be executed includes a peripheral start control register including a start bit for storing data for starting reading of data from the internal data RAM, wherein the processing unit includes the address in the bidirectional buffer unit. The address for the memory transfer is written in a register, and the start-up window is transmitted using a control register transfer instruction. 4. The system LSI according to claim 3, wherein the peripheral block corresponding to the activation bit executes the memory transfer operation with the internal data RAM by updating a start bit. 5. The processing means further comprises a bidirectional buffer unit connected to an address bus and a data bus for accessing an internal data RAM, and the peripheral block means comprises:
Data that is connected to the processing unit via the bidirectional buffer unit and stored in a peripheral control register provided in each of the plurality of peripheral block units in the peripheral block unit is read and updated by the processing unit. Wherein each of the plurality of peripheral block units is independent of the processing means via the bidirectional buffer unit and independent of the internal data RA.
M, directly performing a memory transfer, performing a dedicated process on the data read by the memory transfer, taking in the leading data of the read data, and performing a dedicated process in accordance with the leading data. 2. The system LSI according to claim 1, wherein the step (c) is performed on data read after the head data.