JPS6375869A - Initialization system for processor - Google Patents

Abstract

PURPOSE:To reduce cost and deal with the modification of system flexible by reducing firmware for initialization, and starting an initialization program on a common memory. CONSTITUTION:A master CPU 0 loads the initialization program 60 for a slave CPU 1 on the common memory 5 from a file 6, and informs the slave CPU 1 of it. The slave CPU 1, in accordance with this information, read a head address from an address specifying part 11, and executes the initialization program. In case, for instance, a processor provided with a vector for reset- processing is employed as the slave CPU 1, by releasing the resetting of it by means of the information from the master CPU 0, the content of the vector allocated to the reset-processing is set in the program counter of the slave CPU 1, and the slave CPU 1 runs from this address.

Description

[Detailed Description of the Invention] [Summary] The master processor (hereinafter referred to as master CPU)
In this method, the initial startup program of the slave CPU is loaded into the shared memory from an external file by the mask CPU, and then the initial startup program of the slave CPU is loaded into the shared memory.
The slave CPU reads the start address of the initial startup program from the address specification section and executes it.Since the initial startup program is executed on the shared memory, the amount of firmware required for initial startup can be reduced. .

[Industrial application field]

The present invention provides a slave C system in a multiprocessor system.
This article relates to improving the initial startup method of PU.

A unique memory accessed exclusively by each CPU;
In a loosely coupled multiprocessor system equipped with a shared memory that is commonly accessed by each CPU, the system starts up by first starting up the mask CPU, then starting up the master CPU.
Start up the slave CPU with U.

For this reason, the master CPU loads the slave CPU's initial startup program from an external file etc. into the shared memory,
The slave CPU stores the program in its own unique memory and executes its initial startup program.

In order to initialize the slave CPU or load the initial startup program, firmware stored in the ROM is required, which poses a problem in that the system becomes expensive along with hardware for inter-processor communication.

Therefore, there is a need for an initial startup method that facilitates the initial startup of the slave CPU and reduces the amount of hardware described above.

[Conventional technology]

FIG. 3(a) is a multiprocessor system configuration diagram, and FIG. 3(b) is an explanatory diagram of a conventional initial startup method.

Figure 3 (in al, CPU0 is the master CPU, CPU
TJI and CPIJn are slave CPUs, each having its own memory 2.3.4 and accessing the shared memory 5 in common.

For this reason, each CPU is allocated with an individual area 20 and a common area 21, as shown in FIG. 3 (bl).

When starting up the slave CPUI in the above system, the master cpuo that starts up by reading and executing the initial startup program from file 6 reads the initial startup program 50 of the slave CPUI from file 6, stores it in its own specific memory 2, and , (2) Transfer to the shared memory 5, and notify the slave CPU of the start address through inter-CPU communication.

The slave CPU is equipped with firmware 51 in a ROM (not shown) for initial settings and loading the initial startup program 50 into the specific memory 3, and after initializing each part, the initial startup program 50 is loaded into the specific memory 3 through the inter-CPU communication. Load it and run it to start up.

Note that for inter-CPU communication, for example, each CPU
There is a method in which a register is provided in the CPU and an interrupt is raised when it is written by another CPU.

[Problem that the invention seeks to solve]

The conventional method is to initialize the slave CPUI.

In addition to firmware (ROM) 51 for loading the initial startup program, hardware for communicating between CPUs was required.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to provide a simple initial startup method that reduces the above-mentioned hardware for initial startup.

[Means for solving problems]

For the above purpose, the initial startup method of the processor of the present invention, as shown in FIG. and executes the initial startup program (60) on the slave processor (
An initial startup control section (13) for instructing the CPU 1) is provided in the master processor (CPU0), an address specifying section (11) for specifying the start address of the loaded initial startup program (60), and an address specifying section (11) for specifying the start address of the loaded initial startup program (60); An execution means (step 4) for reading the start address from the address specifying section (11) and executing the initial startup program (60) is connected to the slave processor (CPLIL).
).

[Effect]

The master CPU0 loads the initial startup program 60 of the slave CPUI from the file 6 into the shared memory 5, and notifies the slave CPUI of the initial startup program 60.

With this notification, the slave CPUI
The first address is read from 1 and executed.

For example, if a processor equipped with a vector for reset processing is used as the slave CPUI, the master CPU
By canceling the reset with the notification of 0, the vector (address specification section 11) assigned to the reset process
The contents of is set in the program counter PC of the slave CPU 1, and the slave CPU runs from that address (the start address of the initial startup program 60).

With the above, the initial startup program 60 is transferred to the slave CPU.
Initial startup processing can be performed on the shared memory 5 without being transferred to the specific memory 3 of I, and the amount of firmware can be reduced.

Note that the initial startup program 60 of this method includes initial settings that were conventionally performed by firmware.

〔Example〕

An embodiment of the present invention will be described with reference to FIG.

This embodiment shows an example in which a processor equipped with a vector for reset processing is used as the slave CPUI.

FIG. 2(a) is a block diagram of the multiprocessor system of the embodiment, FIG. 2(fb) is an operation explanatory diagram, and FIG. 2(fc) is an operational flowchart.

In this embodiment as well, the master CPU is CPU0. Let slave CPU be CPUI~n, slave L'-sub CPUI
Explain the initial startup of.

In FIG. 2(a), 10 is a reset unit, which sends out a reset signal 53 when the power is turned on or when the reset key is pressed to reset the slave CPU.
11 is an address designation part to which the address of the vector 23 for reset processing of the slave CPU 1 is assigned, and is shared. The start address 54 of the initial startup program 60 stored in the memory 5 is set. The notification signal 52 is output to the slave CPUI after the mask CPU 0 transfers the initial startup program 60 to the shared memory 5. The same reference numerals represent the same objects throughout the design.

Note that the execution means 14 includes the reset unit 10 and the CPU
Compatible with processors.

The operation will be explained below.

(1) The master CPU 0 stores the initial startup program 60 from the file 6 in the private memory 2, transfers it to the specified area of the shared memory I 75, and outputs the notification signal 52 to the slave CPU I.

(2) As shown in FIG. 2(b), the reset unit 10 holds the reset signal 53 (“L” level) when the power is turned on or the reset key is pressed, but the notification signal 5
2 to cancel (H” level).

As a result, the slave CPUI fetches the vector 23 assigned to the reset process and sets it in the program counter PC (not shown).

Since the address specifying unit 11 is assigned the vector address and the starting address 54 on the shared memory 5 of the initial startup program 60 is sent, this starting address 54 is sent to the program counter PC of the slave cput. , the initial startup program 60 is executed.

The initial startup program 60 is composed of a program for initial settings conventionally stored in the firmware 51, nine diagnostic programs, O8, and the like.

In the above embodiment, the address setting unit 11 is fixed, that is, the start address 54 of the initial startup program 60 is fixed.
This may be configured with a register or the like so that the start address 54 is set by the mask CPU0.

As described above, the initial startup program can be executed on the shared memory without having separate firmware, which reduces the amount of firmware and allows for flexible system configuration.

〔Effect of the invention〕

The present invention reduces firmware for initial startup,
Since the system is configured so that the initial startup program is started using the "shared memory", the effects of reducing costs and being able to flexibly respond to changes in the system are extremely large.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the principle of the present invention, Fig. 2 (a) is a block diagram of the multi-processor system system J of the embodiment - 9 Fig. 2 (b) is an explanatory diagram of the operation, Fig. This is an explanatory diagram of a conventional initial startup method. In the diagram, 2 to 4 are specific memories, 5 is a coexisting memory, 6 is a file, 10 is a reset section, 11 is an address specification section, 13 is an initial startup control section, and 14 is a execution means,
20 is an individual area, 21 is a common area, 23 is a vector for reset processing, 50, 60 is an initial startup program, 51 is firmware, 52 is a notification signal, 53 is a reset signal, 54 is a start address, 100 is a bus line, CPU01. '! , master processor (mask CPU
), CPUI, and CPUn are slave processors (slave processors/
- CPU), is. Figure 1 Operation flowchart 1/Figure 2 (C1 Figure 2 + al Figure 2 IQ) 1

Claims (1)

[Claims] Master processor (CPU0) and slave processor (
In a multiprocessor system in which a slave processor (CPU 1) and a CPU 1 commonly access a shared memory (5), an initial startup program (
60) into the common memory (5), and executes the initial startup program (60) on the slave processor (CP).
The master processor (CPU0) is provided with an initial startup control section (13) for instructing U1), an address specifying section (11) for specifying the start address of the loaded initial startup program (60), and The slave processor (CPU 1) includes an execution means (14) that reads the start address from the address designation section (11) and executes the initial startup program (60).
An initial startup method for a processor, characterized in that a master processor (CPU0) loads an initial startup program (60) into a shared memory (5) and performs initial startup of the slave processor (CPU1).