WO2020177577A1

WO2020177577A1 - Method and apparatus for controller to load multi-core firmware, and computer device

Info

Publication number: WO2020177577A1
Application number: PCT/CN2020/076595
Authority: WO
Inventors: 杨志佳; 冯元元; 周强
Original assignee: 深圳忆联信息系统有限公司
Priority date: 2019-03-07
Filing date: 2020-02-25
Publication date: 2020-09-10
Also published as: CN109901890A; CN109901890B

Abstract

A method and apparatus for a controller to load multi-core firmware, and a computer device. The method comprises: a first CPU operates a boot code (S10); the boot code loads a multi-core firmware loading project from Nandflash (S20); the first CPU operates the multi-core firmware loading project (S30); a Nandflash controller moves multi-core firmware of each page in the Nandflash to a specified storage area of a CPU (S60); the multi-core firmware loading project operated by the first CPU releases all CPUs except the first CPU, and the first CPU jumps to the zero address to operate (S80). According to the method, the use of DMA to move multi-core firmware in DRAM to a specified storage area of a specified CPU is avoided; instead, multi-core firmware of each page in Nandflash is directly moved to the specified storage area of the CPU by means of a Nandflash controller, thereby greatly reducing the time for the controller to load the multi-core firmware.

Description

Method, device and computer equipment for controller to load multi-core firmware

This application requires the priority of the Chinese patent application filed at the Chinese Patent Office on March 7, 2019 with the application number 201910170875.9 and the invention title "A method, device, computer equipment and storage medium for loading multi-core firmware for a controller" Right, the entire contents of which are incorporated in this application by reference.

Technical field

This application relates to the technical field of solid-state hard disks, and in particular to a method, device and computer equipment for a controller to load multi-core firmware.

Background technique

The Bootloader (multi-core firmware loading project) of the solid-state hard disk controller runs in a single CPU, and its function is to load the multi-core firmware from Nandflash to the storage area of the controller to run. Considering that the multi-core firmware file is usually large, the controller usually reads and caches the multi-core firmware from Nandflash to DRAM (Dynamic Random Access Memory), and then moves the firmware.

The process of loading multi-core firmware is shown in Figure 1. After the controller chip is powered on, the Bootrom (startup code) solidified in the controller runs first, and the bootrom will load the Bootloader from the designated area of NandFlash to run. Bootloader will initialize the modules related to the controller, including CRM (clock module), NFC (NandFlash controller), DMAC (direct memory access module controller), and DRAM. Bootloader applies for a cache space in SRAM (Static Random Access Memory), the controller reads the data of each Page to this cache space, and the first CPU (CPU0) copies the data in the cache to DRAM in order Until the multi-core firmware has been read. At this time, the complete multi-core firmware is stored in the DRAM of the solid state drive. Because CPU0 cannot move the data in DRAM to the ITCM (kernel instruction operating area) or DTCM (kernel data operating area) of other CPUs through CPU copy, the data can only be transferred through external modules, usually the controller uses DMA to transfer Move the multi-core firmware to the designated storage area of the designated CPU. CPU0 then releases other CPUs, allowing other CPUs to run normally, and CPU0 then jumps to zero address to run. At this time, all CPUs are running the system-wide multi-core firmware normally.

Usually the solid-state hard disk controller Bootloader has high requirements for loading multi-core firmware. Once the startup time is too long, the solid-state hard disk and the host cannot send and receive commands normally.

The above method has the following problems: usually the multi-core firmware file is large, and the existing bootloader needs to move the data from the particle to the specified storage area of the specified CPU three times. First, move it from NandFlash to a cache through NFC, and then copy it through the CPU. The method is moved from the cache to the DRAM. Finally, the DMAC is used to move the data in the DRAM to the designated location of each CPU. It takes too long to load the firmware. Once the time is too long, the SSD and the host will not be able to send and receive commands normally. In addition, there are too many modules that need to be initialized, resulting in too long time for initialization.

Summary of the invention

technical problem

One of the objectives of the embodiments of the present application is to provide a method, device, and computer equipment for a controller to load multi-core firmware, so as to solve the problem of a long time for the controller to load multi-core firmware.

The solution to the problem

Technical solutions

In order to solve the above technical problems, the technical solutions adopted in the embodiments of this application are:

In a first aspect, a method for a controller to load multi-core firmware is provided, and the method includes:

The first CPU runs the startup code;

The startup code loads the multi-core firmware loading project from Nandflash;

The first CPU runs the multi-core firmware loading project;

The Nandflash controller moves the multi-core firmware of each page in Nandflash to the designated storage area of the CPU;

The multi-core firmware loading project run by the first CPU releases all CPUs except the first CPU, and the first CPU jumps to the zero address to run.

In a second aspect, there is provided a device for a controller to load multi-core firmware, the device including a first running unit, a loading unit, a second running unit, a moving unit, and a releasing unit;

The first running unit is configured to run the startup code by the first CPU;

The loading unit is used for starting code to load a multi-core firmware loading project from Nandflash;

The second running unit is used for the first CPU to run the multi-core firmware loading project;

The moving unit is used for the Nandflash controller to move the multi-core firmware of each page in Nandflash to the designated storage area of the CPU;

The release unit is used for the multi-core firmware loading project run by the first CPU to release all CPUs except the first CPU, and the first CPU then jumps to zero address to run.

In a third aspect, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and capable of running on the processor. The processor implements the controller described in the first aspect when the processor executes the computer program Steps of the method of loading multi-core firmware.

In a fourth aspect, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the method for loading multi-core firmware by the controller in the first aspect are realized.

The beneficial effects of the method and device for loading multi-core firmware by the controller provided by the embodiments of the application and the computer equipment are: the method for loading multi-core firmware by the controller provided by the present application avoids using DMA to move the multi-core firmware in the DRAM to a specified The designated storage area of the CPU, instead of directly moving the multi-core firmware of each page in Nandflash to the designated storage area of the CPU through the Nandflash controller, greatly reducing the time for the controller to load the multi-core firmware. In addition, the use of clock modules, direct memory access module controllers, and dynamic random access memory is eliminated, further shortening the time for multi-core firmware loading.

The beneficial effects of the invention

Brief description of the drawings

Description of the drawings

In order to more clearly describe the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings that need to be used in the embodiments or exemplary technical descriptions. Obviously, the drawings in the following description are only for the present application. For some embodiments, those of ordinary skill in the art can obtain other drawings based on these drawings without creative work.

Figure 1 is a flow chart of loading multi-core firmware for a prior art controller;

2 is a flowchart of a specific embodiment of a method for a controller to load multi-core firmware according to this application;

3 is a schematic structural diagram of a specific embodiment of an apparatus for loading multi-core firmware by a controller according to this application;

FIG. 4 is a schematic block diagram of a specific embodiment of a computer device according to this application.

Invention embodiment

Embodiments of the invention

In order to make the purpose, technical solutions, and advantages of this application clearer, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the application, and not used to limit the application.

As shown in Figure 2, the present application provides a method for a controller to load multi-core firmware. The method includes the following steps:

S10. The first CPU runs the startup code;

S20. The startup code loads the multi-core firmware loading project from Nandflash;

S30. The first CPU runs the multi-core firmware loading project;

S40. Initialize the Nandflash controller;

S50. The multi-core firmware loading project reads the first page of the channel where the multi-core firmware is located to obtain information about the movement of the multi-core firmware;

S60, Nandflash controller moves the multi-core firmware of each page (page) in Nandflash to the designated storage area of the CPU;

S70. Judge whether all pages have been read, if yes, go to step S80, if no, go back to step S60;

S80. The multi-core firmware loading project run by the first CPU releases all CPUs except the first CPU, and the first CPU jumps to the zero address to run.

Specifically, in step S50, the relevant information includes the designated CPU number, the storage area address, and the moved data length. In step S60, the designated storage area is the kernel data operation area and the kernel instruction operation area.

When the chip of the solid state drive is powered on, the first CPU (referred to as CPU0) runs the startup code. The startup code will load the multi-core firmware loading project from Nandflash, and then CPU0 will run the multi-core firmware loading project. After the multi-core firmware loading project runs, only Load the Nandflash controller (NFC) required by the multi-core firmware to the project for related initialization operations. The SSD controller uses NFC to directly move the firmware in each page to the kernel data operation area and kernel instruction operation area of the designated CPU through the SSD system bus. Since the related information of the multi-core firmware movement is stored in the first page of Nandflash, the controller first reads the first page in Nandflash before moving the data to obtain the relevant information of the multi-core firmware. After the data is moved, the multi-core firmware loading project run by CPU0 releases all CPUs except CPU0, and CPU0 jumps to the zero address to run, thereby making the multi-core firmware run successfully.

It should be understood that the size of the sequence number of each step in the foregoing embodiment does not mean the order of execution. The execution sequence of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiment of the present application.

Corresponding to the method for a controller to load multi-core firmware described in the foregoing embodiment, the present application provides an apparatus for a controller to load multi-core firmware. As shown in Figure 3, the device includes a first operating unit 1, a loading unit 2, a second operating unit 3, a moving unit 4 and a releasing unit 5, an initialization unit 6, a reading unit 7, and a judgment unit 8;

The first running unit 1 is used for the first CPU to run the startup code;

Loading unit 2, used to load the multi-core firmware loading project from Nandflash with the startup code;

The second running unit 3 is used for the first CPU to run the multi-core firmware loading project;

The moving unit 4 is used for the Nandflash controller to move the multi-core firmware of each page in Nandflash to the designated storage area of the CPU;

The release unit 5 is used for the multi-core firmware loading project run by the first CPU to release all CPUs except the first CPU, and the first CPU then jumps to zero address to run;

The initialization unit 6 is used to initialize the Nandflash controller;

The reading unit 7 is used for the multi-core firmware loading project to read the first page of the channel where the multi-core firmware is located, so as to obtain information about the movement of the multi-core firmware;

The judging unit 8 is used to judge whether all pages have been read.

Specifically, the related information includes the designated CPU number, storage area address, and moved data length. The designated storage area is the kernel data operation area and the kernel instruction operation area.

When the chip of the solid state drive is powered on, the first CPU (referred to as CPU0) runs the startup code. The startup code will load the multi-core firmware loading project from Nandflash, and then CPU0 will run the multi-core firmware loading project. After the multi-core firmware loading project runs, only Load the Nandflash controller (NFC) required by the multi-core firmware to the project for related initialization operations. The SSD controller uses NFC to directly move the firmware in each page to the kernel data operation area and kernel instruction operation area of the designated CPU through the SSD system bus. Since the related information of the multi-core firmware movement is stored in the first page of Nandflash, the controller first reads the first page in Nandflash before moving the data to obtain the relevant information of the multi-core firmware. After the data is moved, the multi-core firmware loading project run by CPU0 releases all CPUs except CPU0, and CPU0 jumps to the zero address to run, thus making the multi-core firmware run successfully.

As shown in FIG. 4, the present application also provides a computer device, including a memory, a processor, and a computer program stored in the memory and running on the processor. When the processor executes the computer program, the controller can be loaded as described above. Method steps for multi-core firmware.

The computer device 700 may be a terminal or a server. The computer device 700 includes a processor 720, a memory, and a network interface 750 connected through a system bus 710, where the memory may include a non-volatile storage medium 730 and an internal memory 740.

The non-volatile storage medium 730 can store an operating system 731 and a computer program 732. When the computer program 732 is executed, the processor 720 can execute any method for the controller to load multi-core firmware.

The processor 720 is used to provide computing and control capabilities, and support the operation of the entire computer device 700.

The internal memory 740 provides an environment for the operation of the computer program 732 in the non-volatile storage medium 730. When the computer program 732 is executed by the processor 720, the processor 720 can execute any method for loading multi-core firmware by the controller.

The network interface 750 is used for network communication, such as sending assigned tasks. Those skilled in the art can understand that the structure shown in FIG. 4 is only a block diagram of part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device 700 to which the solution of the present application is applied. The specific computer device 700 may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement. Wherein, the processor 720 is configured to run the program code stored in the memory to implement the following steps:

The first CPU runs the startup code;

The startup code loads the multi-core firmware loading project from Nandflash;

The first CPU runs the multi-core firmware loading project;

In this application, after the first CPU runs the multi-core firmware loading project, it further includes the following steps:

Initialize the Nandflash controller;

The multi-core firmware loading project reads the first page of the channel where the multi-core firmware is located to obtain information about the movement of the multi-core firmware.

In this application, after the Nandflash controller moves the multi-core firmware of each page in Nandflash to the designated storage area of the CPU, it further includes the following steps:

Determine whether all pages have been read;

If yes, enter the multi-core firmware loading project run by the first CPU to release all CPUs except the first CPU, and the first CPU then jumps to the zero address operation step;

If not, return to the Nandflash controller to move the multi-core firmware of each page in Nandflash to the designated storage area of the CPU.

It should be understood that in the embodiment of the present application, the processor 720 may be a central processing unit (Central Processing Unit, CPU), and the processor 720 may also be other general-purpose processors, digital signal processors (Digital Signal Processors, DSPs), Application Specific Integrated Circuit (ASIC), Field-Programmable Gate Array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor may be a microprocessor or the processor may also be any conventional processor.

Those skilled in the art can understand that the structure of the computer device 700 shown in FIG. 4 does not constitute a limitation on the computer device 700, and may include more or less components than shown, or a combination of certain components, or different components Layout.

If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the embodiments of the present application essentially or the part that contributes to the prior art or all or part of the technical solutions can be embodied in the form of software products, and the computer software products are stored in a storage The medium includes several instructions to enable a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program code .

Those skilled in the art can clearly understand that for the convenience and conciseness of description, only the division of the above-mentioned functional units and modules is used as an example. In practical applications, the above-mentioned functions can be allocated to different functional units and modules as required. Module completion means dividing the internal structure of the device into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist alone physically, or two or more units can be integrated into one unit. The above-mentioned integrated units can be hardware-based Formal realization can also be realized in the form of software functional units. In addition, the specific names of the functional units and modules are only used to facilitate distinguishing each other, and are not used to limit the protection scope of the present application. For the specific working process of the units and modules in the above-mentioned device, reference may be made to the corresponding process in the foregoing method embodiment, which is not repeated here.

A person of ordinary skill in the art may be aware that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be implemented by electronic hardware or a combination of computer software and electronic hardware. Whether these functions are executed by hardware or software depends on the specific application and design constraint conditions of the technical solution. Professionals and technicians can use different methods for each specific application to implement the described functions, but such implementation should not be considered beyond the scope of this application.

In the embodiments provided in this application, it should be understood that the disclosed device and method may be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods, for example, multiple units or components may be It can be combined or integrated into another device, or some features can be omitted or not implemented. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.

In addition, the functional units in the various embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or software functional unit.

The above only uses examples to illustrate the technical content of this application for easier understanding of readers, but it does not mean that the implementation of this application is limited to this. Any technical extension or re-creation made according to this application is subject to this application. protection. The scope of protection of this application is subject to the claims.

Claims

A method for a controller to load multi-core firmware, characterized in that the method includes:

The first CPU runs the startup code;

The startup code loads the multi-core firmware loading project from Nandflash;

The first CPU runs the multi-core firmware loading project;

The Nandflash controller moves the multi-core firmware of each page in Nandflash to the designated storage area of the CPU;

The multi-core firmware loading project run by the first CPU releases all CPUs except the first CPU, and the first CPU jumps to the zero address to run.
The method for loading multi-core firmware by a controller according to claim 1, wherein the Nandflash controller moves the multi-core firmware of each page in Nandflash to a designated storage area of the CPU, and the designated storage area is the kernel. Data operation area and kernel instruction operation area.
The method for loading multi-core firmware by a controller according to claim 1, wherein after the step of running the multi-core firmware loading project by the first CPU, the method further comprises the following steps:

Initialize the Nandflash controller;

The multi-core firmware loading project reads the first page of the channel where the multi-core firmware is located to obtain information about the movement of the multi-core firmware.
The method for loading multi-core firmware by a controller according to claim 1, wherein the multi-core firmware loading project reads the first page of the channel where the multi-core firmware is located to obtain information related to the movement of the multi-core firmware. The related information includes the designated CPU number, storage area address, and moved data length.
The method for loading multi-core firmware by a controller according to claim 1, wherein after the step of moving the multi-core firmware of each page in Nandflash by the Nandflash controller to the designated storage area of the CPU, the method further comprises the following steps:

Determine whether all pages have been read;

If yes, enter the multi-core firmware loading project run by the first CPU to release all CPUs except the first CPU, and the first CPU then jumps to the zero address operation step;

If not, return to the Nandflash controller to move the multi-core firmware of each page in Nandflash to the designated storage area of the CPU.
A device for a controller to load multi-core firmware, characterized in that the device includes a first running unit, a loading unit, a second running unit, a moving unit, and a releasing unit;

The first running unit is configured to run the startup code by the first CPU;

The loading unit is used for starting code to load a multi-core firmware loading project from Nandflash;

The second running unit is used for the first CPU to run the multi-core firmware loading project;

The moving unit is used for the Nandflash controller to move the multi-core firmware of each page in Nandflash to the designated storage area of the CPU;

The release unit is used for the multi-core firmware loading project run by the first CPU to release all CPUs except the first CPU, and the first CPU then jumps to zero address to run.
The device for loading multi-core firmware by a controller according to claim 6, wherein the Nandflash controller moves the multi-core firmware of each page in Nandflash to a designated storage area of the CPU, and the designated storage area is the kernel. Data operation area and kernel instruction operation area.
The device for loading multi-core firmware by a controller according to claim 6, wherein the device further comprises an initialization unit and a reading unit;

The initialization unit is used to initialize the Nandflash controller;

The reading unit is used for the multi-core firmware loading project to read the first page of the channel where the multi-core firmware is located, so as to obtain information about the movement of the multi-core firmware.
The device for loading multi-core firmware by a controller according to claim 6, wherein the multi-core firmware loading project reads the first page of the channel where the multi-core firmware is located to obtain information related to the movement of the multi-core firmware. Related information includes the designated CPU number, storage area address, and the length of the moved data.
The device for loading multi-core firmware by a controller according to claim 6, wherein the device further comprises a judgment unit;

The judging unit is used to judge whether all pages have been read;

If yes, enter the multi-core firmware loading project run by the first CPU to release all CPUs except the first CPU, and the first CPU then jumps to the zero address operation step;

If not, return to the Nandflash controller to move the multi-core firmware of each page in Nandflash to the designated storage area of the CPU.
A computer device comprising a memory, a processor, and a computer program stored on the memory and capable of running on the processor, wherein the processor implements the following steps when the processor executes the computer program:

The first CPU runs the startup code;

The startup code loads the multi-core firmware loading project from Nandflash;

The first CPU runs the multi-core firmware loading project;

The Nandflash controller moves the multi-core firmware of each page in Nandflash to the designated storage area of the CPU;

The multi-core firmware loading project run by the first CPU releases all CPUs except the first CPU, and the first CPU jumps to the zero address to run.
The computer device according to claim 11, wherein the Nandflash controller moves the multi-core firmware of each page in Nandflash to a designated storage area of the CPU, and the designated storage area is the kernel data operating area and the kernel Command operation area.
The computer device according to claim 11, wherein the processor further implements the following steps when executing the computer program:

Initialize the Nandflash controller;

The multi-core firmware loading project reads the first page of the channel where the multi-core firmware is located to obtain information about the movement of the multi-core firmware.
The computer device according to claim 11, wherein the multi-core firmware loading project reads the first page of the channel where the multi-core firmware is located to obtain information related to the movement of the multi-core firmware. In the step, the related information includes The specified CPU number, storage area address, and data length to be moved.
The computer device according to claim 11, wherein the processor further implements the following steps when executing the computer program:

Determine whether all pages have been read;

If yes, enter the multi-core firmware loading project run by the first CPU to release all CPUs except the first CPU, and the first CPU then jumps to the zero address operation step;

If not, return to the Nandflash controller to move the multi-core firmware of each page in Nandflash to the designated storage area of the CPU.
A computer-readable storage medium having a computer program stored thereon, the computer program including program instructions, wherein the program instructions are executed by a processor to cause the processor to perform the following steps:

The first CPU runs the startup code;

The startup code loads the multi-core firmware loading project from Nandflash;

The first CPU runs the multi-core firmware loading project;

The Nandflash controller moves the multi-core firmware of each page in Nandflash to the designated storage area of the CPU;

The multi-core firmware loading project run by the first CPU releases all CPUs except the first CPU, and the first CPU jumps to the zero address to run.
The computer-readable storage medium according to claim 16, wherein the Nandflash controller moves the multi-core firmware of each page in Nandflash to a designated storage area of the CPU, and the designated storage area is kernel data running The area and the kernel command execution area.
The computer-readable storage medium according to claim 16, wherein when the program instructions are executed by a processor, the processor further executes the following steps:

Initialize the Nandflash controller;

The multi-core firmware loading project reads the first page of the channel where the multi-core firmware is located to obtain information about the movement of the multi-core firmware.
The computer-readable storage medium according to claim 16, wherein the multi-core firmware loading project reads the first page of the channel where the multi-core firmware is located to obtain information related to the movement of the multi-core firmware. Including the specified CPU number, storage area address, and data length to be moved.
The computer-readable storage medium according to claim 16, wherein when the program instructions are executed by a processor, the processor further executes the following steps:

Determine whether all pages have been read;

If yes, enter the multi-core firmware loading project run by the first CPU to release all CPUs except the first CPU, and the first CPU then jumps to the zero address operation step;

If not, return to the Nandflash controller to move the multi-core firmware of each page in Nandflash to the designated storage area of the CPU.