JP2012137946A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multiprocessor system which can flexibly adapt to a requested specification.SOLUTION: A semiconductor device (10) includes: a start instruction section (72) for instructing data processors (1 to 3) to be started based on first information (720) to be input when power-on reset; a master instruction section (73) for instructing the data processors to be converted into masters based on second information (730) to be input when the power-on reset; and address instruction sections (74 and 75) for instructing information on an initial address in a program region executed by the data processors which have been instructed to start based on third information (740) to be input when the power-on reset or fourth information (746 and 751) to be set from the data processors started after the power-on reset.

Description

  The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a large-scale integrated circuit incorporating a plurality of data processors.

  In recent years, dedicated circuits for high-speed execution of specific functions such as compression and decompression of images and voices in accordance with high performance and multi-functionality of small information devices such as mobile phones, portable navigation devices, and portable terminals for business use. A large-scale integrated circuit (hereinafter referred to as “multiprocessor”) that incorporates multiple modules, CPUs (Central Processing Unit) that play the core role of the system, and other types of CPUs with different instruction sets from the CPU in the same package Also called development). For example, in a multiprocessor system for a mobile phone, each processing unit such as a communication unit that mainly performs baseband processing such as a call or mail transmission, an application unit that executes processing for video playback, and other system units Has a CPU and a dedicated circuit module for realizing a specific function, and constitutes a multiprocessor having a plurality of CPUs as a whole. Such a multiprocessor system often has a configuration in which a specific CPU is a master CPU for managing other CPUs, and other CPUs are slave CPUs. Which CPU is the master CPU is determined according to, for example, the specifications of the final product. In the case of the above-described multiprocessor system for mobile phones, the CPU of the communication unit is the master CPU, and the other CPUs are slaves. Some are configured as CPUs, and some are vice versa.

  One technique for switching between a master and a slave on the system is disclosed in, for example, Patent Document 1. In the technique of Patent Document 1, when one data signal control circuit among the plurality of data signal control circuits is a master having the control right of the data bus and the other data signal control circuit is a slave, there is a problem with the master. This is a technology that prevents the entire system from being stopped by switching between the master and slave when it occurs.

Japanese Patent Laid-Open No. 5-122232

  By the way, in the development of software for debugging and dedicated processing in the initial stage of product development using a multiprocessor system, if the CPU as the master is fixed, the boot code of the master CPU is required. In product development using the aforementioned multiprocessor system for mobile phones, for example, a product developer has a boot code related to the CPU of the application unit as a past software resource, but has a boot code of the CPU of the communication unit. If not, development is facilitated by starting from the CPU of the application unit having the boot code and then starting the CPU of the communication unit. However, if the master CPU is fixed to the CPU of the communication unit, it is necessary to start the CPU before other CPUs, so it is necessary to newly develop a boot code for the CPU of the communication unit. This leads to an increase in the boot code development cost.

  Furthermore, in future multi-processor design and development, it is necessary to develop a highly versatile semiconductor product that can be used for other products in order to reduce development costs. However, the technique of Patent Document 1 described above does not consider which data signal control circuit is set as a master when the system is activated, which data signal control circuit is activated first.

  An object of the present invention is to provide a multiprocessor system that can flexibly cope with required specifications.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, the semiconductor device includes a start instruction unit for instructing a data processor to be started based on first information input at the time of power-on reset, and a data processor to be a master based on second information input at the time of power-on reset And a program executed by the data processor instructed to start based on the third information input at the time of power-on reset or the fourth information set by the data processor started up after the power-on reset And an address instruction unit for instructing information on the head address of the area.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to this semiconductor device, it is possible to flexibly cope with the required specifications.

FIG. 1 is a block diagram of a microprocessor incorporating a plurality of CPUs according to the present embodiment. FIG. 2 is an explanatory diagram when the CPU 1 and the CPU 2 are activated. FIG. 3 is an explanatory diagram when the CPU 2 is activated. FIG. 4 is an explanatory diagram when the CPU 1 is activated as a master. FIG. 5 is an explanatory diagram when the CPU 2 is activated as a master. FIG. 6 is an explanatory diagram when both the CPU 1 and the CPU 2 are activated and the CPU 1 is set as a master at the time of activation. FIG. 7 is an explanatory diagram when only the CPU 1 is activated. FIG. 8 is an explanatory diagram in the case where the CPUs 1 to 3 are activated and the CPU 1 is activated as a master. FIG. 9 is an explanatory diagram including the activation CPU selection unit 72 and the master CPU selection unit 73 in the case of FIG. FIG. 10 is a block diagram illustrating an example of the internal configuration of the power supply control unit 71. FIG. 11 is a flowchart showing an example of the flow of power control by the power control unit 71 when power is turned on. FIG. 12 is an explanatory diagram when the power is shut off after the power-on reset. FIG. 13 is a flowchart showing an example of the flow of control for power shutdown. FIG. 14 is an explanatory diagram in the case where power is restored after a power-on reset. FIG. 15 is a flowchart illustrating an example of a flow of control for power recovery. FIG. 16 shows an example of a state transition diagram of a multiprocessor that does not have a power shutdown function. FIG. 17 shows an example of a state transition diagram of the microprocessor 10 according to the present embodiment. FIG. 18 is an explanatory diagram of the activation target memory designation register 741. FIG. 19 is an explanatory diagram when a memory to be read at the time of activation is designated. FIG. 20 is an explanatory diagram of the activation address designation register 742. FIG. 21 is an explanatory diagram of the activation address control unit 75. FIG. 22 is an explanatory diagram of the clock control register 743. FIG. 23 is an explanatory diagram of the system reset control register 744. FIG. 24 is a flowchart illustrating an example of a process flow when switching between the slave CPU and the master CPU. FIG. 25 is an explanatory diagram illustrating an example of the storage locations of the master boot codes and slave boot codes of the CPUs 1 to 3.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

[1] (Semiconductor device capable of selecting a master CPU and a CPU to be activated)
A semiconductor device (10) according to a typical embodiment of the present invention includes a plurality of data processors (1 to 3) and the data processor that is activated based on first information (720) input at the time of power-on reset. A start instruction unit (72) for instructing the data processor, a master instruction unit (73) for instructing the data processor to be a master based on the second information (730) input at the time of power-on reset, and an input at the time of power-on reset Of the program area executed by the data processor instructed to start based on the third information (740) to be executed or the fourth information (746, 751) set from the data processor started after the power-on reset. And an address instruction section (74, 75) for instructing address information.

  According to this, it is possible to freely select a data processor to be activated and a data processor as a master according to the specifications of the system to be developed, which contributes to the effective use of existing hardware resources and software resources. For example, by making it possible to select a data processor to be activated, it becomes possible to select and use the data processor necessary for the system, so that hardware resources can be effectively utilized. However, in many cases, existing software resources cannot be used by themselves alone. Therefore, according to the semiconductor device, it is possible to select a data processor to be a master at power-on, and separately designate the head address at the time of power-on reset and the head address after the power-on reset. Therefore, for example, the data processor started as a slave at power-on can be restarted as a master, or the data processor started as a master can be restarted as a slave. As an example, consider a case where the present semiconductor device is applied in a situation where there is a CPU boot code that is a slave during normal operation as a past software asset, but there is no CPU boot code that is a master during normal operation. In this case, first, the data processor that is normally set as a slave is activated as a master, and the activated data processor causes the data processor that is normally set as a master to be activated as a slave. Thereafter, by switching the start address of the program area executed by the data processor activated as the slave to the start address of the master program area, the data processor activated as the slave can be restarted as the master. According to this, it is not necessary to newly develop the boot code of the data processor that originally operates as a master, and the existing software assets can be effectively used, so that the development cost of the boot code can be suppressed. Become.

[2] (Selectable by external terminal)
The semiconductor device according to Item 1, further including external terminals (P1 to P12) to which data is input, wherein the first information to the third information are data input from the external terminal.

  According to this, it is possible to easily select the data processor to be activated and the master data processor.

[3] (Selectable by the value read from the fuse)
The semiconductor device according to Item 1, further including a nonvolatile storage unit in which data is stored, wherein the first information to the third information are data input from the storage unit.

  According to this, it is possible to easily select the data processor to be activated and the master data processor, and it is not necessary to provide an external terminal.

[4] (Operation of address instruction unit)
In the semiconductor device according to any one of Items 1 to 3, in response to a power-on reset, the address instruction unit instructs the data processor, which is instructed to start, the head address based on the third information, In response to the system reset after the power-on reset, the head address based on the fourth information is instructed to the data processor instructed to start.

  According to this, for example, a program to be executed after canceling the system reset and a program to be executed after canceling the power-on reset can be made different programs.

[5] (Any address can be specified)
In the semiconductor device according to Item 4, the address instruction unit further includes an activation address control unit (75) in which address information specified by the data processor as a master is stored, and the fourth information is the activation It includes information indicating that the head address is designated based on the address information stored in the address control unit.

  According to this, since the start address of the program area executed by the CPU after the system reset can be set to an arbitrary address designated by the master CPU, the degree of freedom of program mapping is increased.

[6] (Address is fixed)
In the semiconductor device according to Item 4 or 5, the fourth information includes information instructing to use a fixed address as the head address.

[7] (Latch circuit in which the fourth information is set)
In the semiconductor device according to any one of Items 4 to 6, the address instruction unit includes a latch circuit (742) in which the fourth information is set.

  According to this, once the activated data processor outputs the fourth information, the value is set in the latch circuit, so that the data processor does not need to output the fourth information each time. Good.

[8] (Power supply control)
The semiconductor device according to any one of Items 1 to 7, further including a power control unit (71) for managing power supplied to the data processor, wherein the power control unit is based on an instruction from the activation instruction unit. Then, power is supplied to the selected data processor.

  According to this, it becomes easy to start the data processor specified at the time of power-on.

[9] (Power shutdown control)
In the semiconductor device according to Item 8, the power supply control unit stops supply of power to the data processor selected based on an instruction from the activated data processor.

  According to this, since the activated data processor can be stopped, for example, if the power supply of the data processor is stopped after the specific processing by the data processor is finished, compared with a standby state in which the power is not turned off. This contributes to lower power consumption.

[10] (Power recovery control)
In the semiconductor device according to Item 8 or 9, the power control unit supplies power to the data processor selected based on an instruction from the activated data processor.

  According to this, it is possible to operate the data processor once the power supply has been stopped, and to start the data processor that was not started at the time of power-on later. The degree increases.

[11] (Clock signal supply and stop)
Item 12. The semiconductor device according to any one of Items 1 to 10, further including a clock signal control unit (743, 76) that controls supply of a clock signal to the data processor instructed to start, Control is performed to supply and stop the clock signal to the data processor selected based on the first information input at the time of power-on reset or an instruction from the data processor as a master.

  According to this, it is possible to contribute to power saving of the semiconductor device, and it is possible to shorten the time required for restarting the operation compared to the case where the power supply to the data processor is stopped. For example, when the power supply is stopped to stop the operation of the data processor, it is necessary to supply the power again to restart the data processor, but until the voltage stabilizes after the power is supplied. It may take time to increase the time until the operation is restored. On the other hand, according to the semiconductor device of item 11, since the clock signal is stopped and supplied in a state where the power is supplied, the time required to restart the operation can be shortened.

  Also, according to the semiconductor device of item 11, it is possible to supply a clock signal only to the data processor that has been instructed to start, and it is possible to suppress the supply of useless clock signals. Further, even when the data processor that was not started at the time of power-on is started after that, a clock signal can be supplied in response to the start-up.

[12] (Clock signal supply)
14. The semiconductor device according to Item 11, wherein the clock signal control unit supplies a clock signal to the data processor selected based on the first information input at the time of power-on reset or an instruction from the data processor as a master. Let

[13] (Power status management)
Item 12. The semiconductor device according to any one of Items 1 to 12, wherein the power supply control unit includes a power management register that holds information indicating a power supply state to the data processor, and the electrical management register is after the power-on reset is canceled. The value corresponding to the first information is held, and the value is updated according to an instruction relating to supply or stop of power from the data processor as a master.

  According to this, it becomes possible to grasp the power supply state to each of the data processors.

[14] (Data processors with different architectures)
Item 14. The semiconductor device according to any one of Items 1 to 13, wherein the plurality of data processors include data processors having different architectures.

[15] (Data processor for communication and image processing)
Item 14. The semiconductor device according to any one of Items 1 to 14, wherein the plurality of data processors include a data processor (1) that executes data processing related to communication and a data processor (3) that executes data processing related to an image. .

2. Details of Embodiments Embodiments will be further described in detail.

<< Configuration of Microprocessor 10 >>
FIG. 1 is a block diagram of a microprocessor incorporating a plurality of CPUs as an embodiment of a semiconductor device according to the present invention. The microprocessor 10 shown in the figure is not particularly limited, but is formed on a single semiconductor substrate such as single crystal silicon by a known CMOS integrated circuit manufacturing technique. The microprocessor 10 is an LSI for a car navigation system having a communication function, for example.

  The microprocessor 10 constitutes a multiprocessor having a plurality of CPUs. There is no particular limitation on the number of CPUs. Here, as an example, it is assumed that the microprocessor 10 includes three CPUs having different architectures, and the CPUs are referred to as CPU1, CPU2, and CPU3. The CPUs 1 to 3 are commonly connected to the internal ROM 7, the internal RAM 8, the external memory 14, and the peripheral circuits 4 to 6 through a bus 15, for example. The external memory 14 is a flash memory, for example, and is connected to the bus 15 via a memory interface (not shown). The peripheral circuits 4 to 6 are dedicated processing circuits that perform control of setting of processing conditions and the like by the CPUs 1 to 3 and execute specific processing instead of the CPUs 1 to 3. The peripheral circuits 4 to 6 are, for example, a DMAC (Direct Memory Access Controller) or a dedicated processing circuit for music reproduction.

  The CPUs 1 to 3 execute processing based on programs stored in the internal ROM 7, the internal RAM 8, or the external memory 14. Each CPU shares and executes various data processing in the car navigation system. For example, the CPU 1 is a communication CPU that mainly executes a process related to a wireless access function such as W-CDMA, and the CPU 2 is mainly based on traveling information and map information of the own vehicle equipped with a car navigation system. The CPU 3 is a CPU for image processing that executes processing for drawing map information on a monitor mainly based on map information and the calculation results. In the microprocessor 10, any one of the CPUs 1 to 3 is a master CPU, and the other CPUs are slave CPUs. The master CPU puts the slave CPU under its own management, controls the execution and stop of the data processing in each slave CPU, and manages the data processing state. The master CPU has an access right to various registers of the control unit 7 to be described later, and controls power supply to the slave CPU, clock signal supply, and the like.

  The CPUs 1 to 3 include a CPU core unit that is an execution subject of program processing, and a peripheral circuit for executing specific processing at high speed instead of the CPU core unit. For example, the CPU 1 includes a CPU core unit 11 and a peripheral circuit 12, and the peripheral circuit 12 executes specific processing according to the conditions set by the CPU core unit 11. The peripheral circuit 12 is, for example, a dedicated circuit that performs baseband processing. Similarly, the CPU 2 includes a CPU core unit 21 and a peripheral circuit 22, and the CPU 3 includes a CPU core unit 31 and a peripheral circuit 32. The peripheral circuit 13 is, for example, a dedicated circuit that performs image data compression / decompression processing. The CPU cores 11, 21, and 31, the peripheral circuits 12, 22, and 32, and the peripheral circuits 4 to 6 include power switches 16_1 to 16_9, and the controller 7 described later turns on the power switches 16_1 to 16_9. By controlling OFF, supply and stop of the power supply voltage to each circuit are controlled. This enables independent power management for each circuit.

  The microprocessor 10 further has a control unit 7. The control unit 7 controls the startup of the CPUs 1 to 3 by supplying and stopping the power supply voltage and the clock signal, the selection of the master CPU, and the program after canceling the power-on reset and after canceling the system reset by setting from the master CPU or external terminal Control such as designation of the start address of the area is executed. When a power supply voltage is supplied to the microprocessor 10 from the outside (powered on), the control unit 7 is always supplied with power. The control unit 7 includes a power supply control unit 71, a startup CPU selection unit 72, a master CPU selection unit 73, a reset control unit 74, a startup address control unit 75, and a clock control unit 76. Hereinafter, each functional unit of the control unit 7 will be described in detail.

(1) Activation CPU selection unit 72
The activation CPU selection unit 72 outputs a selection signal 722 that indicates the CPU to be activated among the CPUs 1 to 3 in the microprocessor 10 based on the information 720 indicating the CPU to be activated input from the external terminals P1 to P3. Specifically, the activation CPU selection unit 72 includes a latch circuit (register) 721 therein, and stores information 720 input from the external terminals P1 to P3 at the time of power-on reset in the register 721, based on the value thereof. A selection signal 722 is output. This makes it possible to select in advance the CPU to be activated. Note that the information 720 held in the register 721 is not limited to the method of fetching from the external terminals P1 to P3. For example, a nonvolatile storage device such as a program fuse storing information 720 indicating the CPU to be activated is used as the microprocessor 10. The information 720 may be read from the program fuse and stored in the register 721 upon power-on reset. Further, the information 720 input from the external terminals P1 to P3 only needs to be stored in the register 721 at the time of power-on reset, and thereafter, the external terminals P1 to P3 can be used as input / output terminals for other signals. is there.

  An example of a method for selecting the CPU to be activated is shown in FIGS. 2 and 3, for convenience of explanation, a case where there are two CPUs, CPU1 and CPU2, will be described as an example.

  FIG. 2 is an explanatory diagram when the CPU 1 and the CPU 2 are activated. In the figure, for example, the switch 100 provided on the substrate 200 on which the microprocessor 10 is mounted is connected to the external terminals P1 to P3, and the CPU 1 and the CPU 2 are connected by the information 720 input from the switch to the external terminals P1 to P3. Shows when it is activated. In the switch 100 in the figure, for example, the external terminals P1 to P3 are pulled up when the switch is on (ON), and the external terminals P1 to P3 are pulled down when the switch is off (OFF).

  FIG. 3 is an explanatory diagram showing an example when the CPU 2 is activated. In the figure, the case where only the CPU 2 is activated by the information 720 input from the switch 100 to the external terminals P1 to P3 is shown.

(2) Master CPU selection unit 73
Based on the information 730 indicating the CPU to be the master input from the external terminals P4 to P6, the master CPU selection unit 73 selects the selection signal 732 that instructs the CPU to be the master among the CPUs 1 to 3 in the microprocessor 10. Is output. Specifically, the master CPU selection unit 73 has a latch circuit (register) 731 inside, holds information 730 input to the external terminals P4 to P6 at the time of power-on reset in the register 731, and based on the value A selection signal 732 is output. This makes it possible to select in advance the CPU to be the master. The information 730 held in the register 731 is not limited to the method of fetching from the external terminals P4 to P6, but may be a method of reading from the program fuse and storing it in the register 731 similarly to the information 720. Similarly to the external terminals P1 to P3, the external terminals P4 to P6 can also be used as input / output terminals for other signals after power-on reset.

  A method for selecting a CPU to be a master at the time of startup is shown in FIGS. 4 to 7 described below, as an example, a case where there are two CPUs, CPU1 and CPU2, will be described for convenience of explanation.

  FIG. 4 is an explanatory diagram when the CPU 1 is activated as a master. In the figure, for example, the switch 101 provided on the substrate 200 on which the microprocessor 10 is mounted is connected to the external terminals P4 to P6, and the CPU 1 serves as the master by the information 730 input from the switch to the external terminals P4 to P6. A case where the CPU 2 is started as a slave is shown. Although the switch 101 is represented as a changeover switch in the figure, for example, a low signal is input to an unselected external terminal, and a high signal is high to a selected external terminal. Shall be entered.

  FIG. 5 is an explanatory diagram showing a case where the CPU 3 is activated as a master. In the figure, the case where the CPU 2 is activated as a master and the CPU 1 is activated as a slave is shown by the information 730 input from the switch 101 to the external terminals P4 to P6.

  FIG. 6 to FIG. 9 show an example of a combination of a CPU to be activated and a CPU as a master.

  FIG. 6 is an explanatory diagram showing a case where both the CPU 1 and the CPU 2 are activated and the CPU 1 is used as a master. In the figure, information 720 for instructing activation of CPU1 and CPU2 from switch 100 is input to external terminals P1 to P3, and information 730 for instructing CPU1 to be a master from switch 101 is input to external terminals P4 to P6. The Thereby, CPU1 starts as a master CPU and CPU2 starts as a slave CPU.

  FIG. 7 is an explanatory diagram showing a case where only the CPU 1 is activated. In the figure, information 720 for instructing that only the CPU 1 is activated from the switch 100 is input to the external terminals P1 to P3. On the other hand, the information 730 specifying the CPU to be the master is not input to the external terminals P4 to P6. In this case, since only the CPU 1 is activated, the master inevitably becomes the CPU 1, so that there is no need to input from the switch 101. According to this, for example, in a system using only the CPU 1, the external terminals P <b> 4 to P <b> 6 that receive input from the switch 101 are not necessary, and the chip area of the microprocessor 1 can be reduced.

  FIG. 8 is an explanatory diagram in a case where the CPUs 1 to 3 are activated and the CPU 1 is activated as a master. In the figure, information 720 for instructing activation of the CPUs 1 to 3 from the switch 100 is input to the external terminals P1 to P3, and information 730 for instructing the CPU 1 to be the master from the switch 101 is input to the external terminals P4 to P6. The Thereby, CPU1 starts as a master CPU, and CPU2 and CPU3 start as slave CPUs.

  FIG. 9 is an explanatory diagram including the activation CPU selection unit 72 and the master CPU selection unit 73 in the case of FIG. In the figure, information 720 for instructing activation of the CPUs 1 to 3 from the switch 100 is input to the external terminals P 1 to P 3 and held in the latch circuit 721 of the activation CPU selection unit 72. The activation CPU selection unit 72 supplies a selection signal 722 to the power supply control unit 71 based on the held value, and the power supply control unit 71 that has received the selection signal 722 supplies power to the CPUs 1 to 3. Information 730 that instructs the CPU 1 to be the master from the switch 101 is input to the external terminals P4 to P6 and held in the latch circuit 731 of the master CPU selection unit 73. The master CPU selection unit 73 gives a selection signal 732 to the CPU 1 based on the held value. Thereby, CPU1 starts as a master CPU, and CPU2 and CPU3 start as slave CPUs.

(3) Power supply control unit 71
The power supply control unit 71 controls the supply of power supply voltages for the CPU1 to CPU3, the peripheral circuits 4 to 6, and other internal circuits. Specifically, the power supply voltage for each circuit is cut off, the power supply voltage is supplied, and the power supply state is monitored. Here, it demonstrates centering on the part in connection with the power supply control with respect to CPU1-3.

  FIG. 10 is a block diagram illustrating an example of the internal configuration of the power supply control unit 71. As shown in the figure, the power control unit 71 includes a power management unit 711, a power cutoff unit 712, a power recovery unit 713, a power state unit 714, a power region exclusive control unit 715, and a control signal generation unit 716.

  The power management unit 711 has a register 7111 inside, and supplies power to an area on the chip (hereinafter also referred to as “power area”) where the CPUs 1 to 3, the peripheral circuits 4 to 6, and other circuits exist. Information indicating whether or not to allow shut-off and power supply control is set in the corresponding register for each power supply area. Settings for the power management unit 711 are performed by the master CPU. For example, when the master CPU writes “1” in a portion indicating the power supply area (CPU core section 11 and peripheral circuit 12) related to CPU1 of the register 7111 of the power supply management section 711, the power supply cutoff and power supply to the power supply area related to CPU1 are written. Supply control is prohibited.

  The power shut-off unit 712 requests power shut-off to each power source area according to a value set in the register 7121 provided therein. The setting for the power shut-off unit 712 is performed by the master CPU. For example, when “1” is written to the power supply area (CPU core unit 31 and peripheral circuit 32) related to CPU 3 of the register 7121 by the CPU 1 as the master, the power cut-off unit 712 issues a cut-off instruction for the power supply area. After the power is turned off, the value is cleared to “0”.

  The power return unit 713 requests restart of power supply to each power supply area according to a value set in the register 7131 provided therein. The setting for the power return unit 713 is performed by the master CPU. For example, when “1” is written to the power supply area (CPU core unit 31 and peripheral circuit 32) related to the CPU 3 of the register 7131 by the CPU 1 as the master, the power supply return unit 713 issues a return instruction to the power supply area. Issue. Then, after the power supply is resumed, the value is cleared to “0”.

  The power supply state unit 714 includes a register 7141 therein, and a value indicating the power supply state of each power supply area is set in the register. Thereby, the power supply state of each power supply area | region of CPU1-CPU3 is monitored.

  The power supply area exclusive control unit 715 has a register 7151 therein, and information indicating whether or not to interrupt the power supply for each power supply area of the CPUs 1 to 3 is set in the register. The register 7151 is set by the master CPUs 1 to 3. For example, when the CPU 1 is executing a process, it is indicated that “1” is set in a portion related to the CPU 1 of the register 7151 so that the power supply is not cut off. When the process in the CPU 1 is completed, Setting “0” in the portion related to CPU 1 of the register 7151 indicates that the interruption of the power supply is permitted. Thus, even when a power shutdown request is issued from the power shutdown unit 712, the power shutdown is not permitted until the processing of the CPU related to the request is completed.

  The control signal generator 716 outputs a power control signal 700 according to the settings of the registers 7111, 7121, 7131, 7141, and 7151, and controls the power switches 16_1 to 16_7 of each circuit. Further, when the power is turned on, the selection signal 722 from the activation CPU selection unit 72 is input, and the power switches 16_1 to 16_6 in the power supply areas of the CPUs 1 to 3 designated by the selection signal 722 are controlled to supply power.

  A flow of power control by the power control unit 71 when the external power is turned on will be described.

  FIG. 11 is a flowchart showing the operation flow of the microprocessor 10 when the power is turned on.

  When the power supply voltage is supplied from the outside to the microprocessor 10 (S101), the values of the registers and the like of each circuit are initialized by a power-on reset by the reset control unit 74 described later, and the required node voltage is set to an optimum value. After waiting for this, the power-on reset is canceled (S102). After the power-on reset is released, the information input to the external terminals P1 to P12 is taken into each latch circuit (S103). The control signal generation unit 716 of the power supply control unit 71 supplies power to the power supply area related to the CPU designated by the selection signal 722 from the activation CPU selection unit 72, the built-in ROM, the built-in RAM, and the peripheral circuits 4 to 6 ( S104). As a result, the activated CPU becomes operable. Thereafter, the resources such as the peripheral circuits 4 to 6 and the internal RAM 9 are initialized (S105). Note that the power to the peripheral circuits 4 to 6 may be individually supplied by software after the CPUs 1 to 3 are activated. This completes the process when the power is turned on.

  Next, a control method in the case where the power is shut off and the power is restored after the power-on reset will be described. Here, a case where the power source of the CPU 2 as a slave is turned off and the power source is restored will be described as an example.

  FIG. 12 is an explanatory diagram when the power is shut off after the power-on reset.

  In the figure, when power is turned on, information 720 for instructing activation of CPU1 to CPU3 is input from the switch 100 to the external terminals P1 to P3, and information 730 for instructing the CPU 1 to be the master from the switch 101 is external terminals P4 to P4. Input to P6. Thereby, CPU1 starts as a master CPU, and CPU2 and CPU3 start as a slave CPU. In this state, the CPU 1 as the master accesses the power shut-off unit 712, and requests the power shut-down of the CPU 2 by rewriting the value of the register 7121 of the power shut-off unit 712 from, for example, “000” to “010”. As a result, a power-off instruction for the CPU 2 is issued from the power cut-off unit 712, and the control signal generation unit 716 that has received the instruction stops the power supply of the CPU 2 by the power control signal 700. Thereafter, the value of the register 7121 of the power shutoff unit 712 is reset to “000”.

  FIG. 13 is a flowchart showing a flow of control of the power shutdown.

  When the CPU 1 as the master executes a predetermined program, a power-off process for stopping the power supply of the CPU 2 is started (S201). First, the CPU 1 refers to the power status section 714 to confirm the power supply status of the power area of the CPU 2 (S202). As a result, when it is confirmed that no power is supplied to the CPU 2, the power shut-off process is terminated (S209). On the other hand, when it is confirmed that the power is supplied to the CPU 2, the CPU 1 refers to the power management unit 711 and determines whether or not power control of the power area of the CPU 2 is permitted (S203). Here, when the power control of the power source area of the CPU 2 is not permitted, the power shut-off process is terminated (S209). On the other hand, when the power control of the power area of the CPU 2 is permitted, the CPU 1 refers to the power area exclusive control unit 715 and determines whether or not the power of the CPU 2 can be shut off (S204). For example, when the CPU 2 is processing data and the power shutdown is not permitted, the CPU 1 waits until the power shutdown is permitted. After that, when the CPU 2 is permitted to shut off the power, the CPU 1 acquires the access right to control the power shut-off unit 712, and rewrites the value of the register 7121 of the power shut-off unit 712 from “000” to “010” (S205). As a result, a power shutdown instruction is issued from the power shutdown unit 712, and processing for powering down the CPU 2 is started (S206). First, the supply of the clock signal to the CPU 2 is stopped (S207), and then the power supply to the power source area of the CPU 2 is stopped by the control signal generation unit 716 (S208). Thus, the power shut-off process ends (S209). Details of the method for stopping the supply of the clock signal will be described later.

  FIG. 14 is an explanatory diagram in the case where power is restored after a power-on reset.

  In the figure, as an example, the power supply to the CPU 2 is supplied again after the power supply to the CPU 2 is cut off by the method of FIGS. 12 and 13 described above. In this case, when the CPU 1 serving as the master accesses the power recovery unit 713 and rewrites the value of the register 7131 from “000” to “010”, for example, the power recovery command of the CPU 2 is issued from the power recovery unit 713. . The control signal generation unit 716 that has received the power recovery instruction supplies power to the CPU 2 by the power control signal 700. Thereafter, the value of the register 7131 of the power return unit 713 is reset to “000”.

  FIG. 15 is a flowchart showing the flow of control for power recovery.

  When the CPU 1 as the master executes a predetermined program, a power recovery process for supplying power to the CPU 2 is started (S301). The CPU 1 refers to the power status section 714 and confirms the power supply status of the power area of the CPU 2 (S302). If it can be confirmed that the power has already been supplied to the CPU 2, the power recovery process is terminated (S309). On the other hand, when it can be confirmed that the power is not supplied to the CPU 2, the CPU 1 refers to the power management unit 711 and determines whether or not the power control of the power area of the CPU 2 is permitted (S303). Here, when the power control of the power source area of the CPU 2 is not permitted, the power recovery process is terminated (S309). On the other hand, when the power control of the power supply area of the CPU 2 is permitted, the CPU 1 refers to the power supply area exclusive control unit 715 and determines whether or not the power supply of the CPU 2 is possible (S304). . If the power supply of the CPU 2 is not permitted, the CPU 1 waits until the power supply is permitted. Thereafter, when the power supply of the CPU 2 is permitted, the CPU 1 acquires the access right for controlling the power recovery unit 713 and rewrites the value of the register 7131 of the power recovery unit 713 from “000” to “010” (S305). ). As a result, a power restoration instruction is issued from the power restoration unit 713, and power is supplied to the power source area of the CPU 2 by the control signal generation unit 716 (S306). Thereafter, a clock signal is supplied to the CPU 2 (S307), and the reset of the power source area of the CPU 2 is released (S308). Thus, the power recovery process ends (S309).

  FIG. 16 shows an example of a state transition diagram of a microprocessor having no power shut-off function as a comparative example of the microprocessor 10 according to the present embodiment. As shown in the figure, the microprocessor has an instruction execution state 300, a reset state 301, and a standby state 302. The instruction execution state 300 is a state in which the CPU is executing program processing. The reset state 301 is a state in which the values of the program counter and various registers are reset by the power-on reset or system reset of the CPU. A transition is made to the reset state 301 when a reset signal is generated, and a transition is made from the reset state 301 to the instruction execution state 300 when the reset signal is released. The standby state 302 is a state in which the CPU stops operating due to the supply of a clock signal being stopped in a state where power is supplied to the CPU. A transition is made to the standby state 302 by execution of a sleep instruction or the like, and transition from the standby state 302 to the instruction execution state 300 is caused by the occurrence of an external interrupt or an interrupt by a timer. Further, the transition from the standby state 302 to the reset state 301 is caused by the generation of the reset signal.

  FIG. 17 shows an example of a state transition diagram of the microprocessor 10 according to the present embodiment. As shown in the figure, the microprocessor 10 has a power-off state 303 in addition to the three states shown in FIG. As described above, the power shutdown state 303 is a state in which the power supply is stopped and the operation of the CPU is stopped. As a result, the microprocessor 10 contributes to lower power consumption than a multiprocessor that does not have a power-off function.

(4) Clock control unit 76
The clock control unit 76 controls supply and stop of the clock signal to the CPUs 1 to 3. The clock control unit 76 is, for example, a clock pulse generation circuit (CPG), and controls the supply and stop of the clock signal to each CPU according to the value of the clock control register 743 in the reset control unit 74 described later.

(5) Reset control unit 74, start address control unit 75
The reset control unit 74 generates reset signals for the CPUs 1 to 3 and the peripheral circuits 4 to 6, controls the supply and stop of the clock signal by controlling the clock control unit 76, and the program area executed by the CPUs 1 to 3. Specify the start address. The reset control unit 74 includes a plurality of latch circuits (registers). Specifically, the reset control unit 74 includes a boot target memory designation register 741, a boot address designation register 742, a clock control register 743, and a system reset control register 744. Hereinafter, the operations of the registers 741 to 744 and the reset control unit 74 using them will be described in detail.

  The activation target memory designation register 741 is a register that indicates a reading destination of a program executed by each of the CPUs 1 to 3 after canceling the power-on reset. Information 740 for designating a memory to which a program executed by the CPUs 1 to 3 after canceling the power-on reset is input from the external terminals P7 to P12, and the information 740 is stored in the activation target memory designation register 741 at the time of power-on reset. The

  FIG. 18 is an explanatory diagram of the activation target memory designation register 741. As shown in FIG. 18A, the activation target memory designation register 741 is assigned 2 bits for each of the CPUs 1 to 3. A setting example of the activation target memory designation register 741 is shown in FIGS. Specifically, as shown in FIG. 18B, for example, when the value of the register 741 is “00”, the memory to which the program executed by the CPU 1 after the power-on reset is released is the external memory 14. The In this case, the reset control unit 74 performs address designation 745 to the CPU 1 using a predetermined address in the external memory 14 as a program start address. The predetermined address of the external memory 14 is, for example, the head address of the external memory 14. When the value of the register 741 is “01”, the read destination memory is the built-in ROM 8. In this case, the reset control unit 74 performs address designation 745 to the CPU 1 using a predetermined address of the built-in ROM 8 as a program start address. The predetermined address of the internal ROM 8 is, for example, the head address of the internal ROM 8. Further, when the value of the register 741 is “10”, the read-out memory is the internal RAM 9. In this case, the reset control unit 74 performs address designation 745 to the CPU 1 using a predetermined address of the built-in RAM 9 as a program start address. The predetermined address of the internal RAM 19 is, for example, the head address of the internal RAM 9. The above example is the same for the CPU 2 and CPU 3.

  FIG. 19 is an explanatory diagram when a memory to be read at the time of activation is designated.

  In the figure, the switch 102 installed on the mounting substrate 200 is connected to the external terminals P7 to P12, and the information 740 indicating the memory after the release of the power-on reset is input from the switch 102 to the external terminals P7 to P12. Information 730 for instructing the CPU 1 as a master is input to the external terminals P4 to P6 from the switch 101. In the switch 102 in the figure, for example, the external terminals P7 to P12 are pulled up when the switch is on (ON), and the external terminals P7 to P12 are pulled down when the switch is off (OFF). Thereby, CPU1 starts as a master CPU, and CPU2 and CPU3 start as a slave CPU. In addition, by loading information 740 (“000101”) into the register 741 of the reset control unit 74, the memory to which the program is read after the power-on reset of the CPU 1 is released is the external memory 14, and the reading destinations of the CPU 2 and the CPU 3 are read. These memories are built-in ROMs and are addressed 745 to the CPUs 1 to 3.

  The activation address designation register 742 is a register in which information 746 indicating a program reading method executed by each of the CPUs 1 to 3 after the system reset is set by the master CPU. Depending on the value of the register, it is possible to separately set the reading destination of the program executed after the power-on reset is released and the reading destination of the program executed after the system reset. Specifically, it is used when a CPU activated as a master CPU is switched to a slave CPU after a system reset. For example, a startup program as a master CPU and a startup program as a slave CPU are stored in the memory, and the CPU 1 is made to read the startup program as a master CPU after canceling the power-on reset, and after the system reset, the register 742 Thus, the activation program as the slave CPU is read out. As a result, the CPU 1 activated as the master can be operated as a slave after the system reset.

  FIG. 20 is an explanatory diagram of the activation address designation register 742. As shown in FIG. 20A, the activation address designation register 742 is assigned 2 bits for each of the CPUs 1 to 3, and for example, after the power-on reset is canceled, the value of the activation target memory designation register 741 is set as an initial value. Is set.

  20B to 20D show setting examples of the activation address designation register 742. FIG.

  In the case of FIG. 20B, when a value other than “11”, for example, is set in the activation address designation register 742, that is, when the value (initial value) of the activation target memory designation register 741 is set. The reset control unit 74 does not change the start address of the program executed after the system reset, and addresses the same address as the start address of the program executed after the power-on reset. For example, when the value of the register 742 is “00”, the reset control unit 74 specifies the start address of the external memory 14, and when the value of the register 742 is “01”, specifies the start address of the internal ROM 8. In the case of 10 ″, the head address of the internal RAM 9 is designated as the head address of the program to be executed after the system reset.

  On the other hand, when a value of “11”, for example, is set in the register 742, the reset control unit 74 changes the start address of the program executed after the system reset from the start address of the program executed after canceling the power-on reset. Specifically, the reset control unit 74 specifies the head address of a program to be executed after system reset based on the address information 751 set in the activation address control unit 75 by the master CPU. Here, a method for changing the top address of the program executed after the system reset will be described in detail together with the function of the activation address control unit 75.

  The activation address control unit 75 has a register in which address information 751 for designating the top address of the program area executed by the CPUs 1 to 3 after the system reset is set.

  FIG. 21 is an explanatory diagram of the activation address control unit 75. As shown in FIG. 21A, address information 751 for designating a head address after system reset is set corresponding to each of CPUs 1 to 3. The address information 751 is set by the master CPU. The address information 751 to be set is, for example, the value of the upper bits of the head address specified as the program area executed by the CPUs 1 to 3 after the system reset. For example, when the address specified as the start address of the program executed after the system reset is 32 bits, the upper 20 bits (31 bits to 112 bits) of the address are set as the address information 751.

  The reset control unit 74 generates an address based on the address information 751 set in the activation address control unit 75 when “11” is set in a portion related to a predetermined CPU of the activation address designation register 742. For example, as shown in FIG. 21B, the reset control unit 74 uses the upper 20 bits as the value of the address information 751 set in the activation address control unit 75, and the lower 12 bits (11 bits to 0 bits). Is generated as the start address of the program to be executed after the system reset, and address designation 754 is performed for the target CPU. As a result, it is possible to execute a new program with the address designated by the master CPU as the head address. After the power-on reset is released, “0” is set to all bits as the initial value of the address information 751.

  The clock control register 743 is a register that indicates supply and stop of the clock signal to the CPUs 1 to 3.

  FIG. 22 is an explanatory diagram of the clock control register 743. As shown in FIG. 22A, the clock control register 743 is assigned 1 bit for each of the CPUs 1 to 3. As shown in FIG. 22B, when the value of the register 743 is “0”, the reset control unit 74 controls the clock control unit 76 to stop the supply of the clock signal to the CPU 1. On the other hand, when the value of the register 743 is “1”, the reset control unit 74 controls the clock control unit 76 to supply a clock signal to the CPU 1. The cases of the CPU 2 and the CPU 3 are the same as those of the CPU 1 as shown in (C) and (D) of FIG.

  In the clock control register 743, after the power-on reset is canceled, the value of the register 721 of the activation CPU selection unit 72 is set as an initial value. As a result, the clock signal is supplied to the activated CPU, and the clock signal is not supplied to the CPU that is not activated. After the power-on reset, the value is set by the CPU as the master or the slave CPU to which the access right is given. For example, when the CPU 2 operating as a slave is set in a standby state, the CPU 1 as a master controls the clock control register 743 to stop the supply of the clock signal to the CPU 2. Further, when controlling the start timing of the start sequence of the CPU 2 that is started as a slave by the master CPU 1 after the power-on reset, the CPU 1 controls the clock control register 743 to start the supply of the clock signal of the CPU 2. adjust. Further, in the power-off process or the power-return process of the CPU shown in FIGS. 13 and 15, the CPU that has requested the process controls the clock control register 743, so that the clock signal to the processing target CPU is obtained. Supply and stop. In this case, the control signal generation unit 716 of the power supply control unit 71 may control the control register 743 to supply and stop the clock signal instead of the CPU.

  The system reset control register 744 is a register indicating assertion and negation of a reset signal in system reset.

  FIG. 23 is an explanatory diagram of the system reset control register 744. As shown in FIG. 23A, the system reset control register 744 is assigned 1 bit for each of the CPUs 1 to 3. As shown in FIG. 23B, when the value of the register 744 is “0”, the reset control unit 74 negates a reset signal to the CPU 1. On the other hand, when the value of the register 744 is “1”, the reset control unit 74 asserts a reset signal to the CPU 1. After a predetermined time has elapsed since the reset signal was asserted, the value of the register 744 is reset to “0” again, and the reset signal is negated. The CPU 2 and CPU 3 are the same as the CPU 1 as shown in (C) and (D) of FIG.

  The system reset control register 744 is set to “0” as an initial value after canceling the power-on reset. After the power-on reset, the value is set by the master CPU. For example, when the CPU 2 operating as a slave is reset, the CPU 1 as the master controls the system reset control register 744 to assert a reset signal for the CPU 2.

  Next, as an example of the operation of the microprocessor 10 using the control unit 7, a process of switching the slave CPU to the master CPU will be described.

  FIG. 24 is a flowchart illustrating an example of a process flow when the slave CPU is switched to the master CPU. This figure shows, as an example, processing when the CPU 1 is switched from the CPU 1 to the CPU 2 in a state where the CPU 1 is activated as a master CPU and the CPU 2 is activated as a slave CPU at power-on.

  The processing related to the switching of the master CPU is started when the master CPU 1 executes a program that uses the CPU 2 as the master CPU (S401). First, the CPU 1 accesses the activation address designation register 742 and the activation address control unit 75 in the control unit 7. That is, the CPU 1 changes the value of the activation address designation register 742 in order to validate the value of the activation address control unit 75, and the activation address control unit in order to set the start address of the program executed by the CPU 2 after the system reset. A value is set to 75 (S402). For example, the CPU 1 changes the value of the activation address designation register 742 to “11”, and sets the higher address of the start address of the activation program as the master CPU of the CPU 2 as the address information 751 in the activation address control unit 75.

  Next, the CPU 1 refers to the power supply state unit 714 in the control unit 7 and confirms the power supply state of the power supply area of the CPU 1 (S403). Further, the CPU 1 accesses the power management unit 711 and permits power control of the power area of the CPU 1 (S404). Then, the CPU 1 instructs the CPU 2 to stop the power source area of the CPU 1 (S405). Receiving the instruction, the CPU 2 refers to the power region exclusion control unit 715 to determine whether or not the power of the CPU 1 can be shut off (S406). For example, when the CPU 1 is processing data and the power shutdown is not permitted, the CPU 2 waits until the power shutdown is permitted. After that, when the power cut-off of the CPU 1 is permitted, the CPU 2 acquires the access right to control the power cut-off unit 712, and rewrites the value of the register 7121 of the power cut-off unit 712 from “000” to “100” (S407). ). As a result, a power cut-off instruction is issued from the power cut-off unit 712, and a process for powering down the CPU 1 is started (S408). When the process is started, the supply of the clock signal to the CPU 1 is stopped (S409), and then the power supply of the power source area of the CPU 1 is stopped by the control signal generation unit 716 (S410). Next, the CPU 2 accesses the system reset control register 744 of the control unit 7, sets “1” in the portion corresponding to the CPU 2 of the register, and asserts a reset signal (S411). After the system reset, the reset controller 74 designates the start address of the program to be executed for the CPU 2 based on the setting contents of the activation target memory designation register 741, the activation address designation register 742, and the activation address controller 75 (S412). Here, as described above, since “11” is set in the portion corresponding to the CPU 2 of the activation address designation register 742 in step 402, the reset control unit 74 is generated based on the address information 745 of the activation address control unit 75. The designated address is addressed to the CPU 2. The CPU 2 that has received the address designation 745 is restarted as a master CPU by executing a program with the designated address as the head address (S413). Thereafter, the CPU 2 determines whether or not to activate the CPU 1 as a slave (S414), and when returning, executes the processing shown in FIG. 15 (S415). When the CPU 1 is not restored, the master CPU switching process is completed (S416). As described above, the master CPU is switched.

<< Operation example of system to which microprocessor 10 is applied >>
The operation of the entire system when the microprocessor 10 is applied to a car navigation system having a mobile phone function (Internet access function) will be described. Here, a series of operations by the microprocessor 10 will be described by taking as an example a case where map data is drawn by downloading surrounding map information and traffic information after the car navigation system is activated.

(1) Single activation of CPU 1 After the activation, the car navigation system activates CPU 1 in order to download map information, traffic information, and the like. As described above, since the CPU 1 can specially handle a wireless access function such as W-CDMA, the car navigation system activates the CPU 1 alone. At this time, the CPU 1 is activated as a master. In order for the CPU 1 to start as a master, a start program for starting as the master is required. The storage location of the startup program is as follows.

  FIG. 25 shows an example of a storage location of a master start program (hereinafter also referred to as “master boot code”) and a slave start program (hereinafter also referred to as “slave boot code”) of CPUs 1 to 3. It is explanatory drawing which shows. In this description, it is assumed that the master boot code of the CPU 1 is stored in an area starting from the head address of the external memory 14 as shown in FIG. Further, it is assumed that the slave boot code of CPU 1 and the boot codes of CPU 2 and CPU 3 are also stored in the external memory 14 as shown in FIG.

  The setting of the microprocessor 10 at the time of starting to start the CPU 1 independently is as follows. Data “100” is input from the switch 100 serving as the startup CPU selecting means connected to the external terminals P1 to P3, and data “100” is input from the switch 101 serving as the master CPU selecting means connected to the external terminals P4 to P6. Further, data “000000” is inputted from the switch 102 as the activation target memory selection means connected to the external terminals P7 to P12. Thus, at the time of power-on reset of the microprocessor 10, “100” is stored in the register 721 of the startup CPU selection unit 72, “100” is stored in the register 731 of the master CPU selection unit 73, and “000000” is reset control. By being stored in the activation target memory designation register 741 of the unit 74, the CPU 1 is activated as a master CPU.

(2) Activation of CPU 2 Next, the car navigation system activates CPU 2 by CPU 1 in order to display a simple initial activation screen on the monitor. The CPU 1 accesses the activation address designation register 742 and the activation address control unit 75, and sets values in portions corresponding to the CPU 2 of these registers. Specifically, the CPU 1 sets “00” in the activation address designation register 742, and the activation address control unit 75 stores the start address of the memory area in which the CPU 2 slave boot code shown in FIG. Set the information. Thereafter, when the CPU 1 accesses the power return unit 7131 of the power control unit 71, the CPU 2 is activated as a slave.

(3) Download Start by CPU 1 The car navigation system causes the CPU 1 to download peripheral map (for navigation screen) data and traffic information data, and stores the downloaded data in the built-in RAM 9 or the external memory 14.

(4) Calculation by CPU 2 The car navigation system causes the CPU 2 to execute processing in order to grasp the position of the host vehicle equipped with the car navigation system. Specifically, the CPU 2 calculates the position information of the host vehicle by calculation based on the data downloaded by the CPU 1. Then, the CPU 2 develops map data in the vicinity of the position of the own vehicle in the internal RAM 9 or the external shared RAM so that the CPU 3 which is a map drawing CPU draws the position of the own vehicle and the surrounding map on the monitor. Other map data and the like are stored in the external memory 14. Thereafter, the CPU 2 calculates the position information of the own vehicle and develops the map data in the built-in RAM 9 or the common RAM as necessary while monitoring the own vehicle position and the map data.

(5) Activation of CPU 3 When the car navigation system is downloading data, the CPU 1 monitors the download status. Then, when the map data or the like for drawing the navigation information on the monitor is sufficiently acquired, the CPU 3 is activated from the CPU 1 as the master. First, the CPU 1 accesses the activation address designation register 742 and the activation address control unit 75, and sets values in portions of these registers corresponding to the CPU 3. For example, the CPU 1 sets “00” in the start address designation register 742, and sets the start address information of the memory area where the slave boot code for the CPU 3 shown in FIG. To do. Thereafter, when the CPU 1 accesses the power recovery unit 7131 of the power control unit 71, the power recovery instruction of the CPU 3 is given, and the CPU 3 is activated as a slave.

(6) Start of Drawing of Navigation Screen by CPU 3 In the car navigation system, the newly started CPU 3 causes the monitor 2 to draw the map data developed in the RAM by the CPU 2. At this time, the CPU 3 may control the peripheral circuit 6, which is a dedicated circuit for image processing, to execute processing for rendering the navigation screen.

(7) Switching the master CPU from CPU 1 to CPU 3 The car navigation system stops power supply to the CPU 1 when the CPU 1 completes downloading of necessary data. At this time, since the CPU 1 is activated as a master CPU, it is necessary to use another CPU as a master. Therefore, after the download is completed, the main processing as the car navigation system is drawing of map data and media playback, and thus processing for setting the CPU 3 that mainly performs the processing as a master is executed.

  First, the CPU 1 accesses the activation address designation register 742 and the activation address control unit 75, and sets values in portions of these registers corresponding to the CPU 3. Specifically, the CPU 1 sets “00” in the activation address designation register 742, and the activation address control unit 75 stores the start address of the memory area in which the boot code for the master of the CPU 3 shown in FIG. Set the information. Thereafter, the processing is executed in accordance with the above-described procedure of FIG. 24, whereby the CPU 1 stops supplying power and the CPU 3 becomes the master CPU. Then, the CPU 3 changes the value of the register 731 of the master CPU selection unit 73 from “100” to “001”, and acquires the access right of various registers including the power management unit 711. It should be noted that during the execution of the process for the CPU 3 to switch to the master CPU, the CPU 2 may execute the drawing process for the navigation screen.

(8) Restart of CPU1 During the navigation screen rendering process, the car navigation system causes the CPU 2 to calculate the map data and the position of the host vehicle and monitor the navigation information for rendering so as not to be insufficient. If it is determined that supplementation of map data, traffic information, or the like is necessary due to movement of the host vehicle or changes in surrounding traffic conditions, the CPU 1 is restarted to download the necessary data before data shortage occurs. The process for restarting the CPU 1 is executed by the CPU 3 which is the master CPU.

  First, the CPU 3 accesses the activation address designation register 742 and the activation address control unit 75, and sets values in portions corresponding to the CPU 1 of these registers. Specifically, the CPU 3 sets “00” in the activation address designation register 742, and the activation address control unit 75 stores the start address of the memory area in which the CPU 1 slave boot code shown in FIG. Set the information. Thereafter, when the CPU 3 accesses the power return unit 7131 of the power control unit 71, the CPU 1 is activated as a slave. It should be noted that the CPU 1 slave activation code and CPU 1 clock supply stop are set in advance and the system reset is issued. When the CPU 1 activation request is issued thereafter, the clock control register 743 is issued. It is also possible to restart the system simply by rewriting the setting from clock stop to supply.

(9) Start of download by CPU 1 and calculation by CPU 2 The car navigation system causes CPU 1 to download data of surrounding maps and traffic information while CPU 3 executes map drawing, and stores it in built-in RAM 9 or external memory 14. Store downloaded data. And the positional information of the own vehicle, etc. are calculated based on the data downloaded by CPU2 similarly to said (4).

(10) Power-off of CPU1 The said car navigation system makes CPU1 power-off by CPU3 which is a master after acquisition of insufficient data. The method for shutting off the power is the same as the method shown in FIG.

  As described above, according to the microprocessor 10 according to the present embodiment, the CPU to be activated by the external terminal, the program fuse, or the like and the CPU to be the master can be selected in advance. In addition, since the start address of the program to be executed by the CPU after the power-on reset and the start address of the program to be executed by the CPU after the power-on reset can be separately designated, for example, the CPU activated as a slave at the time of power-on is used as the master. It is possible to operate the CPU activated as a master and operate as a slave. Thus, the data processor to be activated and the master data processor can be freely selected according to the specifications of the system to be developed, which contributes to the effective use of existing hardware resources and software resources. Further, even after the microprocessor 10 is activated, the activated CPU can selectively supply power to the CPU and shut off the power. This contributes to lower power consumption compared to a standby state in which the power is not turned off.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, although the number of CPUs built in the microprocessor 10 is three in the above description, there is no limit to the number of CPUs mounted if the number of bits of various registers is changed according to the number of CPUs. In the above description, the case where the present invention is applied to a microprocessor having a plurality of CPUs having different architectures is shown as an example. However, the present invention can be applied to a microprocessor having a plurality of CPUs having the same architecture.

  Whether or not to activate the CPU is shown as an example of whether or not power is supplied from the power controller 71, but can also be determined depending on whether or not a clock signal is supplied from the clock controller 76. is there. According to this, although it is inferior in terms of reducing power consumption as compared with the case where the power supply is stopped, the power can be restored earlier than when the power is turned on again to restore the CPU.

  As an example, the setting of various registers of the power supply control unit 71 and the reset control unit 74 is performed by the master CPU. However, the present invention is not limited to this, and a slave CPU that receives an instruction from the master CPU may set the register instead. . For example, access to the register of the power shut-off unit 712 for power shut-off is not limited to the master CPU, but may be performed by a slave CPU that has received an instruction from the master CPU.

  The address information 751 stored in the activation address controller 75 shown in FIG. 21 is the value of the upper 20 bits of the head address specified by the CPU, but is not limited to this, and may be the value of all bits of the head address. .

  For the process related to the switching of the master CPU shown in FIG. 24, the case where the process is started by the CPU as the master executing the program is shown as an example, but the present invention is not limited to this, and the slave CPU that is scheduled to become the master May be started by executing the program.

  Although the value of the activation target memory designation register 741 is set to 2 bits for each of the CPUs 1 to 3, the number of bits may be changed according to the storage unit storing the program. Further, the number of bits for each of the CPUs 1 to 3 of the activation address designation register 742 is not limited to 2 bits, and the number of bits is not particularly limited as long as it can be determined whether or not an instruction to change the top address of the program after system reset has been issued.

  Furthermore, in the above description, when the value of the activation address designation register 742 is other than “11”, an example is given in which the start address of the program after the system reset is the same address as the start address of the program after the power-on reset is released. However, the present invention is not limited to this. For example, a value other than “11” in the activation address designation register 742 is associated with another fixed address different from the start address of the program after canceling the power-on reset, and the reset control unit 74 fixes the value according to the value. The address may be addressed.

10 Microprocessor 1-3 CPU
P1 to P12 External terminals 11, 21, 31 CPU core part 4-6, 12, 22, 32 Peripheral circuit 8 Built-in ROM
9 Built-in RAM
14 External memory (flash memory)
DESCRIPTION OF SYMBOLS 15 Common bus 16_1-16_9 Power switch 7 Control part 700 Power supply control signal 71 Power supply control part 711 Power supply management part 712 Power supply cutoff part 713 Power supply return part 714 Power supply state part 715 Power supply area exclusive control part 716 Control signal generation part 7111, 7121, 7131, 7141, 7151 Register 72 Activation CPU selection unit 720 Information indicating CPU to be activated 721 Latch circuit (register)
722, 732 Selection signal 73 Master CPU selection section 730 Information indicating CPU to be master 731 Latch circuit (register)
300 Instruction execution state 301 Reset state 302 Standby state 303 Power-off state 74 Reset control unit 740 Information indicating the memory to which the program is read after canceling the power-on reset 741 Startup target memory specification register 742 Startup address specification register 743 Clock control register 744 System reset control register 745 Address specification 746 Information indicating a program reading method after system reset 75 Start address control section 751 Address information 76 Clock control section

Claims (14)

Multiple data processors;
An activation instructing unit for instructing the data processor to be activated based on the first information input at the time of power-on reset;
A master instructing unit for instructing the data processor as a master based on the second information input at the time of power-on reset;
Based on the third information input at the time of power-on reset or the fourth information set by the data processor started after the power-on reset, the start address of the program area executed by the data processor instructed to start An address instruction unit for instructing information. It further has an external terminal for inputting data,
The semiconductor device according to claim 1, wherein the first information to the third information are data input from the external terminal. A non-volatile storage unit for storing data;
The semiconductor device according to claim 1, wherein the first information to the third information are data input from the storage unit.   In response to the power-on reset, the address instruction unit instructs the start address based on the third information to the data processor instructed to start, in response to the system reset after the power-on reset, 3. The semiconductor device according to claim 2, wherein the start address based on the fourth information is instructed to the data processor instructed to start. The address instruction unit further includes an activation address control unit in which address information designated by the data processor as a master is stored,
The semiconductor device according to claim 4, wherein the fourth information includes information indicating that the start address is designated based on address information stored in the activation address control unit.   The semiconductor device according to claim 5, wherein the fourth information includes information instructing to use a fixed address as the head address.   The semiconductor device according to claim 6, wherein the address instruction unit includes a latch circuit in which the fourth information is stored. A power control unit for managing power supplied to the data processor;
The semiconductor device according to claim 7, wherein the power control unit supplies power to the data processor selected based on an instruction from the start instruction unit.   The semiconductor device according to claim 8, wherein the power control unit stops supply of power to the data processor selected based on an instruction from the activated data processor.   The semiconductor device according to claim 9, wherein the power control unit supplies power to the data processor selected based on an instruction from the activated data processor. A clock signal control unit that controls supply of a clock signal to the data processor instructed to start;
The clock signal control unit controls supply and stop of a clock signal to the data processor selected based on the first information input at the time of power-on reset or an instruction from the data processor as a master. The semiconductor device according to claim 10. The power control unit includes a power management register that stores information indicating a power supply state to the data processor;
The power management register holds a value according to the first information after the power-on reset is released, and the value is updated according to an instruction related to supply or stop of power from the data processor as a master. The semiconductor device according to claim 11.   The semiconductor device according to claim 1, wherein the plurality of data processors include data processors having different architectures.   The semiconductor device according to claim 1, wherein the plurality of data processors include a data processor that executes data processing related to communication and a data processor that executes data processing related to an image.

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