JP2002236527A - Multiprocessor system and processor control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multiprocessor system which can freely set whether some of mounted CPUs should be actuated. SOLUTION: In a CPU operation flag 122 which is secured on a nonvolatile storage means 121, the constitution of processors to be operated is stored. A service processor 120 issues a power supply command to only the power supply controller of a processor to be operated among power supply controllers 111 to 114 for CPUs 101 to 104 according to the CPU operation flag 122 when an OS is started.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-processor system having
The present invention relates to a multiprocessor system in which a CPU to actually start can be selected.

[0002]

2. Description of the Related Art In recent years, the demand for computer processing power has been steadily increasing. Particularly, in servers used which require high processing power for business use such as mission-critical business, as a technique for increasing the speed of computers, CP
It is common to adopt a multiprocessor system equipped with a plurality of U's. Also, from the customer's point of view, a multiprocessor system can easily increase the processing capacity by adding CPUs, memory, and hard disks without replacing the system even if the customer's computer processing capacity increases. Therefore, there is an advantage that one computer can be used for a long time. Such extensibility is generally called scalability.

In a multiprocessor system, all the mounted CPUs are usually operated. Japanese Patent Application Laid-Open No. 8-221375 describes a technique for controlling the CPU configuration of a multiprocessor system. In the known example, the CPU is disconnected by continuously inputting a reset signal to the failed CPU, and only the normally operating processor is selected to restart the information processing system. In Japanese Patent Application Laid-Open No. 11-202988, the operating system monitors the usage of each CPU,
A technique for stopping or suspending a PU is described. As described above, in the related art related to the CPU configuration control of the multiprocessor system, all the mounted CPUs are used.
Is running and the system starts up, and dynamically degenerates the CPU during system operation in the event of a CPU failure or power saving. In a multiprocessor system, performance is generally determined by the number of operating CPUs. For this reason, according to the conventional technology, the number of CPUs to be mounted is changed in order to change the processing performance as a device of the multiprocessor system.

[0004]

As described above, in the conventional multiprocessor system, since all the installed CPUs are operated, a product which covers various processing capabilities and provides a product which can respond to customer's demands in detail is provided. For this purpose, a computer maker needs to prepare a plurality of models having the same number of CPUs but different models. For this reason, in the production process, it is necessary to provide a plurality of production lines according to the number of CPUs to be mounted, or to clearly indicate to the worker the number of CPUs to be mounted in the same production line by a production instruction sheet or the like. Also, it is necessary to perform device management for the number of models regardless of the same device. As described above, providing various product lineups to satisfy various needs of customers by using the conventional technology causes complicated production processes and equipment management.

[0005] Furthermore, if a customer who already has a multiprocessor system increases the processing capacity of the system, the CP
U will be added. Although scalability is an advantage of a multiprocessor system, actually adding a CPU at a customer site is not an easy task. Secure workplaces at customer sites (especially for business use servers, it is unlikely that a dedicated computer room will be provided), the complexity of mounting in the cabinet, and an increase in the number of pins due to the high functionality of the CPU itself CPU like
Given the difficulties in handling, it is technically difficult to quickly add a CPU. As a result, a long-term stoppage of a customer job and an increase in cost due to a long-term dispatch of maintenance personnel are caused.

The present invention has been made in view of the above circumstances, and it is possible to mount a large number of CPUs or a maximum number of mountable CPUs in advance and operate only some of the CPUs among the mounted CPUs. It is an object of the present invention to provide a multiprocessor system that can perform the processing.

[0007]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a multiprocessor system having a plurality of processors, which sets information relating to the start or stop of each processor, and starts and stops each set processor. When you save the setting information and start the system,
A configuration for controlling the power supply of each processor based on the start / stop setting information is adopted.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of the present invention will be described in detail with reference to FIGS.

FIG. 1 shows a configuration of a multiprocessor system according to the first embodiment. 101 to 104 store the CPU of this system, 105 stores the basic input / output system (BIOS)
ROM, 106 is a main memory, 108 is a system bus, 107 is a bus bridge connecting the system bus 108 and a local bus 125 described later. 111 to 114 are devices for supplying power to the CPUs 101 to 104, and 115 is a power supply line. 120 is CP
A service processor 121 for performing reset control and power supply control of U is a non-volatile storage means in which data is not erased even when the power is turned off. A non-volatile memory such as a FLASH ROM or a hard disk device is conceivable. Further, the CP actually operated in the CPUs 101 to 104 is stored in the nonvolatile storage unit 121.
The CPU operation flag 122 for recording the setting information of U is stored. Reference numeral 123 denotes a register for collecting information of a CPU actually mounted on the multiprocessor system 100. 1
Reference numeral 24 denotes a terminal connected to the service processor 120. 1
Reference numeral 25 denotes a local bus for connecting the service processor, the shared memory, and the CPU mounting register.

FIG. 2 shows a circuit relating to the CPU start register 107 and the CPU mounting register 123 in detail. CPU
Slots 201 to 204 are insertion holes for mounting a CPU in the multiprocessor system 100, and 1-bit information indicating whether or not the CPU is mounted is transmitted from the slot to the CPU mounting register 123. Fig. 3 shows the flow of the user information setting process, and Fig. 4 shows the operating CP.
Details of the U configuration flag, FIG. 5 is a flowchart of a system startup process.

The present invention is characterized in that the system is started with a CPU configuration according to the user's setting among the installed CPUs. First, the process of registering the CPU to be operated by the user is shown in FIG. This will be described with reference to a flowchart. The user selects the CPU to be operated from the installed CPUs via the terminal 124. The service processor 120 has the CPU configuration currently implemented in the multiprocessor system 100.
It is collected from the CPU mounting register 123 (step 301), and it is checked whether the CPU configuration selected by the user is valid (step 302). This is a step for confirming, for example, whether the user has erroneously selected a CPU that is not mounted, or has selected a configuration that does not hinder the operation of the CPU due to electrical characteristics.
If the user sets a normal configuration, the service processor 120 stores the CPU operation configuration information specified by the user in the CPU operation flag 122 provided on the non-volatile storage means 121 (step 303). Is output to the terminal 124 to indicate that has been completed normally (step 304).
Here, as shown in FIG. 4, the CPU operation flag 122 is obtained by allocating 1-bit operation or non-operation information for each CPU similarly to the CPU mounting flag. “1” indicates operation, and “0” indicates non-operation. In the example of FIG. 4, the CPUs 101 to 103 operate, and the CPU 104
Represents a setting for non-operation. If the user selects an incorrect configuration, the service processor 120 outputs to the terminal 124 a display indicating that the request from the user has not been accepted and has ended abnormally (step 305). By the above processing, C to be operated for the multiprocessor system 100
Setting the PU configuration is complete. Since the CPU operation flag 122 is stored in the non-volatile storage unit 121, the information of the CPU operation flag 122 is not deleted even if the power of the multiprocessor system 100 is turned off. In other words, once the user sets the CPU information to be operated at the time of introduction, there is no need to perform the setting work unless the CPU operation configuration is changed thereafter.

Next, a system startup process performed based on user settings will be described with reference to the flowchart of FIG. The service processor 120 collects the CPU operation flag 122 stored in the non-volatile storage means 121 (step 501), and turns on the power only to the power control device of the CPU to be operated among the power control devices 111 to 114 according to the collected flag. An instruction is issued (step 502). For example, based on FIG.
0 issues a power-on instruction to the power control devices 111, 112 and 113. By this step, the power is turned on only for the CPU set by the user to operate. Next, the service processor 120 releases the system reset (step 503), and the powered-on CPU is activated. As described above, according to the present invention, it is possible to activate only the CPU set by the user among the plurality of mounted CPUs.

Thus, a computer maker can prepare a variety of product lineups only by changing the CPUs that produce and operate models in which a large number of CPUs are mounted in advance. Therefore, the difference in the number of CPUs mounted during production can be reduced, and the production process and equipment management can be simplified.

Next, a second embodiment of the present invention will be described in detail with reference to FIGS. FIG. 6 shows a second embodiment of the present invention. 6, the same components as those in the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and the description thereof will be omitted. As a new code, 60
Reference numeral 5 denotes a device for supplying power to the CPUs 101 to 104. Figure
In 1, each CPU has its own power control device, but in FIG. 631-634 is C
This is a CPU reset control signal line connected to the reset signal inputs of the PUs 101 to 104. FIG. 7 is a flowchart of the startup processing of the multiprocessor system 600.

The process of registering the CPU to be operated by the user is the same as in FIG. 3, and will not be described here. A system startup process performed based on user settings will be described with reference to the flowchart in FIG. The service processor 120 collects the CPU operation flag 122 stored in the nonvolatile storage means 121 (Step 701). Next, the service processor 120 issues a power-on instruction to the power control device 605 (step 70).
2), power is turned on to all mounted CPUs. Next, according to the user setting of the CPU operation flag 122, the service processor 120 controls only the CPU to be operated among the CPUs 101 to 104.
Release U reset (Step 703) and set CP for user
Only U starts. In the present embodiment, power is supplied to CPUs that do not operate, but there is no need to prepare a power supply control device for each CPU, and the number of components can be reduced. by the way,
The CPU reset signal is continuously input to the CPU that does not operate, but processing for ensuring the stop of the CPU may be added. For example, some CPUs have a disable signal input,
By inputting a disable signal to a CPU that does not operate, the CPU becomes invalid and the stop can be ensured.

[0016]

As described above, in the multiprocessor system of the present invention, the CPU to be activated among the mounted CPUs can be freely set.

Further, in the multiprocessor system of the present invention, in the CPU addition work, the CPU addition work can be completed by merely changing the number of operating CPUs in the system without actually performing the CPU mounting work. It is possible to avoid time-consuming job stoppages and dispatch of specialized maintenance personnel, and reduce costs.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a CPU mounting register 123.

FIG. 3 is a flowchart illustrating a procedure for setting a CPU operation configuration in the multiprocessor system 100.

FIG. 4 is a schematic diagram showing details of a CPU operation flag 122.

FIG. 5 is a service processor 1 according to the first embodiment.
20 is a flowchart showing a processing procedure in which the CPU 20 starts the CPU.

FIG. 6 is a block diagram illustrating a configuration of a second embodiment of the present invention.

FIG. 7 is a service processor 1 according to the second embodiment.
20 is a flowchart showing a processing procedure in which the CPU 20 starts the CPU.

[Explanation of symbols]

100: Multiprocessor system, 101-104: CPU, 10
5: BIOS ROM, 106: main memory, 107: bus bridge, 108: system bus, 111 to 114: power supply control device, 115: power supply line, 120: service processor, 12
1: Non-volatile storage means, 122: CPU operation flag, 124: CPU
Implementation register, 125: Local bus, 201 to 204: CPU Slo
t, 400: CPU operation flag, 600: multiprocessor system, 605: power supply control device, 631 to 634: CPU reset control signal line

Claims (4)

[Claims] 1. A multiprocessor system having a plurality of processors, comprising: a plurality of power supply control means for controlling power supply to each of the processors; and a setting means for setting information on activation or deactivation of each of the processors. ,
Storage means for storing start / stop setting information relating to each processor set by the setting means; and when starting up the system, issuing a command to the power supply control means based on the start / stop setting information. A multiprocessor system comprising: a control unit that controls power supply of the processor. 2. A multiprocessor electronic computer having a plurality of processors, comprising: setting means for setting start or stop of each processor; and start / stop setting information of each processor set by the setting means. A multiprocessor system comprising: storage means for storing; and means for controlling reset for each processor based on the start / stop setting information when the system is started. 3. A processor control method for controlling a plurality of processors, the method comprising referring to a mounting state of the plurality of processors and determining whether a user setting configuration regarding the mounting of the processors is valid. As a result, if the user setting configuration is valid, the user setting configuration is stored as a processor operation flag. 4. When activating the plurality of processors, the stored processor operation flag is read, a processor configuration to be activated is acquired based on the read result, and the processor to be activated is turned on to activate. 4. The method according to claim 3, wherein