JP2008090760A - Method and device for supplying power to processor of multiprocessor system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method and device for supplying power to a processor of a multiprocessor system. <P>SOLUTION: An embodiment comprises a method for monitoring a parameter related to a first voltage potential connected to a processor. When a monitored parameter or state shows that a first voltage is defective or has a trouble, the method generally comprises separating the voltage from the processor to invalidate or reset the processor, and connecting a second voltage potential to the processor. The method enables a computer system to continuously operate with the processor being invalidated. Another embodiment comprises an error detection circuit for detecting an error related to a first voltage regulator, an invalidation circuit for invalidating the first voltage regulator in response to the error, a processor separation circuit, and a voltage switching circuit for supplying voltage to the processor from a second voltage regulator. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

The present invention generally relates to computer systems having a plurality of microprocessors. More particularly, the present invention relates to a method and apparatus for supplying power to a processor in a multiprocessor system.

Our society rests heavily on computer systems for many of our daily activities. Computer systems that use processors control equipment in our homes, in our offices, in our production facilities, in our automobiles, and even in space shuttles and geostationary satellites. Computers and processors can be found in devices such as desktop and laptop computers, mainframe computer systems, and in portable devices such as mobile phones and palm-held computers.

In addition to these existing uses, people are constantly finding new uses for computer systems. Many applications demand improved processor performance and place a burden on modern computer systems. Examples of processor performance improvements that computer designers are constantly striving to improve include increased processor speed and faster data processing capabilities. Examples of applications that require improved processor performance are image and speech recognition, climate or weather modeling, fluid turbulence modeling, human genome mapping, oil reservoir modeling, and ocean circulation modeling. All of these applications require a huge amount of computational power for a large number of mathematical calculations.

To meet these application requirements, computer system designers have significantly changed the architecture of processors, primarily microprocessors. For example, computer systems of the 1980s and early 1990s generally had a single central processing unit that handled data in a linear or sequential manner. Unfortunately, such sequential architectures only provide limited computational power due to the physical limitations of the microprocessor. Thus, today's computers typically use multiple processors that compute simultaneously on various processor architectures, such as a parallel architecture.

As mentioned above, many computer systems today include multiple processors. Also, as the number of processors in a computer increases, designers creating these multiprocessor systems tend to use various techniques and design methods to derive additional computing power from these computer systems. Such techniques and design methods include pipeline processing, vector processing, and the use of superscaler architectures. Computer systems using these techniques and design methods generally follow Moore's law, where the number of transistors and resistors on a chip doubles every 18 months. Today, even state-of-the-art computer system chips containing millions of transistors or billions of transistors are not uncommon.

Unfortunately, the more transistors and other integrated circuit elements used by computer systems and computer chips, the more likely they will fail than systems and devices with fewer elements. To address these increasing failure rates, computer manufacturers use a variety of design techniques that tend to improve the continuous uptime and reliability of these systems. For example, one technique for improving continuous uptime currently used in computer systems with multiple processors includes disabling processors with internal failures. When detecting that the processor has an internal fault, the processor is held in a reset state. Holding the failed processor in a reset state effectively tri-states the output of the failed processor, allowing other processors attached to the common bus to continue to operate.

However, there are significant problems with attempts to allow computer systems with multiple processors to operate using this technology. The processor may fail due to problems within the processor itself, or the processor may fail due to problems with the voltage regulator that provides power to the processor. If the problem is internal to the processor, the technique of holding the processor in the reset state described above can disable the processor and allow the multiprocessor system to continue to operate. However, if the processor fails due to problems with the voltage regulator that powers the processor, a simple attempt to keep the processor in reset can allow the system to continue to operate without the processor. Can not.

Because the processor requires power to accurately tri-state the processor inputs and outputs, the technique of holding the processor in reset works well when the problem is related to a voltage regulator that powers the processor Can not. Due to the fact that other processors are connected to the same data, control, and address bus, the inputs and outputs of the failed processor need to be tri-stated. If not properly tri-stated, the input and output of the failed processor will cause the bus signal line to fail and prevent other processors from functioning properly.

Many multiprocessor system architectures require a core voltage for each processor that is independent of core voltages for other processors during normal operation. As a result, if the voltage supply or voltage regulator for the processor in question fails, the processor cannot be properly tri-stated due to a voltage shortage. In many cases, the core power supply plane is isolated from other power supply layers, and other power supplies of the core voltage are not available. Eventually, the failure of a single voltage regulator in a computer with multiple processors will prevent the computer from operating. Accordingly, there is a need for a method and apparatus that allows multiple processor computers to operate even if one of the voltage regulators fails.

The problems identified above are primarily addressed by methods and apparatus for providing voltage to a processor when a voltage source, such as a voltage regulator, is defective. One embodiment includes a method of providing power to a processor of a computer system having a plurality of processors. In general, the method includes monitoring a parameter associated with a first voltage potential coupled to the processor. If the monitored parameter or condition indicates that the first voltage is bad or faulty, the method isolates the voltage from the processor and disables or resets the processor, A second voltage potential is coupled to the processor. This method may also allow the computer system to continue to operate with the processor disabled. In various embodiments, first voltage potential isolation, processor disablement, and second voltage potential coupling may be achieved by using devices such as switches, transistors, and relay contacts.

Another embodiment includes an apparatus for supplying a voltage to a processor of a computer system having a plurality of processors. The apparatus includes an error detection circuit for detecting an error associated with the first voltage regulator, a disabling circuit for disabling the first voltage regulator in response to the error, a processor isolation circuit, and a second to the processor. A voltage switching circuit for supplying a voltage from the voltage regulator may be included. All elements of this device may reside in a single device called a service processor. The device can utilize transistors, switches, and relay contacts to isolate the voltage regulator, isolate the processor, and switch the processor to a second voltage regulator.

Further embodiments include a multi-processor computer system that includes two or more processors, two or more voltage regulators that supply voltages to the processors, a voltage error detection module that detects problems with the voltage regulator module, and a problematic voltage. A voltage isolation module that isolates the regulation module and a voltage switching module that couples at least one of the remaining voltage regulation modules to any processor affected by the problematic voltage regulation module. In other embodiments, the computer system may also include a processor disable module that disables one or more of the processors affected by the problematic voltage regulation module.

Other objects and advantages of the present invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings. In the accompanying drawings, like reference numbers may indicate like elements.

The following is a detailed description of example embodiments of the invention illustrated in the accompanying drawings. The example embodiments are thus shown in detail to clearly inform the invention. However, the overall details provided are not intended to limit the anticipated variations of the embodiments, but on the contrary, all modifications, equivalents, and so on that are within the spirit and scope of the invention as defined in the appended claims. It is intended to include alternatives. The detailed description below is intended to make such embodiments obvious to those skilled in the art.

In general, a method, apparatus, and system for providing power to a processor of a multiprocessor computer system is disclosed. Discusses a new technique for switching power between processors after detecting a voltage error. Embodiments include a method of monitoring a computer system having a plurality of processors that are powered by a plurality of voltage sources and switching power between the processors when a voltage error is detected. In these embodiments, the device software and / or hardware can detect that the voltage for one or more processors is out of tolerance, and in response switch the voltage from the other power source, and Affected processors can be isolated.

In some embodiments, the voltage is switched between two processors that use two independent voltage regulators. In other embodiments, the voltage can be switched between any number of processors, such as 3, 4, 8, or more. Similarly, the voltage for the processor can be derived from a number of different power sources. In many embodiments, the voltage can be switched using a semiconductor device, such as a field effect transistor. In other embodiments, the voltage to the processor can be switched using a relay or other switching device.

The method of detecting and responding to various voltage problems is different in various embodiments. In some embodiments, the voltage control unit can simply detect the loss of voltage from the voltage regulator. In other embodiments, the voltage control unit can monitor more subtle voltage error conditions such that the voltage does not reach a predetermined threshold. In a further embodiment, the service processor can monitor the voltage error by monitoring a single status bit from the voltage regulator or from a processor powered by the regulator. In response to various errors, the voltage control unit of some embodiments provides a processor affected by the voltage error to a voltage source that is not affected and keeps the processor in a reset state. Can respond. In other embodiments, the voltage control unit can be responsive in different ways, for example, to keep the status input to the processor at a high level that allows the processor to float its inputs and outputs.

In some of the detailed discussion below, a number of embodiments will be described, including new techniques for supplying power to a microprocessor in a computer system having a plurality of microprocessors. It will be appreciated that in a processor-based computer system, for example, a processor implemented in a multi-board computer, and even a processor implemented in a mainframe system can be implemented using many different types of processors. . Although embodiments have been described as having a processor coupled to a single bus, such as a data bus or a memory access bus, various embodiments can be coupled to multiple buses simultaneously. Further, although the embodiments describe switching voltages between processors using transistors and relays, those skilled in the art will appreciate that the techniques disclosed herein can utilize almost infinite variations of switching devices. Will recognize. All configurations and methods embodying the invention are interchangeable with other embodiments when used to perform substantially equivalent functions based on similar constraints.

Reference is now made to FIG. 1 showing a multiprocessor computer system 100 having two processors, two voltage regulator modules, and a device for switching between the two regulator modules. More specifically, the computer system 100 shown in FIG. 1 includes a first microprocessor 118 and a second microprocessor 120 coupled in parallel to the bus controller 154 via a single bus segment 128. Have In various embodiments, the bus segment 128 can couple the processors 118 and 120 to buses of various widths. For example, in some systems, bus segment 128 may include an 8-bit bus segment. In other embodiments, the bus segment 128 may include a bus with 16, 32, or a larger number of bits.

Coupled to the bus controller 154 is an AGP (accelerated graphics port) bus 158, a PCI (peripheral component interconnect) bus 150, and a bank of random access memory (RAM) 124. In this embodiment, microprocessor 118 and microprocessor 120 share a bank of RAM 124 and include a shared memory computer system, although other embodiments may have microprocessors arranged in other ways. . For example, instead of microprocessor 118 and microprocessor 120 sharing one bank of memory, in other embodiments, microprocessors 118 and 120 having separate dedicated memory banks, as in a distributed memory computer system. Can be placed.

Microprocessors 118 and 120 can operate in communication and can display information to a user of computer system 100 via a cathode ray tube monitor using AGP bus 158 and AGP video card 160. In other embodiments, the display device may be a liquid crystal display screen or a thin film transistor flat panel monitor. Further, in various embodiments, information can be displayed to the user using other types of display adapters different from the AGP video card 160, such as legacy industry standard architecture (ISA) cards. In a further embodiment, the microprocessors 118 and 120 can be embedded in computing equipment that has no display at all.

Computer system 100 may have a basic input / output system (BIOS) program stored in BIOS module 190. Included in the BIOS module 190 is a Power On Self Test code or program that causes the microprocessors 118 and 120 to perform a number of predetermined tests on the system hardware after the computer system 100 is powered on. It can be done. For example, the POST program can check the computer system and check various ports and USB ports for input / output devices such as keyboards and mice.

As shown in FIG. 1, the computer system 100 can include a microprocessor 118 coupled to a cache memory 116. Similarly, computer system 100 can have a microprocessor 120 coupled to cache memory 122. Such a cache memory device may facilitate improving the operating performance of individual processors in various embodiments. However, in some embodiments, one or more processors similar to microprocessors 118 and 120 may have multiple cache memory devices coupled to individual microprocessors and coupled to multiple microprocessors. It may even have one or more microprocessors without a cache memory device.

As shown in FIG. 1, the computer system 100 includes a voltage regulation module (VRM) 108 that supplies power to the microprocessor 118 and a power supply to the microprocessor 120 via the switching module 114. Another VRM 112 can be provided. During normal operation, the switching module 114 can isolate the voltage from the VRM 108 and the VRM 112 so that the VRM 108 supplies voltage to the microprocessor 118 while the VRM 112 supplies voltage to the microprocessor 120. If VRM 108 or VRM 112 fails, voltage regulator control unit 102 can detect such a failure from each of status input lines 104 and 106 and activate switching module 114 via output switching control line 110. Can do. By operating the switching module 114, it is possible to couple the voltage from the non-failed VRM to the processor supplied from the failed VRM in the normal state. By coupling the backup voltage in this manner, the affected processor can be placed in a bypass mode, the affected processor stops normal operation, and the bus controller Other processors and devices coupled to 154 are allowed to operate normally.

For example, assume that the computer system 100 is operating in normal mode with the microprocessor 118 receiving voltage from the VRM 108. Similarly, the microprocessor 120 is receiving voltage from the VRM 112. By monitoring the state of each of the two state input lines 104 and 106, the VRM control unit 102 can detect that the VRM 108 and VRM 112 are operating normally. Upon detecting that VRM 108 and VRM 112 are operating normally, VRM control unit 102 can cause switching module 114 to separate the outputs of VRM 108 and VRM 112 so that each VRM output is isolated from the other outputs. It is made like. In this normal mode of operation, the switching module 114 can couple the voltage from the VRM 108 only to the microprocessor 118 and can couple the voltage from the VRM 112 only to the microprocessor 120. However, assume that the VRM 108 fails and stops supplying the output voltage. With the lack of operating voltage supplied by the VRM 108, the microprocessor 118 stops operating. Unfortunately, with the complete lack of operating voltage applied to the microprocessor 118, the output signal line of the bus segment 128 can be held low and prevent normal operation of the microprocessor 120 having the bus controller 154. To ameliorate this problem, the microprocessor 118 can be placed in a bypass mode so that sufficient voltage is applied to the microprocessor 118. Such a voltage may be provided from other VRM modules such as VRM 112 that are still operating normally.

The VRM control unit 102 can detect that the VRM 108 has failed by sensing the current lack of voltage on the status input line 104. Thus, the VRM control unit 102 can activate the switching control line 110 and couple the output of the VRM 112 to the microprocessor 118 via the switching module 114. By providing sufficient voltage from the VRM 112 to the microprocessor 118, the microprocessor 118 can be reset and held in a diverted state, so that the microprocessor 120 can operate normally with the bus controller 154. Can interact. Obviously, the reverse situation can also occur. That is, the VRM 112 can fail and affect the microprocessor 120. At that time, the VRM control unit 102 can activate the switching module 114 to couple the voltage from the VRM 108 to the microprocessor 120, so that the microprocessor 120 can be bypassed and the microprocessor 118 can continue to operate. It can be.

To better explain how voltage and power can be supplied to a processor in a multiprocessor system, here we can see how voltage errors and how voltage can be detected in various embodiments. A more detailed discussion of how errors can be isolated and how the processor of the system can be disabled continues. FIG. 2 shows an apparatus 200 that controls two core voltages: core voltage 230 and core voltage 260. In some embodiments, the device 200 can be fully implemented in a semiconductor substrate and include a single integrated circuit. In other embodiments, one or more components of the device 200 can exist as separate electronic devices coupled with metal lines or other conductive materials, such as electrical traces on one or more printed circuit boards. .

As shown in FIG. 2, the core voltage 230 can provide an operating voltage and current to the microprocessor 240. Similarly, the core voltage 260 can provide an operating voltage and current to the microprocessor 270. During normal operation, the VRM 220 can output or supply the core voltage 230 while the VRM 250 can supply the core voltage 260. Microprocessors 240 and 270 can be two processors of a multiprocessor computer system configured with a variety of different computer architectures, such as a shared memory architecture. In addition, the microprocessors 240 and 270 can utilize various data processing techniques such as pipelining, time sharing, multithreading, interleaving, and overlapping.

The voltage and microprocessor control unit 210 can monitor a number of parameters related to the voltages provided by the microprocessor 240, the microprocessor 270, and the VRM 220 and VRM 250. For example, the control unit 210 can monitor the voltages supplied by the VRM 220 and VRM 250 to ensure that both voltages are within the normal voltage range. In some embodiments, the control unit 210 can monitor such a voltage to ensure that it is not below some minimum operating threshold. In other embodiments, the control unit 210 can simply monitor status bits generated by internal diagnostic circuitry within the VRM 220 and VRM 250. In other words, each VRM can have its own diagnostic circuitry to monitor voltage parameters such as voltage level, voltage drop, voltage drop duration, voltage noise, ripple, and other voltage quality measures. . Such monitoring of voltage parameters may be performed by the VRM or control unit 210, depending on the embodiment.

Upon detecting a voltage error associated with VRM 220 or VRM 250, control unit 210 may respond in a variety of different ways, depending on the embodiment. In some embodiments, the control unit 210 first disables the processor affected by the faulty or faulty VRM, disables the faulty VRM, and voltage from the operating VRM. Can be coupled to both the microprocessor 240 and the microprocessor 270 to keep the processor coupled to the faulty VRM out of sight normally. This holding the processor invisible may allow one or more remaining processors of the computer system to continue to operate. In some embodiments, each individual VRM module can have sufficient current generation capability to supply both the microprocessor 240 and the microprocessor 270 so that the affected microprocessor can be easily It can be reset by the control unit 210 and the affected microprocessor can continue to operate.

In other embodiments, the control unit 210 may detect and respond to voltage errors in different ways. For example, the control unit 210 can monitor the status bits from the microprocessors 240 and 270, and the disappearance of either bit would correspond to an abnormal voltage being supplied to the processor. In other words, the microprocessor can perform voltage monitoring. If either status bit disappears, the control unit 210 invalidates the faulty VRM, couples the other VRM to the affected processor, and keeps the affected processor in reset. In order to allow any other system processor or device connected to the same I / O line to continue functioning, the affected processor's I / O line is effectively tri-stated. To do. In a further embodiment, the control unit 210 can monitor the core voltages 230 and 260 directly and detect a voltage error at the control unit 210.

To provide a clearer example of how power can be redistributed to the processors of a multiprocessor computer system, go to FIG. FIG. 3 shows a computer system 300 having a service processor 315 that controls the voltages from two voltage regulator modules VRM 350 and VRM 365 that power two microprocessors 375 and 380. The microprocessor 375 may be dedicated to the RAM 385, and the microprocessor 380 may be dedicated to the RAM 390. Microprocessors 375 and 380 can be coupled to a single system bus 395 and form what may be a distributed memory multiprocessor computer system 300.

During normal operation, the VRM 350 can provide a regulated and filtered core voltage 355 to the microprocessor 375. Similarly, the VRM 365 can supply the core voltage 370 to the microprocessor 380. Both core voltage 355 and core voltage 370 can be distributed to microprocessors 375 and 380 through a copper plane. With both VRM 350 and VRM 365 functioning properly, both microprocessors 375 and 380 can utilize core voltages 355 and 370, respectively, and communicate and operate while transmitting and receiving data to and from RAMs 385 and 390. To do. In addition, each microprocessor can communicate data with other devices in computer system 300 via system bus 395. Also, during normal operation, service processor 315 can monitor the status of VRM 350 and VRM 365 via independent status lines 325 and 335, respectively.

If one of the voltage regulator modules fails and causes an error, the service processor 315 can detect the error from the state line 325 or the state line 335 and reset the affected microprocessor to detect the failure. It can be accommodated by connecting core voltages 355 and 375 by disabling certain voltage regulators, activating output connection line 345 and closing switch 360. In other words, whenever the voltage regulator has an error, the service processor 315 can detect and respond by disabling the regulator and supplying voltage to the affected processor from the active regulator. As a result, the processor may be bypassed to allow the computer system 300 to continue to operate. If processor 315 is powered from a reserve voltage source such as reserve voltage 305, service processor 315 can continue to operate even if VRM 350 or VRM 365 disappears.

For example, assume that computer system 300 is operating normally with both VRM 350 and VRM 365 supplying power to microprocessor 375 and microprocessor 380, respectively. The service processor 315 can deactivate the output connection line 345 and open the switch 360. If VRM 365 experiences an internal failure, status line 335 may change to a logical zero. Service processor 315 can detect this change in status line 335 and can respond by disabling VRM 365 by changing control output 340 from logical 1 to logical 0, and finally, Disable VRM365. Further, the service processor 315 can set the microprocessor 380 to a reset state by changing the control output 320 from logical 0 to logical 1. In addition, the service processor 315 can supply power from the VRM 350 to the microprocessor 380 by activating the output connection line 345 and closing the switch 360. By closing the switch 360, the VRM 350 can be provided with sufficient power from the core voltage 355 to the core voltage 370. As a result, the microprocessor 380 can normally tri-state the input / output lines. In this way, by having the service processor 315 with the control output 320 held at a logical one, tri-state the microprocessor 380 I / O lines can isolate the microprocessor 380 from the system bus 395. The microprocessor 375 can continue to operate and communicate with other devices coupled to the system bus 395.

Similar to disabling VRM 365 and providing power from VRM 350 to microprocessor 380, service processor 315 uses control output 330, control output 310, and output connection line 345 to disable VRM 350 and VRM 365. Can supply power to the microprocessor 375. Further, the service processor 315 may vary by changing the control output from a low level to a high level or from a high level to a low level, depending on the configuration of the VRM 350, VRM 365, microprocessor 375, and microprocessor 380. Embodiments can achieve these functions. In other words, depending on the configuration of the voltage regulator, the microprocessor, and the switching device, the control output can be activated by lining up from high to low or from low to high.

In various embodiments, the exact procedure performed by service processor 315 in bypassing the voltage regulator and disabling the microprocessor can be varied, but can accomplish the same task. For example, in some embodiments, the service processor can first disable the defective VRM, configure the microprocessor, and then connect the power layer. In yet another embodiment, the service processor can first set the microprocessor to a reset state, then disable the defective VRM, and finally close the voltage switch. The exact order in which the various output control lines are controlled is not critical and may vary depending on the components of the computer system 300.

Referring now to FIG. 4, a multiprocessor computer system 400 is shown. As shown in FIG. 4, the computer system 400 can have different numbers of processors powered by different numbers of voltage regulators. More specifically, the computer system 400 can include two microprocessors, a microprocessor 435 and a microprocessor 440 that are powered by a first VRM 430. Similarly, the second VRM 455 can supply power to the microprocessor 485 and the microprocessor 490. Note how the computer system 400 of FIG. 4 differs from the computer system 100 of FIG. 1, the computer system 300 of FIG. 3, and the apparatus 200 of FIG. While the former system and apparatus had only two microprocessors and two voltage regulator modules, the computer system 400 provides power to four microprocessors, microprocessors 435, 440, 485, and 490 2. Two VRMs, 430 and 455 are used. As described above, different embodiments may include different numbers of voltage regulators and microprocessors, depending on application requirements, processor power demand, regulator output ratings, and the like.

In computer system 400, during normal operation, VRM 430 can provide power to microprocessor 435 and microprocessor 440. Similarly, VRM 455 can provide normal operating power to microprocessors 485 and 490. Service processor 410 can monitor the status of VRM 430 on status line 420 and monitor the status of VRM 455 on status line 465. For illustrative purposes, if a voltage error occurs in the VRM 455, the service processor 410 can detect the error via the status line 465 and output control outputs 470 and 480, respectively, so that the microprocessor 485 and the microprocessor 490 You can respond by disabling. Service processor 410 can then disable VRM 455 by changing the state of control output 460 and can couple power to microprocessors 485 and 490 by energizing relay 445. By energizing relay 445, relay contact 450 can be closed and the voltage and power from VRM 430 can be coupled to microprocessors 485 and 490.

In other embodiments, the service processor 410 may not need to disable or bypass all microprocessors associated with the voltage regulator. For example, assume that VRM 430 fails. Service processor 410 can respond by disabling VRM 430 by activating control output 425 and energizing relay 445 to close relay contact 450. Further assume that VRM 455 has a power rating that is large enough to power three microprocessors, but not enough to power four microprocessors. Service processor 410 may not need to disable both microprocessor 435 and microprocessor 440. Alternatively, the service processor 410 can attempt to maximize the number of processors operating in the computer system 400 and either disable the microprocessor 440 using the control output 405 or use the control output 415. Only the microprocessor 435 can be disabled.

FIG. 5 shows another technique for how the service processor can control the voltage from several voltage regulators for several processors to consider a more flexible and detailed configuration. Refer to Computer system 500 normally has four processors, processors 586, 588, 590, and 592 that are powered by each of four voltage regulator modules 550, 556, 560, and 564. During normal operation, the service processor 502 can activate the control outputs 508, 514, 528, and 532 to close each of the switches 566, 570, 572, and 574, and individually voltage the VRM. To the next processor. Service processor 502 can monitor VRMs 550, 556, 560, and 564 via VRM status lines 504, 518, 524, and 536, respectively.

The configuration of the computer system 500 shown in FIG. 5 can provide additional flexibility in switching operations if one or more VRMs fail. For example, assume that both VRM 550 and VRM 560 fail. Service processor 502 can detect these faults via status lines 504 and 524, and can activate control output lines 506 and 526 to disable VRM and change control outputs 508 and 528. Responding by opening switches 566 and 572 to isolate the output of the VRM from the interconnect wiring at the outputs of the microprocessor 586, microprocessor 590, and all VRMs. Service processor 502 can subsequently disable processor 586 by activating control output 510, and can disable processor 590 by activating control output 530. The service processor 502 can then supply power from the VRM 556 to the microprocessor 586 by activating the control output 552 and closing the switch 568. Similarly, service processor 502 can supply power from VRM 564 to microprocessor 590 by activating control output 562 and closing switch 584. Alternatively, the service processor 502 can supply power from the VRM 556 to the microprocessor 590 by closing the switch 580 with the control output 520 activated, and closing the switch 578 with the control output 512 activated to close the VRM 564. To supply power to the microprocessor 586.

In other embodiments, the switching circuitry employed in the computer system 500 of FIG. 5 is even more flexible than some other embodiments, depending on any previous failures that the computer system 500 may have already experienced. Provide redundancy and redundancy. For example, assume that microprocessor 588 has previously experienced an internal failure. Service processor 502 may have already detected this fault and disabled processor 588 by activating control output 558. However, service processor 502 may also detect from status line 518 that VRM 556 still has a good voltage condition. As a result, control output 514 may still be active and switch 570 may still be closed. However, assume that computer system 500 experiences a failure of VRM 564 and that this failure is detected by service processor 502 via status input 536. Service processor 502 can disable microprocessor 592 by activating control output 540, activating control output 534 and activating control output 532 and opening switch 574. By separating the VRM 564, the VRM 564 can be disabled.

Service processor 502 can then continue by simply supplying power from VRM 550 to microprocessor 592 by activating control output 512 and closing switch 578, or alternatively, activating control output 562 and switching to switch 578. Closing 584 can continue by supplying power from VRM 560. However, the service processor 502 may be configured to recognize that the microprocessor 588 has already been disabled, which means that the power drain for the disabled microprocessor 588 is sufficiently low. This can mean that the VRM 556 may be available to supply power to other microprocessors. In that case, service processor 502 can activate control output 522 and close switch 582, thereby coupling power from VRM 556 to microprocessor 592. Thereafter, the service processor 502 can return the microprocessor 592 to the in-use state by disabling the invalid command from the control output 540.

It is worth emphasizing that the output of each VRM can be combined with any of the other outputs of other VRMs. The VRM 550 activates the control output 552 and closes the switch 568 to activate the microprocessor 588 and the control output 554 and closes the switch 576 to activate the microprocessor 590 and the control output 512. , And by closing switch 578, respectively, can be coupled to microprocessor 592. Similarly, by activating control outputs 552, 554, 512, 520, 522, and 562 to close each of switches 568, 576, 578, 580, 582, and 584, VRM 556, VRM 560, and VRM 564 are Each microprocessor can be individually coupled.

FIG. 6 illustrates what may be a larger computer system 600 having eight microprocessors and using two service processors that switch the voltage between the microprocessors. It will be noted that the computer system 600 differs from the embodiment with a single service processor or voltage control unit discussed above by the use of a dual service processor. This comparison helps to show how different embodiments can have different numbers of voltage regulation modules and different numbers of service processors composed of different numbers of microprocessors.

More specifically, the computer system 600 has a first service processor 602 that monitors four VRMs 610, 612, 614, and 616 having corresponding core voltages, 670, 672, 678, and 680. . The service processor 602 controls switching transistors 630, 632, 634, 636, 638, 640, and 642 to control voltages supplied to the four microprocessors 668, 674, 676, and 682. As reflected in the mirror, the second service processor 604 can monitor four VRMs 618, 620, 622, and 624 having corresponding core voltages 686, 688, 694, and 696. In addition, the service processor 604 can control the voltages supplied to the four microprocessors 684, 690, 692, and 698 with the switching transistors 644, 645, 646, 648, 650, 652, and 654.

Implementing computer system 600 using two service processors instead of one service processor can have a number of favorable benefits, such as a simpler service processor design. Alternatively, partitioning the processor and voltage regulator in such a manner may be required due to hardware requirements. For example, the computer system 600 can include a computer system in a server network. Dividing multiple processors among various server processors may be required in server systems due to spacing and thermal load requirements. That is, the service processor 602 and all associated VRMs and microprocessors are on one printed circuit board and can be loaded into rack-mounted computer system hardware. Maximum allowable circuit dimensions determined by application or hardware enclosure dimensions may require that service processor 604 and all associated VRMs and microprocessors be on separate printed circuit boards.

Similar to the previous example, service processors 602 and 604 can monitor and control the various VRMs, transistors, and microprocessors associated therewith. For example, during normal operation, service processor 604 can couple the output voltage from VRM 618, 620, 622, and 624 to each core voltage 686, 688, 694, and 696. The service processor 604 can couple the voltages by energizing the gates of P-type field effect transistors (P-fet) 644, 646, 650, and 654 to ground potential to turn them on and P -The gates of fets 645, 648, and 652 can be coupled to a positive voltage supply such as Vdd to turn off the transistors and isolate the cross-coupling lines connecting the outputs of the different VRMs.

Upon detecting a failure in one of the VRMs, the service processor 604 may use one or several of the several, in order to couple the voltage from the other functioning VRM to the processor affected by the failed VRM. The state of the transistor can be switched so that the affected processor can be held in a reset state, bypassed, or returned to a use state, similar to the techniques described above. For example, assume that VRM 622 fails, affecting the core voltage 694 and the power layer for the microprocessor 692. Service processor 604 can respond by energizing the gate of P-fet 650 to Vdd to isolate the voltage output of VRM 622 from the microprocessor and other VRM outputs. The service processor 604 can then combine the output from one of the other VRMs to provide to the core voltage 694 and the microprocessor 692. One possible coupling situation may include coupling the output of VRM 620 with core voltage 694 and microprocessor 692 by biasing the gate of P-fet 648 to ground. As can be seen, the voltage output of VRM 624 can also be coupled with core voltage 694 and microprocessor 692 by switching P-fet 652.

Service processor 602 may operate in a manner similar to that described for service processor 604. In other embodiments, the service processor can combine the voltage output of the VRM using a device other than P-fet. For example, in some embodiments, only N-type fet or a combination of P-fet and N-fet can be utilized. In still further embodiments, other circuit devices may operate with fets, switches, or contacts. For example, the switching P-fet for the computer system 600 shown in FIG. 6 may provide benefits such as debouncing, smoother switching operations, and reduced inductive kick-back. And a capacitor element and a resistor element coupled to the transistor. Further, although not specifically mentioned in the description of the above-described embodiments, addition of other circuit devices such as a switching network to various embodiment components is also applicable.

Further, the service processor and voltage control unit for the various embodiments can be relatively simple, such as a relatively small and simple arrangement of logic gates. However, in other embodiments, the service processor and voltage control unit include a relatively complex processor having an internal clock oscillator, memory, coded processing instructions, and a software program that performs the invalidation and voltage switching processor functions. Can be included.

Reference is now made to FIGS. 7 and 8 which illustrate how the multiprocessor computer operates when the processor voltage regulator experiences an error. FIG. 7 begins with operating a system having multiple processors (element 705). Different embodiments may have multiple processors arranged in different computer architectures, such as shared memory computer architectures, distributed memory architectures, and combinations or derivatives of both. All processors can be coupled together on a single bus, or a cluster of processors can be coupled together via a smaller and individual processor group bus.

The method of FIG. 7 can continue by monitoring the multiprocessor computer system for voltage error conditions (element 710). Monitored error conditions may change for different embodiments. For example, in some embodiments, the error condition may be a lack of one or more of the VRMs required by the microprocessor. In other embodiments, the error condition may be a lack of good core voltage. While no error condition is detected, no action is required by this method, but may simply include continuing monitoring for the error condition (elements 715 and 710). However, once an error condition is detected, the system based on the method of FIG. 7 can continue by isolating or disabling the voltage error condition (elements 715 and 720). For example, a computer system that functions based on the method of FIG. 7 can be isolated or prohibited from being supplied with voltage to the input of a defective voltage regulator. Alternatively, embodiments can isolate a faulty voltage regulator by opening a switch coupled between the regulator output and the regulator load.

The embodiment based on FIG. 7 resets the affected processor due to the voltage error condition (element 725) and activates the switch to supply voltage from the other power source to the affected processor (element 730) can continue. In some embodiments, the other power source can be another voltage regulator of the system. However, in other embodiments, the other voltage source can be an unfiltered and unregulated voltage source.

When the affected processor is reset (element 725), the processor is held in a reset state (element 735) and the input / output associated with the affected processor can be tri-stated from the address bus. (Element 745), allowing other processors in the computer system to operate without being interrupted by the disabled or bypassed processor (Element 750). In various embodiments, the affected processor can be isolated from other buses in the system. For example, the processor may be isolated from a data bus, a control bus, or a combination of all three types of buses.

Other embodiments of the invention include a processor for a service processor, a core voltage processor, or even a system processor powered by various voltage sources based on, for example, a computer system 500 as shown in FIG. It is realized as a program product for such a circuit component device. A program product program defines the functionality of the embodiments (including the methods described herein) and may be stored on various data-bearing media and / or signal-bearing media. Exemplary data retention media and / or signal retention media include (i) information permanently stored on a non-writable storage medium (eg, a read-only memory device in a computer system), and (ii) writable. Including, but not limited to, variable information (eg, magnetic media) stored on a storage medium. Such data-carrying media and / or signal-carrying media represent embodiments of the invention when providing microprocessor readable instructions that direct the functionality of the invention.

In general, a routine that is executed to implement an embodiment of the present invention is a portion of an operating system, or a series of components, programs, modules, objects, or a series of memory stored in circuit board device memory. It can be an instruction. The microprocessor program of the present invention may consist of a number of instructions that will be converted to a machine readable format, ie executable instructions, on a microprocessor. A program may also consist of variables and data structures that reside locally to the program or that are found in memory or other storage. In addition, the various programs described below may be identified based on their use in which the various programs are executed in a particular embodiment of the invention. However, any particular program terminology described above is merely used for convenience and, therefore, the present invention is identified in any particular application identified and shown in such terminology. It should be understood that use is not limited to applications.

Those skilled in the art of computer computing and multiprocessor computer system design readily understand the flexibility and opportunities that various embodiments for providing power to the processors of a multiprocessor computer system provide to the field of multiprocessor computer systems. Will do. These examples are just a few of the possible cases, and how to supply power to a processor in a multiprocessor system, or a machine and medium that accomplishes substantially the same, is a multiprocessor computer system design. To provide the field.

It will be apparent to those skilled in the art having the benefit of this disclosure that the present invention contemplates a method, apparatus, and medium that provides and diverts power to a processor of a multiprocessor computer system in the event of a component failure. Let's go. It is understood that the form of the invention shown and described in the detailed description and drawings is to be construed as an example only. The claims should be construed broadly to include all variations of the disclosed example embodiments.

Although the invention and its several advantages have been described in detail for certain embodiments, various changes, substitutions, and modifications can be made without departing from the spirit and scope of the invention as set forth in the claims. It should be understood that this can be done herein. Also, embodiments can achieve multiple objectives, but not all embodiments within the scope of the claims realize all objectives. Further, the scope of the present application is not limited to the specific embodiments of processes, machines, products, composites, means, methods, and steps described herein. Existing, or later developed processes, machines, products, that perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein, Those skilled in the art will readily understand from the present disclosure that compositions, means, methods, or steps may be utilized in accordance with the present invention. Accordingly, the claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

FIG. 2 illustrates a multiprocessor computer system having two processors, two voltage regulator modules, and a device for switching between two regulator modules. FIG. 2 shows an apparatus for controlling core voltage for two processors. FIG. 2 is a system diagram having a service processor that controls voltages from two voltage regulator modules of a two processor computer system. FIG. 2 illustrates a multiprocessor computer system having four processors and two voltage regulator modules with a service processor that controls the voltage to the processor. FIG. 3 shows how a service processor can control the voltages from four voltage regulators for four processors. FIG. 2 illustrates a computer system having eight microprocessors, eight voltage regulator modules, and two service processors that switch voltages between the microprocessors. FIG. 6 illustrates a method of operating a multiprocessor computer when one of the processor voltage regulators has an error. FIG. 6 illustrates a method of operating a multiprocessor computer when one of the processor voltage regulators has an error.

Claims (23)

A method of supplying power to a processor of a computer system having a plurality of processors, comprising:
Determining a parameter associated with a first voltage potential coupled to the processor;
Based on the parameters,
Separating the first voltage potential from the processor;
Disabling the processor;
Coupling a second voltage potential to the processor. The method of claim 1, further comprising operating the computer system having the disabled processor. The method of claim 1, wherein determining a parameter comprises detecting whether the first voltage potential is less than an acceptable value. The method of claim 1, wherein determining a parameter comprises detecting a status signal from the processor. The method of claim 1, wherein determining the parameter comprises detecting a status signal from a voltage regulator module. The method of claim 1, wherein isolating comprises disabling a voltage regulator module that is generating the first voltage potential. The method of claim 1, wherein isolating comprises turning off a transistor that couples the first voltage potential to the processor. The method of claim 1, wherein disabling includes sending an invalid signal to the processor, thereby causing the processor to tri-state at least one of its outputs. The disabling step includes sending a reset signal to the processor, thereby causing the processor to be in a reset state and causing the processor to tri-state at least one of its outputs. The method described. The method of claim 1, wherein coupling includes closing a relay contact to couple the second voltage potential to the processor. The method of claim 1, wherein coupling comprises activating a transistor to couple the second voltage potential to the processor. An apparatus for supplying a voltage to a processor of a computer system having a plurality of processors,
An error detection circuit for detecting an error condition associated with a first voltage regulator module that supplies voltage to the processor;
A disabling circuit for disabling the first voltage regulator module if the error detection circuit detects the error;
A processor isolation circuit that places the processor in an isolated state in which one or more of the processor inputs and outputs are isolated from the bus of the computer system when the error detection circuit detects the error;
A voltage switching circuit for supplying a voltage from a second voltage regulator module to the processor when the error detection circuit detects the error. The apparatus of claim 12, wherein the error detection circuit, the invalidation circuit, the processor isolation circuit, and the voltage switching circuit comprise a service processor. The apparatus of claim 13, further comprising a disable output coupled to the disable circuit to disable the first voltage regulator module. The apparatus of claim 13, further comprising a voltage switching output coupled to the voltage switching circuit to activate a transistor coupling the second voltage regulator module to the processor. The apparatus of claim 12, wherein the error detection circuit is adapted to detect a lack of voltage from the first voltage regulator module. The apparatus of claim 12, wherein the disabling circuit includes a transistor for electrically isolating the first voltage regulator from the processor. The apparatus of claim 12, wherein the processor isolation circuit is adapted to hold the processor in a reset state. The apparatus of claim 12, wherein the voltage switching circuit includes a transistor that couples the second voltage regulator to the processor. A multiprocessor computer system,
Two or more processors;
Two or more voltage regulation modules for supplying voltage to the two or more processors;
A voltage error detection module for detecting a problem in at least one of the two or more voltage regulation modules;
A voltage separation module that separates the at least one voltage regulation module from at least one of the two or more processors affected by the problem based on the voltage error detection module that detects the problem;
A voltage switching module that couples at least one of the two or more voltage regulation modules not affected by the problem with the at least one of the two or more processors affected by the problem; , Including system. 21. A processor invalidation module that disables the at least one of the two or more processors affected by the problem in response to the voltage error detection module detecting the problem. The system described in. 23. The system of claim 21, wherein the processor invalidation module isolates the processor affected by the problem from the computer system bus in response to the voltage error detection module detecting the problem. The system of claim 20, wherein the computer system includes a server.

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