JP2012194749A - Multiprocessor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To properly change electric power source redundancy in a plurality of instruction execution means.SOLUTION: A multiprocessor device includes: a plurality of instruction execution means for executing instruction; a plurality of electric power supply means capable of supplying electric power of desired voltage to the plurality of instruction execution means; electric power supply connection switching means capable of switching to which of the plurality of instruction execution means each of the plurality of electric power supply means supplies electric power; and control means for controlling the electric power supply connection switching means so that redundancy of the electric power supply means allocated to the plurality of instruction execution means is determined according to importance of instruction executed by the plurality of instruction execution means.

Description

  The present invention relates to a multiprocessor device including a plurality of instruction execution means for executing instructions.

  Conventionally, in the field of microcomputers, a plurality of power supply means (more specifically, a power supply circuit, etc.) are assigned to instruction execution means such as a CPU, and instructions are executed even if part of the power supply circuit etc. fails. Means are being made operable. Thus, allocating more power supply means than the minimum necessary number is called power redundancy, ensuring power redundancy, and the like.

  Patent Document 1 describes an uninterruptible power supply system including a plurality of uninterruptible power supply devices that supply power to a plurality of components each composed of one or a plurality of electronic devices. In this system, each of the plurality of uninterruptible power supplies is provided corresponding to each of the plurality of components in accordance with the power redundancy determined for each of the plurality of components, and supplies power to at least the corresponding component. Yes.

JP 2002-136000 A

  However, in the above conventional uninterruptible power supply system, the necessity of changing the power redundancy set for each component is not taken into consideration, and the situation where the power redundancy becomes excessive or insufficient is supported. You may not be able to.

  The present invention has been made to solve such problems, and a main object of the present invention is to provide a multiprocessor device capable of appropriately changing the power supply redundancy in a plurality of instruction execution means.

In order to achieve the above object, one embodiment of the present invention provides:
A plurality of instruction execution means for executing the instructions;
A plurality of power supply means capable of supplying power of a desired voltage to the plurality of instruction execution means;
Each of the plurality of power supply means can switch power supply connection switching means capable of switching which of the plurality of instruction execution means supplies power;
Control means for controlling the power connection switching means so that the redundancy of the power supply means allocated to the plurality of instruction execution means is determined according to the importance of the instructions executed by the plurality of instruction execution means;
Is a multiprocessor device.

  According to this aspect of the present invention, the power supply connection switching unit is configured such that the redundancy of the power supply unit allocated to the plurality of instruction execution units is determined according to the importance of the instructions executed by the plurality of instruction execution units. Therefore, it is possible to appropriately change the power redundancy in the plurality of instruction execution means.

In one embodiment of the present invention,
The redundancy is determined based on the number of instruction execution means and power supply means in a group in which at least some of the plurality of instruction execution means and at least some of the plurality of power supply means are connected in parallel. It may be an index value.

In one embodiment of the present invention,
The importance level of instructions executed by the plurality of instruction execution means is notified from the plurality of instruction execution means to the control means, for example.

In one embodiment of the present invention,
A failure detection means for detecting occurrence of a failure in each of the plurality of power supply means;
When the failure detection unit detects that a failure has occurred in any of the plurality of power supply units, the control unit supplies at least an instruction execution unit connected to the power supply unit in which the failure has occurred. The power supply connection switching unit and / or the power supply unit may be controlled to maintain power supply.

In one embodiment of the present invention,
Clock generating means capable of generating clock signals of different frequencies and outputting them from different output terminals;
A clock switching means capable of switching which of the plurality of power supply means is connected to which output terminal of the clock generation means;
May be provided.

  Here, the clock switching means may be separate from the power connection switching means or may be the same body.

  According to the present invention, it is possible to provide a multiprocessor device capable of appropriately changing power supply redundancy in a plurality of instruction execution means.

1 is a system configuration example of a multiprocessor device 1 according to an embodiment of the present invention. It is an example of circuit composition of PS and FD concerning one example of the present invention. It is an internal structural example of the control apparatus 50 which concerns on one Example of this invention. 4 is an example of power supply configuration information written in a storage unit 52. FIG. 5 is a diagram illustrating a connection relationship between a PE and a PS, which is a source of the power supply configuration information illustrated in FIG. 4. It is explanatory drawing for demonstrating redundancy ensuring of a power supply. It is explanatory drawing for demonstrating redundancy ensuring of a power supply. It is explanatory drawing for demonstrating redundancy ensuring of a power supply. It is an example of a task group table 76 stored in a ROM 70, a RAM 72, or the like. It is a figure which shows typically the concept of the redundancy in this invention. It is a figure which shows the connection relation and state of PE and a power supply in a certain state (initial state). It is a figure for comparing the structure which does not change power supply redundancy in the case where a state change arises, and the structure of a present Example. It is a figure for comparing the structure which does not change power supply redundancy in the case where a state change arises, and the structure of a present Example. It is a figure for comparing the structure which does not change power supply redundancy in the case where a state change arises, and the structure of a present Example. 4 is a flowchart showing a flow of processing of each component of the multiprocessor device 1 when a power failure occurs.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described with reference to the accompanying drawings.

  A multiprocessor apparatus according to an embodiment of the present invention will be described below with reference to the drawings. The multiprocessor device of the present invention can be applied to, for example, a multicore processor in which a plurality of processor cores are sealed on the same chip. However, the present invention is not limited to this. The present invention can also be applied to an apparatus including a plurality of computer units including (Random Access Memory).

[Configuration and basic functions]
FIG. 1 is a system configuration example of a multiprocessor device 1 according to an embodiment of the present invention. The multiprocessor device has, as main components, PE (Processor Element) 10 # 1 to 10 # N, PS (Power Supply) 20 # 1 to 20 # M, and FD (Fault Detection) 25 # 1 to 25 # M. A clock generation circuit 30, a SWMX (Switch Matrix) 40, a control device 50, a BUS control unit 60, a ROM 70, a RAM 72, and a peripheral circuit 74.

  The PEs 10 # 1 to 10 # N are processor cores in the multi-core processor, for example, and are an example of an instruction execution unit that executes instructions stored in a program memory such as a ROM.

  Each PE includes an instruction fetch unit that fetches instructions stored in the ROM 70 and other program memories, an instruction decoder that decodes the fetched instructions, an ALU (Arithmetic Logic Unit) and an FPGA (Field Programmable Gate) that perform arithmetic processing. Array), SIMD arithmetic unit, LSU (Load Store Unit), hardware such as general-purpose registers.

  An instruction executed by each PE is recognized, for example, in units of tasks (or processes) having a certain degree of functional unit. The importance level corresponding to the importance of the process is set in advance for the task. The importance level of a task can be rephrased as the importance level of an instruction group included in the task.

  The importance of the task can be recognized by each PE by referring to the task group table 76 stored in the ROM 70, RAM 72, register, cache memory or the like. The data for identifying the task may be embedded in a part of the instruction group (header or the like) constituting the task, or recognized by an OS (Operating System) (not shown) and notified to the PE. May be.

  With such a configuration, each PE can output the importance of the task it is performing to other components.

  Further, in the task group table 76, in addition to the importance of the task, a desirable processing speed (more specifically, a desirable clock frequency) may be defined corresponding to the task. Specific contents of the task group table 76 will be described later.

  PS20 # 1 to 20 # M are, for example, output voltage variable type power supply circuits. Each PE generates a voltage required by one or more PEs to which it is assigned, and supplies power to the PE. Each PS may have a period in which a PE is not allocated and is in a dormant state. Hereinafter, PS is simply referred to as “power supply” as necessary.

  FDs 25 # 1 to 25 # M are power failure detection circuits attached to each PS. Each FD detects a failure of the attached PS and outputs it to the control device 50.

  FIG. 2 is a circuit configuration example of PS and FD. In the figure, each PS is represented as PS20, and each FD is represented as FD25. The PS 20 includes a PNP transistor 21 having a battery voltage VBAT connected to the collector, a variable resistor (not shown), and the like. The voltage applied to the base of the PNP transistor 21 is controlled by the control device 50. Further, the FD 25 includes a resistor 26 and a failure detection unit 27 for measuring the output voltage of the PS 20 and outputting it to the control device 50.

  The clock generation circuit 30 includes a reference clock generation circuit, a frequency divider, and the like, and outputs a clock signal having a plurality of types of frequencies from, for example, an output terminal provided for each frequency.

  The SWMX 40 has a plurality of switch structures and switches the connection relationship between the PEs 10 # 1 to 10 #N, the PS 20 # 1 to 20 #M, and the output terminal of the clock generation circuit 30. That is, the SWMX 40 obtains which of the PEs 10 # 1 to 10 # N is supplied with power by each of the PS20 # 1 to 20 # M, and what frequency the PE10 # 1 to 10 # N acquires. Switch what to do.

  FIG. 3 is an internal configuration example of the control device 50. The control device 50 includes a bus interface (I / F) 51 serving as an interface with the processor bus 80, a storage unit 52, a matrix driver 53, and a microcomputer (CPU) 54. Note that any PE may function as the control device 50.

  The bus interface 51 acquires various information such as power supply voltage setting, clock frequency, task priority, and the like from each PE via the processor bus 80 and outputs the information to the microcomputer 54.

  The storage unit 52 is, for example, a register or a flash memory, and power supply configuration information expressing the power supply configuration at that time is written by the microcomputer 54. FIG. 4 is an example of power supply configuration information written in the storage unit 52. Further, FIG. 5 shows the connection relationship between the PE and PS, which is the source of the power supply configuration information shown in FIG. As shown in these drawings, in this embodiment, a group of PEs and PSs in which one or more PEs and one or more PSs are connected in parallel is recognized as a power supply group and stored in the storage unit 52.

  The matrix driver 53 executes switching control of the SWMX 40 in response to an instruction signal from the microcomputer 54.

  The microcomputer 54 determines the power supply configuration according to the power supply voltage setting and task priority input from each PE and instructs the matrix driver 53. Further, the matrix driver 53 is instructed so that the clock frequency input from each PE is supplied to the PE. At the clock frequency switching timing, the clock generation circuit 30 is instructed to temporarily stop the clock signal, and control is performed so that noise is not generated in the clock signal supplied to each PE.

[Control based on priority]
[About power supply redundancy]
Hereinafter, power supply configuration change control based on task priority executed by the microcomputer 54 of the control device 50 will be described.

  First, ensuring power supply redundancy will be described. 6 to 8 are explanatory views for explaining redundancy of power supply. As shown in FIG. 6, when one power source drives the number of driveable PEs (when there is no redundant connection), when the power source fails, the PEs belonging to the power source group become inoperable.

  On the other hand, as shown in FIG. 7, when two power supplies are driving the number of PEs that can be driven by one power supply (when two power supplies are in parallel), even if one power supply fails, the power supply group Since the PEs belonging to are supplied with power from the remaining power supply, the operation can be continued.

  Further, as shown in FIG. 8, when three power supplies are driving the number of PEs that can be driven by two power supplies (in the case of three power supplies in parallel), even if one power supply fails, the power supply group Since the PEs belonging to are supplied with power from the remaining power supply, the operation can be continued.

  Next, task priority recognition will be described. FIG. 9 is an example of the task group table 76 stored in the ROM 70, RAM 72, etc. as described above. As shown in the figure, the task group table 76 defines the importance and the processing speed request for each task group including a plurality of tasks. Of these, importance is used to determine power supply redundancy, and processing speed requirements are used to determine clock frequency.

[About redundancy]
FIG. 10 is a diagram schematically showing the concept of redundancy in the present invention. The redundancy is an index value indicating power supply redundancy, and is expressed by the following equation (1), for example.

(Redundancy) = {1− (number of power sources that can continue to operate even if a failure occurs) / (number of power sources in the group)} ⁻¹ (1)

  Therefore, when three power supplies are driving the number of PEs that can be driven by two power supplies, the redundancy is 1.5. When two power supplies are driving the number of PEs that can be driven by one power supply, the redundancy is two. Further, when one power source drives the number of PEs that can be driven by one power source, the redundancy is 1.

  Here, “the number of power supplies that can continue to operate even if a failure occurs” is obtained by subtracting “the minimum number of power supplies” from “the number of power supplies in the group”. The “minimum number of necessary power supplies” is determined in advance within the range shown in the following equation (2), for example, and stored in the ROM 70 or RAM 72 and can be referred to by the control device 50 in advance. In the equation, k is a coefficient indicating how many PEs the power supply can drive, and is a value that changes according to the output voltage of the power supply.

  (Minimum number of necessary power supplies) = (Number of PEs in group / k) to 2 × (Number of PEs in group / k) (2)

  As shown in FIG. 10, and as is clear from the above equation (1), the power supply group 1 in which two power supplies supply power to two PEs has the highest power supply redundancy (redundancy = 2). The power supply group 2 in which three power supplies four PEs is the next highest in power redundancy (redundancy = 1.5), and the power supply group 3 in which one power supply supplies two PEs has power redundancy. The lowest (redundancy = 1).

[Switching control based on redundancy, etc.]
Hereinafter, a scene in which the control device 50 switches the connection relationship between the PE and the power supply based on redundancy or the like will be described.

  FIG. 11 is a diagram illustrating a connection relationship between the PE and the power source and a state in a certain state (initial state). In this state, PE10 # 1 and PE10 # 2 are operating at processing speed = “high” and task importance = “high”, and PE10 # 3 and PE10 # 4 are processing speed = “low” and task importance. = “Low”. The power sources 20 # 1 and 20 # 2 are connected in parallel to the PEs 10 # 1 and PE10 # 2, and only the power source 20 # 3 is connected to the PEs 10 # 3 and PE10 # 4.

  (1) From the state shown in FIG. 11, PE10 # 1 and PE10 # 2 operate with processing speed = “low” and task importance = “low”, and PE10 # 3 and PE10 # 4 operate with processing speed = “medium”. Consider the case where the task importance level is switched to “medium”. FIG. 12A is a diagram illustrating the PE and power connection relationship and state when the power configuration is not changed. In this case, since the power supplies are connected in parallel to the PEs 10 # 1 and 10 # 2 that do not require much power redundancy, not only the power supply becomes excessive, but also supplied to the PEs 10 # 3 and PE10 # 4. There will be a shortage of electricity. Also, the redundancy of PE10 # 3 and PE10 # 4 that require relatively high power redundancy remains low.

  On the other hand, FIG. 12B is a diagram illustrating a state in which the control device 50 according to the present embodiment switches the connection relationship and state between the PE and the power source. As shown in the figure, PE10 # 3 and PE10 # 4 with higher task importance are integrated into the same power supply group, and power is connected in parallel to these two to increase redundancy. For this reason, the power supply redundancy of the PS having a relatively high task importance is increased, and the safety of the apparatus can be improved.

  In addition, since excessive power is not supplied to the PEs 10 # 1 and 10 # 2 having relatively low task importance, the power consumption of the entire apparatus can be suppressed.

  (2) Next, from the state shown in FIG. 11, PE10 # 1 and PE10 # 2 operate with processing speed = “high” and task importance = “high”, and PE10 # 3 and PE10 # 4 operate with processing speed = Consider a case where “medium” and task importance = “medium” are switched. FIG. 13A is a diagram illustrating the PE and power connection relationship and state when the power configuration is not changed. In this case, the power supplied to PE10 # 3 and PE10 # 4 is insufficient.

  On the other hand, FIG. 13B is a diagram illustrating a state in which the control device 50 according to the present embodiment switches the connection relationship and state between the PE and the power source. As shown in the drawing, since the control device 50 instructs to change the output voltage of the PS 20 # 3 to “medium”, the power supplied to the PE 10 # 3 and PE 10 # 4 is not insufficient.

  (3) Next, from the state shown in FIG. 11, PE10 # 1 operates at processing speed = “high” and task importance = “low”, and PE10 # 2, PE10 # 3, and PE10 # 4 operate at processing speed = Let us consider a case where the state is switched to an operation state with “low” and task importance = “low”. FIG. 14A is a diagram illustrating the PE and power connection relationship and state when the power configuration is not changed. In this case, the power supplied to PE10 # 1 and PE10 # 2 becomes excessive, resulting in wasteful power consumption.

  On the other hand, FIG. 14B is a diagram illustrating a state in which the control device 50 according to the present embodiment switches the connection relationship and state between the PE and the power source. As shown in the figure, PE10 # 1 and PE10 # 2 are set as separate power supply groups to reduce power supply redundancy, and the output voltage of PS20 # 2 that supplies power to PE10 # 2 is changed to "low". The power consumption of the entire device can be suppressed.

[Control at power failure]
Further, when a failure detection signal is input from any one of the FDs 25 # 1 to 25 # M, the microcomputer 54 of the control device 50 instructs the matrix driver 53 to control the failed PS to be disconnected from the PE. . In consideration of the correspondence relationship between the power supply group, PS, and PE stored in the storage unit 52, if the power supply group to which the failed PS belongs is not in a redundant configuration, the PE that has been driven by the failed PS An interrupt signal is sent to notify the power failure. Also, power failure information is set in the internal power failure notification register so that information regarding the failed PS can be referred from each PE.

  FIG. 15 is a flowchart showing the flow of processing of each component of the multiprocessor device 1 when a power failure occurs.

  First, it waits until one of the power supply failure detection circuits (FD) detects a failure of the power supply (PS) (S100).

  When any one of the power failure detection circuits detects a power failure, the power failure detection circuit (FD) notifies the control device 50 of the power failure (S102).

  The control device 50 disconnects the failed power source from the PE by changing the corresponding part of the SWMX 40 to open (S104).

  Next, the control device 50 determines whether or not the power supply group to which the failed power supply belongs is redundantly connected (S106).

  If the redundant connection is established, it is determined whether or not the redundancy can be recovered only with the power supply in which the power supply group has not failed (S108). If the redundancy can be recovered, the control device 50 instructs the power supply to increase the output voltage and recovers the redundancy (S110).

  If the redundancy cannot be recovered, the control device 50 performs control such as instructing the SWMX 40 to add power (S112).

  On the other hand, if the power supply group to which the failed power supply belongs is not redundantly connected, an interrupt signal for notifying the power supply failure to the PE belonging to the power supply group is sent (S114).

  The PE that has received the interrupt signal starts execution interruption processing (S116).

  Next, the control device 50 determines whether or not the PE can be connected to a power supply that has not failed (S118). If the PE can be connected to a power supply that does not fail, the PE is connected to the power supply that does not fail by instructing the SWMX 40, and an interrupt signal is sent to notify the PE of power recovery (S120).

  According to the multiprocessor device 1 of the present embodiment described above, the power supply redundancy in the plurality of PEs can be changed appropriately because the power supply redundancy is dynamically changed based on the priority of the task.

  Further, when a failure occurs in any of the plurality of power supplies, the power supply to the PE can be maintained using another power supply.

  Moreover, the power consumption of the entire apparatus can be suppressed by reducing the power supply to the PE whose task priority and processing speed are reduced.

  The best mode for carrying out the present invention has been described above with reference to the embodiments. However, the present invention is not limited to these embodiments, and various modifications can be made without departing from the scope of the present invention. And substitutions can be added.

1 Multiprocessor device 10 # 1, 10 # 2, ... PE
20 # 1, 20 # 2, ... PS (power supply)
21 PNP transistor 25 # 1, 25 # 2, ... FD
26 resistance 27 failure detection unit 30 clock generation circuit 40 SWMX
50 Control device 51 Bus interface (I / F)
52 Storage Unit 53 Matrix Driver 54 Microcomputer (CPU)
60 BUS control unit 70 ROM
72 RAM
74 Peripheral circuit 76 Task group table 80 Processor bus

Claims (5)

A plurality of instruction execution means for executing the instructions;
A plurality of power supply means capable of supplying power of a desired voltage to the plurality of instruction execution means;
Each of the plurality of power supply means can switch power supply connection switching means capable of switching which of the plurality of instruction execution means supplies power;
Control means for controlling the power connection switching means so that the redundancy of the power supply means allocated to the plurality of instruction execution means is determined according to the importance of the instructions executed by the plurality of instruction execution means;
A multiprocessor device comprising: The multiprocessor device according to claim 1, comprising:
The redundancy is determined based on the number of instruction execution means and power supply means in a group in which at least some of the plurality of instruction execution means and at least some of the plurality of power supply means are connected in parallel. Index value
Multiprocessor device. The multiprocessor device according to claim 1 or 2,
The degree of importance of instructions executed by the plurality of instruction execution means is notified from the plurality of instruction execution means to the control means.
Multiprocessor device. A multiprocessor device according to any one of claims 1 to 3,
A failure detection means for detecting occurrence of a failure in each of the plurality of power supply means;
When the failure detection unit detects that a failure has occurred in any of the plurality of power supply units, the control unit supplies at least an instruction execution unit connected to the power supply unit in which the failure has occurred. Means for controlling the power connection switching means and / or the power supply means so that power supply is maintained;
Multiprocessor device. A multiprocessor device according to any one of claims 1 to 4, comprising:
Clock generating means capable of generating clock signals of different frequencies and outputting them from different output terminals;
A clock switching means capable of switching which of the plurality of power supply means is connected to which output terminal of the clock generation means;
A multiprocessor device comprising:

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