JPH04252387A - Microcomputer - Google Patents

Abstract

PURPOSE:To perform memory access while executing refreshing by detecting the access of a memory not requiring the refreshing. CONSTITUTION:A refreshing unnecessary area accessing signal 120 is generated when an external memory accessing signal 110 and a refreshing unnecessary area signal 118 are simultaneously generated. When on overflow signal 105 is generated from a free running counter 102, an F.F119 is set. When the refreshing unnecessary area accessing signal 120 is generated while setting the F.F119, a refreshing timing signal 121 is generated and a refreshing control circuit 104 outputs a refreshing pulse 113. In short, the refreshing pulse is outputted during the access to the external memory not requiring the refreshing.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, and more particularly to a microcomputer having a pseudo SRAM refresh pulse generation function.

0002

BACKGROUND OF THE INVENTION In recent years, the number of applications using large-capacity memories has been increasing. DRAM is a typical large-capacity memory, but there are opinions that it is difficult to use because timing control is difficult. Further, SRAM has the advantage of easy timing control and high speed, but has the disadvantage of being expensive.

[0003] Therefore, in recent years, pseudo SRAMs, which are relatively easy to control timing and are inexpensive, are increasingly being used, and microcomputers with a built-in pseudo SRAM refresh function have been commercialized.

First, a conventional microcomputer with a built-in pseudo SRAM refresh function will be explained with reference to the drawings. FIG. 6 is a block diagram showing the configuration of a refresh pulse generation circuit of a conventional microcomputer. First, the constituent elements will be explained. A clock 601 is a signal that controls the operation of each circuit.
Free running counter 60 from U (not shown)
2, bus control circuit 603, refresh control circuit 604
supplied to Free running counter 602 is a counter that counts clock 601 and periodically generates overflow signal 605. Bus control circuit 6
03 is a clock 601 and a refresh cycle signal 6
11, and outputs an address strobe signal 606, a read signal 607, and a write signal 608. It also outputs an external memory access request signal 609.

External memory access signal 610 is a signal that becomes active when external memory access request signal 609 is output while refresh cycle signal 611 is not output. Refresh control circuit 604 inputs clock 601, overflow signal 605, and external memory access signal 610, outputs refresh cycle signal 611 to bus control circuit 603, and outputs refresh pulse 613 to terminal 114.

Next, the operation will be explained. A free running counter 602 inputs the clock 601 and counts up, and periodically outputs an overflow signal 6.
05 is output to the refresh control circuit 604.

Bus control circuit 603 generates external memory access request signal 609 when accessing external memory, and if refresh cycle signal 611 is not generated at this time, address strobe signal 606, read signal 607, and write signal 608 are generated. occurs. Also, when the refresh cycle signal 611 is generated, the external memory access request signal 609 is output, and the output of the address strobe signal 606, read signal 607, and write signal 608 is suspended until the refresh cycle signal 611 is released. do.

When an overflow signal 605 is generated when an external memory access signal 610 is not generated, the refresh control circuit 612 generates a refresh cycle signal 611 to indicate to the bus control circuit 603 that it is a refresh cycle, and also performs a refresh cycle. Pulse 613 is output to terminal 614. If the overflow signal 105 is generated while the external memory access signal 610 is being generated, the output of the refresh cycle signal 611 and refresh pulse 613 is suspended, and after the external memory access signal 610 is released, the refresh cycle signal 611, A refresh pulse 613 is output.

Furthermore, if the overflow signal 605 and external memory access request signal 609 occur at the same time,
At the same time as the overflow signal 605 is generated, the refresh cycle signal 611 is generated, the external memory access signal 610 is not generated, and the refresh control circuit 604 is configured to control the refresh cycle signal 611, the refresh pulse 6
13 is generated.

Bus control circuit 603 waits until refresh cycle signal 611 is released, and then outputs address strobe signal 606, read signal 607, and write signal 608. Therefore, the output of the refresh pulse is awaited during external memory access, and external memory access is awaited during the refresh cycle.

FIG. 7 shows a timing chart of a conventional microcomputer with a built-in refresh function. This pseudo SRAM generates two refresh pulses for 4ms.
Must be entered 56 times. If the period of the free running counter is set to generate 256 refresh pulses in 4 ms, and the refresh pulse output and external memory access conflict or overlap each time, it is assumed that a conventional microcomputer with a built-in refresh function is used. In this case, the external memory access will be waited for as many as 256 times.

Assuming that a weight of 500 ns is applied each time, 256 times is 500 ns×256=128 μs, which corresponds to about 3.2% of 4 ms.

Next, an example of a microcomputer system using a microcomputer without a built-in refresh function will be described with reference to the drawings. FIG. 8 is a block diagram showing the configuration of a system using a microcomputer without a built-in refresh function.

First, the constituent elements will be explained. The microcomputer 801 receives an address strobe signal 802.
, a read signal 803, and a write signal 804, and input and output addresses and data to and from an address/data bus 805. Address latch 806 inputs address strobe signal 802 and address/data bus 805, and inputs address bus 807 to address decoder 808 and PROM.
810, output to pseudo SRAM 811. Address decoder 808 transfers PROM selection signal 812 to PROM8.
10, output to the refresh pulse generation circuit 809, and output the pseudo SRAM selection signal 813 to the pseudo SRAM 811.

The refresh pulse generation circuit 809 has P
Input ROM selection signal 812 and refresh pulse 8
14 to the pseudo SRAM 811. PROM810
inputs the read signal 803, PROM selection signal 812, and address bus 807, and outputs the address/data bus 805.
Output data to . The pseudo SRAM 811 receives a write signal 804, a pseudo SRAM selection signal 813, a refresh pulse 814, and an address bus 807, and inputs and outputs the same to an address/data bus 805.

Next, the operation will be explained. Microcomputer 801 outputs the address of the external memory to be accessed to address/data bus 805 and outputs address strobe 802 . At this time, address latch 806 latches the address on the address/data bus and outputs it to address bus 807, and address decoder 808 outputs PROM selection signal 812 or pseudo SRAM selection signal 813. When the PROM selection signal 812 is generated, the refresh pulse generation circuit 8
09 generates a refresh pulse 814 using the PROM selection signal 812 and outputs it to the pseudo SRAM 811.

Next, microcomputer 801 generates read signal 803 to read data from PROM 810 via address/data bus 805 . That is, the microcomputer 801 uses the PROM 810
The configuration is such that the pseudo SRAM 811 is refreshed while accessing.

[0018]

[Problems to be Solved by the Invention] In the conventional microcomputers that have a built-in refresh function as described above, whenever there is a conflict between an external memory access such as a fetch or a data access and a refresh cycle, the external memory access is forced to wait. The drawback is that the execution speed for external memory is significantly slower than when using a microcomputer that does not have a built-in microcomputer.

[0019] Furthermore, in a system using a microcomputer that does not have a built-in refresh function, other memories are not always accessed at a frequency higher than a certain level.
There was a risk that the frequency of the refresh pulse would temporarily drop and the data held in the pseudo SRAM would be destroyed.

An object of the present invention is to provide a microcomputer that can execute refresh at a constant cycle and access external memory in parallel during refresh.

[0021]

[Means for Solving the Problems] A microcomputer of the present invention includes means for detecting memory access that does not require refreshing, a free running counter that periodically generates an overflow signal, and a free running counter that periodically generates an overflow signal. and means for outputting a refresh pulse when the memory access is detected after the occurrence of the memory access.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention.

First, the constituent elements will be explained. Here, a clock 101, a free running counter 102
, bus control circuit 103, external memory access signal 110
, the external memory access request signal 111, the refresh pulse 113, and the terminal 114 are the same as in the conventional example described above, so a description thereof will be omitted. Address bus 115 outputs the address of the memory to be accessed to address comparison circuit 117. The refresh area setting register 116 is a register for setting an address area to be refreshed, and outputs data to the address comparison circuit 117.

Address comparison circuit 117 uses clock 10
1, the data set in the refresh area setting register 116, and the address on the address bus 115 are input, and a refresh unnecessary area signal 118 is output. The refresh unnecessary area access signal 120 includes the external memory access signal 110 and the refresh unnecessary area signal 11.
This is a signal that is generated when 8 and 8 occur together.

The flip-flop 119 (hereinafter abbreviated as F.F) is a flip-flop circuit that is set when the overflow signal 105 is generated and reset when the refresh timing signal 121 is generated. The refresh timing signal 121 is the F. This signal is generated when the refresh unnecessary area access signal 120 is generated with F119 set.

The refresh timing signal 122 is F
．． With F119 set, overflow signal 1
This signal is generated when 05 occurs. The refresh control circuit 104 has a clock 101, a refresh timing signal 121, and a refresh timing signal 122.
and an external memory access signal 110, and outputs a refresh pulse 113 to a terminal 114.

Next, the operation will be explained. The address comparison circuit 117 is connected to the refresh area setting register 116.
The value set in is compared with the data on the address bus 115, and if the area does not correspond to the area to be refreshed, a refresh unnecessary area signal 118 is output.

[0028] Refresh-free area access signal 12
0 occurs when the external memory access signal 110 and the no-refresh area signal 118 are generated simultaneously, that is, when an external memory that does not require refresh is being accessed. Free running counter 102
When an overflow signal 105 is generated from F. F119
is set.

F. When the refresh unnecessary area access signal 120 is generated with F119 set, the refresh timing signal 121 is generated, and the refresh control circuit 104 sends the refresh pulse 113 to terminal 1.
Output to 14. At this time, refresh cycle signal 11
1 is not output. Therefore, external memory access is performed while outputting refresh pulses. At this time again F
．． F119 is reset.

[0030]F. Even if the refresh unnecessary area access signal 120 is generated with F119 reset,
Since the refresh timing signal 121 is not generated,
The refresh control circuit 104 generates a refresh pulse 11
3 and the refresh cycle signal 111 are not output.

F. When overflow signal 105 is generated with F119 set, that is, from the first overflow signal 105 generation to the next overflow signal 10
If no access to an external memory that does not require refresh occurs during the time period up to the occurrence of refresh timing signal 122, refresh timing signal 122 is generated. At this time, if the external memory access signal 110 is not generated or if it is generated simultaneously with the overflow signal 105, the refresh control circuit 104 outputs the refresh pulse 113 to the terminal 114, and the refresh cycle signal 111
Output. The bus control circuit 103 starts the next access after the refresh cycle signal 111 is released. At this time F. F119 is not reset.

In addition, the refresh timing signal 122
If the external memory access signal 110 is generated before the external memory access signal 110 is generated, the refresh control circuit 104 waits until the external memory access signal 110 is released, outputs the refresh pulse 113 to the terminal 114, and outputs the refresh signal 111. do. At this time also F. F119 is not reset.

FIG. 2 shows a timing chart in this embodiment. In this embodiment, unlike the conventional example, external memory access and refresh pulse output can be performed in parallel. Therefore, in this embodiment, the time loss described in the conventional example is eliminated.

Furthermore, even if there is no access to the memory that does not require refreshing for a long time, refreshing is performed reliably, so there is no fear that the data held in the pseudo SRAM will be destroyed.

Next, a second embodiment of the present invention will be explained using the drawings. FIG. 3 is a block diagram showing a second embodiment of the present invention.

First, the constituent elements will be explained. Clock 301, free running counter 302, overflow signal 305, address strobe signal 306, read signal 307, write signal 308, external memory access request signal 309, external memory access signal 310, refresh cycle signal 311, refresh pulse 3
13, terminal 314, address bus 315, refresh area setting register 316, address comparison circuit 317,
Refresh unnecessary area signal 318, F. The configurations of F319, refresh-free area access signal 320, and refresh timing signals 321 and 322 are the same as in the first embodiment, so their explanation will be omitted.

[0037] Refresh wait selection register 323
is a register that specifies the number of refresh cycles, and the refresh wait signal 324 is sent to the bus control circuit 303.
and is output to the refresh control circuit 304. The bus control circuit 303 inputs a clock 301, a refresh cycle signal 311, a refresh wait signal 324, an address strobe signal 306, a read signal 307,
Write signal 308, external memory access request signal 309
Output.

The refresh control circuit 304 receives a clock 301, an external memory access signal 310, a refresh timing signal 321, and a refresh timing signal 3.
22, input refresh wait signal 324, refresh cycle signal 311, refresh pulse 31
Outputs 3.

Next, the operation will be explained. F. F3
Even if the refresh unnecessary area access signal 320 is generated in a state where the refresh control circuit 19 is reset, the refresh control circuit 304 does not generate the refresh cycle signal 311 and the refresh pulse 313. At this time, the bus control circuit 303 uses the address strobe signal 306 and the read signal 3 in the same access cycle as normal memory access.
07, output the write signal 308.

F. When refresh unnecessary area access signal 320 is generated with F319 set, refresh control circuit 304 generates refresh pulse 313 and refresh cycle signal 311 with the number of refresh cycles specified by refresh wait selection register 323. At this time, the bus control circuit 303 sets the address strobe signal 306, read signal 30, and
7. Generate write signal 308.

F. When overflow signal 305 is generated with F319 set, refresh control circuit 304 generates refresh pulse 313 and refresh cycle signal 311 with the number of refresh cycles specified by refresh wait selection register 323. At this time, the bus control circuit 303 makes generation of the address strobe signal 306, read signal 307, and write signal 308 wait until the refresh cycle signal 311 is released.

That is, in the microcomputer of this embodiment, only the external memory access that generates the refresh pulse 313 extends the number of access cycles by the time required for refresh.

As a result, regardless of the speed of the pseudo SRAM, it is possible to use a memory that does not require refreshing, and has the effect that the operating speed of the microcomputer is hardly reduced.

In normal microcomputer processing,
Since the number of program fetches is much higher than the number of data accesses (fetching accounts for more than 80% of accesses to external memory), low-speed pseudo SRAM is used as data memory, and high-speed PROM is used as program memory. is often used to increase efficiency. In such a case, the microcomputer of this embodiment is particularly effective.

[0045]

As described above, according to the present invention, it is possible to execute refresh at a constant cycle and to perform external memory access in parallel even during refresh. As a result, it is possible to reliably refresh the pseudo SRAM, and the probability that external memory access is required to wait due to refresh is reduced, which has the advantage of speeding up instruction execution.

[0046]

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

[0047]

FIG. 2 is a timing chart of the first embodiment.

[0048]

FIG. 3 is a block diagram showing a second embodiment of the present invention.

[0049]

FIG. 4 is a timing chart of a second embodiment.

[0050]

FIG. 5 is a timing chart of a second embodiment.

[0051]

FIG. 6 is a block diagram showing a conventional example.

[0052]

FIG. 7 is a timing chart of a conventional example.

[0053]

FIG. 8 is a block diagram showing a conventional example.

[0054]

FIG. 9 is a timing chart of a conventional example.

[0055]

[Explanation of symbols]

101,301,601 Clock 102,30
2,602 Free running counter 103,303,603 Bus control circuit 104,
304, 604 refresh control circuit 105,
305, 605 Overflow signal 106, 30
6,606,802 Address strobe signal 107,307,607,803 Read signal 1
08,308,608,804 Write signal 10
9, 309, 609 External memory access request signal 110, 310, 610 External memory access signal 111, 311, 611 Refresh cycle signal 113, 313, 613, 814 Refresh pulse 114, 314, 614 Terminal 115, 315, 807 Address bus 116 ，
316 Refresh area setting register 117
, 317 Address comparison circuit 118, 318
Refresh unnecessary area signal 119, 319
F. F 120, 320 Refresh unnecessary area access signal 121, 122, 321, 322 Refresh timing signal 323 Refresh wait specification register 32
4 Refresh wait signal 801 Microcomputer 805 Address/data bus 806 Address latch 808 Address decoder 809 Refresh pulse generation circuit 810
PROM 811 Pseudo SRAM 812 PROM selection signal 813 Pseudo SRAM selection signal

Claims (4)

[Claims] 1. A first memory that requires refreshing, refresh means for supplying a refresh pulse to the first memory, a second memory that does not require refreshing, and the second memory is being accessed. A microcomputer comprising: means for detecting this; and means for permitting output of a refresh pulse to the first memory when the memory access is detected. 2. The microcomputer according to claim 1, further comprising a free running counter and a refresh pulse when an access to the second memory is detected after detecting an overflow of the free running counter. A microcomputer characterized by having means for generating. 3. The microcomputer according to claim 2, further comprising means for generating a refresh pulse when no access to the second memory is detected after detecting an overflow of the counter and before a next overflow occurs. A microcomputer characterized by having: 4. The microcomputer according to claim 2, further comprising means for selecting the number of refresh cycles for the memory that requires refreshing, and the number of access cycles for the memory that does not require refreshing and the number of refresh cycles. A microcomputer characterized in that either longer time is the number of memory access cycles when outputting a refresh pulse.