RU2020563C1 - Device for data distribution at parallel copying of data - Google Patents

Abstract

FIELD: computer technology. SUBSTANCE: device has comparison circuit, data memorizing unit, 2AND-OR-NOT gate, AND-NOT gate, OR gate and adder. EFFECT: improved speed of operation. 2 cl, 3 dwg

Description

 The invention relates to computer technology and is intended for the reproduction of data blocks often used in calculations by implementing new operations “write while reading” and “write in parallel”. The invention can be used, in particular, to speed up the operation of system block I / O with buffering, the essence of which is that when a request is received, for example, to output data, the latter are copied by the system to the system pool area, where they are formed into blocks output directly to the recorder. Moreover, the execution of user programs is delayed only while copying the output data to the system pool area. After that, the output data comes from the system pool to the output device at a speed determined by the speed of the output device and system subroutines. Thus, for the user, the process of copying data is limiting.

 A copying device is known (Yu. M. Kazarinov and others. The use of microprocessors and microcomputers in radio systems. M: Higher School, 1988, p. 50), containing a processor that provides processing of string variables, a system bus, address and data buses , and chip memory pages. This device provides copying the contents of part of the RAM into another part by initializing the cycle counter, downloading the start and end addresses of the copy, as well as directing the sequence of copying the original and copy memory areas, loading the copy command of the cycle type itself, addressing the memory cell of the original area, reading the contents of the cell of the original region to the processor register, the addressing of the cell of the copy region, the recording of the contents of the register of the processor in the cell of the copy region, modification and counter cycles check counter at zero cycles, modifications memory cell addresses of areas of the original and copies of the (end of cycle, the transition to the memory cell addressing cycle area of the original).

 A disadvantage of the known device is the slowness of copying data.

 The closest in technical essence to the claimed is a device for copying areas of random access memory through direct access to memory through a register consisting of a system bus, data bus, address bus, direct memory access controller and memory page chips (A. Zhuravsky and others. Organization of management of extended memory for the processor KR580IK80A. Microprocessor tools and systems, 1988, N 4, p. 87). This device is designed to operate the processor with a small number of address buses and large memory, and in it, unlike the device described above, the modification of the cycle counter, checking for zero cycle counter, modifications of the cell addresses of the original memory area and copies are carried out in hardware using the direct access controller memory.

 A disadvantage of the known device is the low speed of the operation of copying data in random access memory associated with the presence of an intermediate medium (processor register) between the original region and the copy region.

 Ideally, the data appearing on the data bus should be directly read into the copy area without using an intermediate medium. To do this, it is necessary to send a read signal and the address of the original to the original area, and a write signal and copy address to the copy area.

 However, the system usually has one address bus and, therefore, only one address can be set on it, at the same time, the read and write control lines are accessible to all units and the simultaneous supply of write and read signals is prohibited.

 The invention allows to place the original region and the region of the future copy in the same place of the address space, which makes it possible to use the same address to address both the original and the copy. In addition, the device ensures that the copy region interprets the read signal as a write signal, although it is possible to modify the device in which the original region treats the write signal as a read signal. Both versions of the device are equivalent in terms of the goal achieved.

 The aim of the invention is to increase performance.

 Figure 1 shows a block diagram of a device; figure 2 and 3 are timing diagrams of the functioning of the device during the process of writing while reading and writing in parallel.

 The invention allows copying using the new "write while reading" operation. In this case, the copy page is moved in the address space by changing the contents of the programmatically accessible registers of the beginning and end addresses of the page so that the beginning of the area to be copied coincides with the beginning of the area of RAM to be copied, and the end of the copied area is aligned with the end of the area , to which copying is performed, as a result, all addresses of the original cells are combined with the corresponding copy cells. After that, the "write while reading" mode is set in the copy page by changing the contents of the programmatically accessible page status register, as a result of which the copy page microcircuits perceive the read signal as a write signal. Following this, the original cells are sequentially read to the processor register or to the input-output device (a dummy input-output device with infinite speed can be used, i.e., only generating a confirmation signal). Simultaneously with reading each original cell, a hardware record is made to the copy cell at the same address, since their addresses are combined.

 After reading (and simultaneously copying) all the necessary memory cells, the copy page is moved to the desired area of the address space by changing the contents of the programmatically accessible address and start address register registers. If necessary, change the operating mode of the page, if necessary.

 The device allows for the rapid multiplication of information blocks, often used in calculations, in the RAM due to the implementation of the new operation “write in parallel”.

 Consider the simplest version of the reproduction of blocks of memory, when you want to write m bytes of information in N contiguous areas of memory located in N different pages. For this, N-1 areas of memory belonging to N-1 pages are combined in the address space with the first area of the first page, after which they are usually written to this area of the address space.

 A combination of the above operations is possible, i.e. "write in parallel while reading."

 The device (Fig. 1) contains the status register 1 included in the information storage unit with cells that allow or prohibit the operation of memory pages in reading, writing and writing modes when reading, logical elements 2 and 3, which ensure coordination and consistency of the read and write signals supplied directly to the memory chips, register 4 of the beginning of the page address included in the information storage unit, and register 5 of the end of the page address included in the information storage unit determining the location and size of the memory page ty in the address space, comparison circuit 6, determining the ownership of the address set on the address bus: address area of a given memory page, adder 7, which converts addresses coming from the address bus to addresses supplied to memory chips, logic element 8, which performs conversion two signals of the system interface "confirmation" (Acknowledgment) and "availability" (GT) in the signal "Confirmation to the central processor" (Acknowledgment of the CPU). Logical element 8 can be one for the entire computer (uniprocessor), all other elements form a logical circuit belonging to each page of memory.

 All described device registers are software accessible, each of them has its own address on the I / O bus.

 The device operates as follows.

 Initialization. In order to initialize the "write while reading" mode, the addresses are entered in address registers 4 and 5 so that the area to be copied is aligned in the address space with the area to be copied. In the register 1 of the page status - the future copy - bits are inserted that enable the "write while reading" mode and prohibit reading, while the state of the write enable cell does not matter and is set as necessary.

 If it is necessary to initialize the "write to parallel" operating mode, the areas of pages into which parallel writing will be performed are combined in the address space by entering the corresponding addresses into the programmatically accessible address registers of the beginning of 4 and the end of 5 pages. Then, a bit that permits writing is entered into the status register 1, while the state of the read permission and write permission cells when reading is not significant and is set as necessary.

 Read-write mode. After initialization, the processor or other device that controls the bus (SUSH), reads the area of memory to be copied. In this case, on the address bus 9 (SHA) (Fig. 1), the address of the corresponding memory cell from the desired area is set. At the end of the transient processes in the AL on the line 15 gating addresses 9ADR STB) establish a signal confirming the reliability of the address (figure 2). After the address is recognized by the pages of the copy and the original, they generate acknowledgment addressing signals ATPT1 and ATPT2 (Fig.2), and since the ATPT system line is made in the form of a mounting OR for negative signals, the ATPT confirmation system signal is set on the first of the ATPTF fronts 1 or Acknowledgment 2, informing the processor that the cell is addressed. After receiving the confirmation, the processor or the USH sets the read signal on the read line 10 (TH). Upon receipt of this signal, the original page exposes data on the data bus 11 (BD). After the data has been established and the transients are finished, the original page removes the HTLR 1 signal and sets the GT 1 signal, which, due to the fact that the 12 HT system line is made as a mounting OR for negative signals, puts the GT system line in a low level, informing the page a copy of the reliability of the data on the SD. In this case, the signal of readiness for the CPU is not received, since this line is not directly connected to the processor. Then the copy page writes data from the SD. At the end of the recording, the page-copy removes the signal ATS 2 from the system line 13 ATS and sets the signal GT 2. This triggers a logic element 8 and generates a signal ATS CPU on line 14 ATS CPU, informing the processor about the completion of copying, after which the processor or CAB the signals from the lines of ADR STB (15) and CT (10), and the pages of the copy and the original remove the signals GT 1 and GT 2, completing the cycle.

 Record in parallel mode. In this mode, the address of the desired cell is set on the SHA (9) and, at the end of the transient processes, the address gating signal is set on line 15 of the STB ADR, confirming the accuracy of the address (Fig. 3). After the address is recognized by pages, for example, the first (fast) and second (slow), the latter set the signals ATPT 1 and ATPT2. As a result, a signal informing the processor or SUSH about the reception of the address by the pages is set on the ATPT line 13. After that, the processor or the USH sets the write signal on line 16 of the RFP, informing the memory pages about the reliability of the data on the SD 11 and initiating the pages for the write operation. After the recording operation is completed with the first (fast) page, it removes the HTLR 1 signal and sets the signal of GT 1. After the recording operation is completed with the second (slow) page, it removes the HTLR signal 2 and sets the signal of GT 2. Removing the signal from the system of the 13 SLR line and setting the signal on line 13 of the GT, element 8 is triggered and a signal is established on the PWT line of the CPU, informing the processor or SUSH about the completion of the write operation of the slowest of the pages. Then the cycle ends similarly to the "write while reading" mode.

Claims (2)

 1. DEVICE FOR DATA DISTRIBUTION AT PARALLEL COPYING OF INFORMATION, containing a comparison circuit, the input of the address of the beginning of the page of the device connected to the first information input of the comparison circuit, characterized in that, in order to improve performance, an information storage unit is inserted into it, element 2I - OR - NOT, the AND element is NOT, the OR element and the adder, and the address input of the device is connected to the second information input of the comparison circuit and to the first information input of the adder, the second information and strobe the input input of which is connected respectively to the input of the address of the beginning of the page and to the input of the gate of the device address, the input of the gate of the address of the device is connected to the gate input of the comparison circuit, the third information input of which is connected to the input of the address of the end of the page of the device, the write permission and read read permission inputs are connected to the first the inputs of the first group of element 2I - OR - NOT and the element AND - NOT, respectively, the "Write when reading" input of the device is connected to the first input of the second group of element 2I - OR - NOT and to the second input of the AND element - NOT, the readiness output is connected to the ready output of the data buffering unit, the first input of the OR element and the second input of the second group of the 2I - OR - NOT element, the readiness confirmation output of the device is connected to the readiness confirmation output of the data buffering unit and the second input of the element OR, the output of which is connected to the output indicating the completion of the operation of the device, the recording input of the device is connected to the second input of the first group of element 2I - OR - NOT, the third input of the first group and the output of which are connected Accordingly, to the read input of the device and to the write input of the data buffering unit, the read input of the device is connected to the third input of the AND - NOT element, the output of which is connected to the read input of the data buffering unit, the sample input and address input of which are connected respectively to the output of the comparison circuit and to the output adder.  2. The device according to claim 1, characterized in that the data buffering unit contains RAM and two pulse shapers, the address input and the information input / output of the RAM being connected respectively to the address input and the information input / output of the unit, the recording input of the unit is connected to the input of the memory record and to the first inputs of the first and second pulse shapers, the block read input is connected to the second inputs of the first and second pulse shapers and to the read memory input, the sample input is and connected to the third input of the pulse and to the input of the sample RAM, the outputs of the first and second pulse generators are connected respectively to the outputs of availability and readiness acknowledgment block.

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