JPH09330305A - System-combined type device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a system-combined type device which makes it possible to confirm that an interruption request from a request source system is securely transmitted to a request destination system. SOLUTION: In the device where >=2 systems 1 and 2 are connected through a DPRAM 30 which, while sending an interruption request to the system 2 in response to writing from the system 1, resets the interruption request in response to reading from the system 2, the system 2 having accepted the interruption request performs writing to a specific bit of a specific address on the DPRAM 30 after the interruption request is reset.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system composite type device, and more particularly, to a system composite type device configured by connecting systems operating asynchronously via a storage means having a plurality of input / output ports. Regarding the improvement of the device.

[0002]

2. Description of the Related Art Some communication terminal devices include a plurality of systems that operate asynchronously, and these systems are connected to each other via a DPRAM. For example, when a multifunctional multifunction device is configured as a whole by adding an option board to the main body of the facsimile device,
There is a system in which the apparatus main body and each option board operate asynchronously, and there is a system in which the apparatus main body and the option board communicate with each other via the DPRAM provided in each option board.

Generally, when two systems are connected and used, if both systems are asynchronous systems having different data processing speeds, data transfer rates, etc., both systems are
A method of connecting via PRAM (dual port RAM) is known. The DPRAM is a storage unit including a plurality of input / output ports, and an input / output port is assigned to each system, and data is transferred between the systems via the DPRAM, so that asynchronous systems can be exchanged. Communication can be facilitated.

In particular, some DPRAMs can generate an interrupt signal by writing data to a specific address. When an interrupt is generated from one system (request source) to the other system (request destination) using such a DPRAM, a command, which is the request content from the request source, is sent between these systems.
It becomes necessary to deliver the status of the requestee.

For example, the requesting system is a DPRAM
The interrupt factor can be transmitted to the request destination system by writing the data indicating the interrupt factor to the above specific address and reading the data by the request destination system receiving the interrupt signal. However, whether the requested system has accepted the interrupt signal,
Further, the requesting system could not confirm whether or not the requesting system has read the data of the interrupt factor from the DPRAM.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and is provided with two or more systems connected via a storage means, and an interrupt request from a requesting system is requested. It is an object of the present invention to provide a system composite type device capable of confirming that the request has been reliably transmitted to the previous system.

[0007]

According to another aspect of the present invention, there is provided a system composite type apparatus according to the present invention, wherein two or more systems are connected via a storage means, and the storage means is connected to one another by writing from one system. Device which cancels the interrupt request by reading from the other system while making an interrupt request to the other system, the other system that receives the interrupt request specifies the storage means after canceling the interrupt request. It is configured to write to an address.

Here, the system means a group of circuits having at least a signal bus therein,
It does not matter whether the coupling relationship between the systems is fixed (whether it is removable or not). That is, each system can be configured as an independent device each having a housing, or as an option board or the like which can be detachably mounted in the housing, but a circuit portion occupying a part of the LSI on the circuit board. Can also be configured as. In addition, with specific address,
It means one or two or more addresses on the storage means which are predetermined.

A system composite type apparatus according to a second aspect of the present invention is the system composite type apparatus according to the first aspect, wherein the storage means is based on the writing after cancellation of the interrupt request. It is configured to issue an interrupt request to one of the above systems. In the system composite type apparatus according to the third aspect of the present invention, two or more systems are connected via a storage means, and the storage means makes an interrupt request to the other system by writing from one system. A device for canceling an interrupt request by reading from the other system, and a confirmation interrupt circuit for making an interrupt request to the one system based on the interrupt request canceling operation by the other system. It is configured with.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an example of the configuration of a system composite type apparatus according to the present invention described in claim 1. This system composite type device is a DPR system 1 and system 2
It is configured to be connected via the AM 30. The system 1 and the system 2 are systems that operate without being synchronized with each other. The DPRAM 30 is a storage unit having two input / output ports and is a storage unit that can write and read from the same address at any port. Therefore, the system 1 and the system 2 connected to the respective input / output ports of the DPRAM 30 can read / write the DPRAM 30 independently of each other, and data can be transferred without synchronization.

In this system composite type device, the system 1
Is transmitted to the system 2 as an interrupt request. This interrupt request is sent to the DPRAM 3 of the system 1.
This is performed by writing data to 0. That is, in the DPRAM 30, a specific address is predetermined as the interrupt generation address rA, and the system 1 writes the DPRAM 30 by designating the interrupt generation address rA. And an interrupt signal is output. In this way, the request from the system 1 is transmitted to the system 2.

The system 2, which has received the interrupt signal,
Cancel the interrupt. The release of the interrupt means stopping the output of the interrupt signal, and the system 2 stops the output of the interrupt signal from the DPRAM 30 by designating the interrupt generation address rA and reading the data from the DPRAM 30. be able to. Therefore, when the system 1 requests an interrupt, if a command such as an interrupt factor from the system 1 is written in the interrupt generation address rA, the command is transmitted to the system 2 by reading when the interrupt is released.

Further, the system 2 in which the interrupt is released
Writes data indicating that the data has been received on the DPRAM 30. In this data writing, the interrupt generation address rA is designated, and a predetermined one bit of the data of the address, for example, the least significant bit (L
This is an operation of writing "1" in SB). The system 1 that has issued the interrupt request then periodically reads the interrupt generation address rA, and if the value of the least significant bit is monitored, then it is confirmed whether or not the system 2 has accepted the interrupt request. be able to. However, in order to make such a determination, it is premised that the system 1 writes "0" in the least significant bit of the interrupt generation address rA at the time of the interrupt request.

FIG. 2 is a flow chart showing an example of the basic operation of the system composite type apparatus shown in FIG. This figure is a diagram showing the respective operations of the system 1, the DPRAM 30, and the system 2 together with the corresponding relationship in time series.
00 to 202 are flowcharts for the system 1, 210 to 214 are flowcharts for the DPRAM 30, and 220 to 222 are flowcharts for the system 2. Moreover, (1) to FIG.
(5) corresponds to (1) to (5) of FIG. 1, respectively.

When a command transmission request to the system 2 is generated in the system 1 (200), the system 1 writes a command in the interrupt generation address rA of the DPRAM 30 (201). The DPRAM 30 monitors writing by the system 1 to the interrupt generation address rA (210), and if there is writing, starts outputting an interrupt signal to the system 2 (211). The system 2 is monitoring the interrupt signal, and if the interrupt signal is detected, the interrupt process is started (220).

In the interrupt processing of the system 2, first, in order to cancel the interrupt, the interrupt generation address rA of the DPRAM 30 is read (221). The DPRAM 30 is
The system 2 monitors the reading of the interrupt generation address rA (212). If the reading is made, the interrupt is released and the output of the interrupt signal to the system 2 is stopped (213).

Finally, the system 2 writes "1" in the least significant bit (LSB) of the interrupt generation address rA (2).
22). On the other hand, the system 1 periodically writes the command to the DPRAM 30 (201) and then periodically
The interrupt generation address rA of is read (202),
By confirming that the least significant bit has changed to “1”, it is possible to confirm that the request of the system 1 has been transmitted to the system 2.

Next, FIG. 3 shows an example of the configuration of the system composite type apparatus according to the present invention as defined in claim 2. This system composite apparatus is configured by connecting the system 1 and the system 2 via the DPRAM 31 like the system composite apparatus of FIG. 1, and the system 1 and the system 2 are systems that operate asynchronously with each other. It is connected to each port of the DPRAM 31 having two input / output ports.

In this DPRAM 31, two different interrupt generation addresses rA1 and rA2 are predetermined. If data is written from the system 1 by designating the first interrupt generation address rA1, the DPRAM 31 outputs an interrupt signal to the system 2. On the other hand, if the second interrupt generation address rA2 is designated and data is written from the system 2, the DPRAM 31 outputs an interrupt signal to the system 1.

The interrupt from the DPRAM 31 to the system 2 causes the system 2 to generate the first interrupt generation address rA.
1 is released by reading the data from the DPRAM 31, and the interruption to the system 1 causes the system 1 to designate the second interrupt generation address rA2,
It is canceled by reading the data from the RAM 31.

That is, the interrupt to the system 2 corresponds to the first interrupt generation address rA1, is generated by the write from the system 1, and is released by the read from the system 2. On the other hand, the interrupt to system 1 is
It corresponds to the second interrupt generation address rA2, is generated by writing from the system 2, and is canceled by reading from the system 1.

FIG. 4 is a flow chart showing an example of the basic operation of the system composite type apparatus shown in FIG. This figure is a diagram showing the respective operations of the system 1, the DPRAM 31, and the system 2 together with the corresponding relationship in time series.
00 to 402 are flowcharts for the system 1, 410 to 417 are flowcharts for the DPRAM 31, and 420 to 422 are flowcharts for the system 2. Moreover, (1) to FIG.
(6) corresponds to (1) to (6) in FIG. 3, respectively.

When a command transmission request to the system 2 is generated in the system 1 (400), the system 1 writes the command in the first interrupt generation address rA1 of the DPRAM 31 (401). The DPRAM 31 monitors writing by the system 1 to the first interrupt generation address rA1 (410), and if there is writing, starts outputting an interrupt signal to the system 2 (411). The system 2 monitors the interrupt signal, and if the interrupt signal is detected, the interrupt process is started (420, 42).
1).

In the interrupt processing of the system 2, first, in order to cancel the interrupt, the first interrupt generation address rA1 of the DPRAM 31 is read (421). DPRAM
31 is the first interrupt generation address rA by the system 2
The reading of 1 is monitored (412), and if there is reading, the output of the interrupt signal to the system 2 is stopped (413).

Next, the system 2 writes confirmation data indicating that the interrupt is accepted to the second interrupt generation address rA2 of the DPRAM 31 (422). DPRAM3
1 is the second interrupt generation address rA2 by the system 2
Is being monitored (414), and if there is a write, output of an interrupt signal to the system 1 is started (415). The system 1 is monitoring the interrupt signal (402) and starts the interrupt process if the interrupt signal is detected.

In the interrupt processing of the system 2, in order to cancel the interrupt, the second interrupt generation address rA2 of the DPRAM 31 is read (403). DPRAM31
Monitors the reading of the second interrupt occurrence address rA2 by the system 1 (416), and stops the output of the interrupt signal to the system 1 if there is a reading (4).
17). The system 1 can confirm that its request has been transmitted to the system 2 based on the read confirmation data from the system 2. Further, by making the confirmation data information including the status of the system 2 etc., it is possible to make a response from the system 2 to the system 1.

Next, FIG. 5 shows an example of the configuration of the system composite type apparatus according to the third aspect of the present invention. This system composite type device further includes a confirmation interrupt circuit 4 in the system composite type device of FIG. 1, and is configured by connecting the system 1 and the system 2 via the DPRAM 30 and the confirmation interrupt circuit 4. . The interrupt confirmation circuit 4 monitors the read operation from the system 2 to the DPRAM 30, and if there is a read to rA at the interrupt generation address, generates an interrupt to the system 1 and performs a predetermined read operation from the system 1. If it is monitored and read, the interrupt is released and the interrupt signal to the system 1 is stopped.

FIG. 6 is a diagram showing an example of the configuration of the confirmation interrupt circuit 4, which is composed of an address decoder 40, logical operation circuits 41 and 42, and a flip-flop 43. The address decoder 40 is a circuit that decodes the address output by the system 2 and outputs the output signal DE at a high level when it matches the interrupt generation address rA. The logical operation circuit 41 is a 3-input AND circuit, and DPRA
The interrupt signal INT2 from M30, the read signal RD2 from the system 2 and the decode signal DE are input. All of these signals are positive logic signals,
The logic operation circuit 41 outputs a high-level signal only when the interrupt signal INT2 is output from the DPRAM 30 and only when the system 2 reads the interrupt generation address rA.

The logical operation circuit 42 is a 2-input NAND circuit, to which the read signal RD1 and the chip select signal CS from the system 1 are input. All of these signals are positive logic, and the chip select signal CS
Is given as a result of decoding the address from the system 1 and can be matched with the interrupt generation address rA of the DPRAM 30, for example. Therefore, the low-level signal is output from the logical operation circuit 42 only when the system 1 performs a predetermined read.

The flip-flop 43 is a D flip-flop with a reset terminal, the D input terminal is fixed at a high level, the output signal DE of the logical operation circuit 41 is input to the clock input terminal, and the reset input terminal is input. The output signal of the logical operation circuit 42 is input, and its output terminal Q
Is output as an interrupt signal INT1 to the system 1.

Therefore, when the interrupt signal INT2 is being output from the DPRAM 30, the system 2 is in the DPRAM.
When the interrupt occurrence address rA of 30 is read, the output signal INT1 of the flip-flop 43 changes to high level, while when the system 1 performs a predetermined read,
The output signal INT1 changes to low level. FIG. 7 is a flowchart showing an example of the basic operation of the system composite type apparatus shown in FIG. This figure shows System 1 and D
FIG. 70 is a diagram showing each operation of the PRAM 30, the confirmation interrupt circuit 4, and the system 2 together with a time-series correspondence relationship.
0 to 704 are flowcharts for the system 1, 710 to 714 are flowcharts for the DPRAM 30 and the confirmation interrupt circuit 4, and 720 to 721 are flowcharts for the system 2. Further, (1) to (4) of FIG. 7 are (1) to (4) of FIG. 5, respectively.
It corresponds to.

When a command transmission request is issued to the system 2 in the system 1 (700), the system 1 writes the command in the interrupt generation address rA of the DPRAM 30 (701). The DPRAM 30 monitors the writing to the interrupt generation address rA by the system 1 (710), and if there is the writing, starts the output INT2 of the interrupt signal to the system 2 (711). The system 2 monitors the interrupt signal INT2, and if the interrupt signal is detected, the interrupt process is started (720).

In the interrupt processing of the system 2, the interrupt is released. The interrupt is released by reading the interrupt generation address rA of the DPRAM 30 (72
1). The DPRAM 30 and the confirmation interrupt circuit 4 both monitor the reading of the interrupt occurrence address rA by the system 2 (712). If there is a read, the DPRAM 3
0 stops outputting the interrupt signal INT2 to the system 2, and the confirmation interrupt circuit 4 starts outputting the interrupt signal INT1 to the system 1 (713).

The system 1 monitors the interrupt signal INT1 and starts the interrupt process if the interrupt signal is detected. In the interrupt process of the system 1, a predetermined read is performed to cancel the interrupt (703). The confirmation interrupt circuit 4 monitors a predetermined read by the system 1. If there is a read, the confirmation interrupt circuit 4 releases the confirmation interrupt and stops the output of the interrupt signal INT1 to the system 1 (71).
4).

The present invention can also be applied to, for example, a communication terminal device provided with two or more systems that operate without being synchronized with each other, and these systems are connected via DPRAM. That is, by configuring each system of the communication terminal device as the system 1 or the system 2 in FIG. 1, 3 or 5, the request from one system to the other system is performed by the method shown in FIG. 2, 4 or 7. Can be reliably transmitted as an interrupt.

[0036]

According to the system composite apparatus of the present invention, when a request is transmitted from one system to another system, the requesting system confirms that the request has been transmitted to the requested system. You can Therefore, requests can be exchanged quickly and reliably between systems that are not synchronized with each other.

Further, according to the present invention as set forth in claim 2 or 3, since the request source system confirms the transmission by receiving the interrupt signal, the processing capability of the request source is not lowered.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration example of a system composite type apparatus according to the present invention as set forth in claim 1;

2 is a flow chart showing an example of a basic operation of the system composite type apparatus shown in FIG.

FIG. 3 is a diagram showing an example of the configuration of a system composite type apparatus according to the present invention as defined in claim 2;

4 is a flowchart showing an example of a basic operation of the system composite type apparatus shown in FIG.

FIG. 5 is a diagram showing a configuration example of a system composite type apparatus according to the present invention as defined in claim 3;

FIG. 6 is a diagram showing a configuration example of the confirmation interrupt circuit shown in FIG.

7 is a flowchart showing an example of a basic operation of the system composite type apparatus shown in FIG.

[Explanation of symbols]

 1 ... One system 2 ... The other system 30, 31 ... Storage means 4 ... Confirm interrupt circuit rA, rA2 ... Specific address

Claims (3)

[Claims] 1. Two or more systems are coupled via a storage means, said storage means making an interrupt request to another system by writing from one system, and interrupting by reading from the other system. In the device that releases the request, the other system that has received the interrupt request is
A system composite type device characterized in that writing is performed to a specific address on the storage means after cancellation of an interrupt request. 2. The system composite type apparatus according to claim 1, wherein said storage means issues an interrupt request to said one system based on said writing after cancellation of the interrupt request. . 3. Two or more systems are coupled via a storage means, said storage means making an interrupt request to another system by writing from one system, and interrupting by reading from the other system. A device for canceling a request, comprising a confirmation interrupt circuit for issuing an interrupt request to the one system based on an operation of canceling an interrupt request by the other system, and a system composite type device. .