JP2015035024A - Communication device, communication system, and communication processing program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a communication device, a communication system, and a communication processing program that can reduce a load on a central processing unit compared with the case where interrupt processing is performed after waiting for completion of data update in a storage unit.SOLUTION: A SerDes control unit 22 of a main control device 12 comprises a packet receiving unit 41, a copy register group control unit 42, an interrupt control unit 44, and a register 46. The register 46 has stored, as a reference data storage address, an address where reference data which a CPU 20 refers to in interrupt processing is written in the copy register group 24 by the CPU 20 in advance. When the packet receiving unit 41 receives an interrupt packet, the interrupt control unit 44 compares a copy register group address with the reference data storage address at a timing based on a copy register group write signal and the timing of reception of the interrupt packet data, and if they accord, the interrupt control unit 44 notifies the CPU 20 of an interrupt.

Description

  The present invention relates to a communication device, a communication system, and a communication processing program.

  In Patent Document 1, at least one device is connected, and each of the data for controlling the driving of the device and the data indicating the state of the device is stored in the first storage unit and the first storage unit. A device control unit having a reading and transmitting unit for reading and transmitting each data, a central processing unit, a second storage unit, and a writing unit for writing the data transmitted from the device control unit into the second storage unit A full-duplex serial bus that connects the main control unit and the device control unit, and the reading and transmitting means and the writing means are connected to the central processing unit. A control device is described that operates so that each data stored in the first storage unit is read out, transmitted, and written into the second storage unit at a period equal to or less than a count period of a system timer serving as an operation reference. ing.

Japanese Patent Application No. 2012-135920

  The present invention relates to a communication device, a communication system, and a communication process that can reduce the load on the central processing unit as compared with the case where the central processing unit waits until the data update of the storage unit is completed and performs the interrupt processing. The purpose is to provide a program.

  In order to achieve the above object, the communication device of the present invention is configured such that the central processing unit performs an interrupt process based on packet data transmitted from another communication device and an interrupt packet transmitted from the other communication device. From the writing means for writing the reference data to be referred to in the storage section, the storage means for storing the address of the storage section to which the other reference data is written by the writing means, and the other communication device When the writing address of the storage unit to which the writing unit has written the reference data based on the transmitted interrupt packet matches the address of the storage unit stored in the storage unit, Interrupt control means for performing control for notifying the central processing unit of the interrupt.

  Further, the interrupt control means of the communication device according to the present invention is configured such that when the central processing unit performs the interrupt processing without referring to the reference data stored in the storage unit, the write address Control may be performed to notify the central processing unit of an interrupt regardless of whether or not the address of the storage unit stored in the storage means matches.

  Further, the interrupt control means of the communication device of the present invention comprises a comparison circuit for comparing the write address with the address of the storage unit stored in the storage means, and based on the comparison result of the comparison circuit It is preferable to perform control for notifying the central processing unit of an interrupt.

  The communication system of the present invention includes a slave communication device and the communication device of the present invention that receives packet data transmitted from the slave communication device by serial communication.

  The communication processing program of the present invention is for causing a computer to function as at least one of writing means and interrupt control means of the communication apparatus of the present invention.

  According to the first, fourth, and fifth aspects of the present invention, the load on the central processing unit is reduced as compared with the case where the interruption process is performed after the data update in the storage unit is completed. be able to.

  According to the second aspect of the present invention, the addition of the central processing unit can be further reduced as compared with the case where the present configuration is not provided.

  According to the third aspect of the present invention, the addition of the central processing unit can be further reduced as compared with the case where the comparison is not performed by the comparison circuit.

1 is a configuration diagram illustrating a schematic configuration of an example of an image forming apparatus according to an exemplary embodiment. It is a block diagram which shows an example of a structure of the SerDes control part 22 regarding the interruption notification process function of the main controller of this Embodiment. It is a block diagram which shows a specific example of the interruption control part of this Embodiment. It is a block diagram which shows the other specific example of the interruption control part of this Embodiment. It is a flowchart showing the whole flow of an example of the interruption notification process performed in the SerDes control part of the main control apparatus of this Embodiment. It is a timing chart of an example of the interrupt notification process performed in the SerDes control part of the main controller of this embodiment. It is explanatory drawing for demonstrating an example of the address stored in the register | resistor of this Embodiment. It is a time chart of an example when the copy register group address when the SerDes control unit of the main controller of the present embodiment receives the interrupt packet is less than the reference data storage address. It is a time chart of an example when the copy register group address when the SerDes control unit of the main controller of the present embodiment receives the interrupt packet is equal to or greater than the reference data storage address. 10 is a time chart of an example when the copy register group address is “0” when the SerDes control unit of the main control device of the present embodiment receives an interrupt packet;

  Hereinafter, an example of an embodiment of the present invention will be described in detail with reference to the drawings.

  First, an image forming apparatus provided with a control apparatus having a main control apparatus which is a communication apparatus of the present invention and an apparatus control apparatus which is another communication apparatus or a sub control apparatus of the present invention will be described. FIG. 1 is a configuration diagram illustrating a schematic configuration of an example of the image forming apparatus 10. The image forming apparatus 10 includes a control device 11 to which a main control device 12 and a device control device 14, which are communication devices, are connected via a serial bus 40, and a device group 16 including various devices connected to the device control device 14. It has. The serial bus 40 is a full-duplex transmission line provided with a signal line Tx for transmission and a signal line Rx for reception when viewed from the main controller 12.

  Each device included in the device group 16 is a device for forming an image. For example, a motor that rotates a photosensitive member or a developing roll, a sensor for detecting paper, or a sensor for detecting toner concentration Etc. are included. Here, the image forming apparatus 10 has been described as an image forming apparatus that forms an image by an electrophotographic method, but may be an image forming apparatus that forms an image by an inkjet method.

  The main control device 12 has a function of controlling the entire image forming apparatus 10 and the device control device 14. The main controller 12 includes a CPU (Central Processing Unit) 20, a serializer / deserializer controller 22 (hereinafter referred to as “SerDes controller 22”), and a copy register group 24.

  The CPU 20 controls the entire image forming apparatus 10 and the device control apparatus 14 by executing a program stored in a non-volatile storage unit (not shown). The storage unit for storing a program executed by the CPU 20 may be an HDD (Hard Disk Drive), a flexible disk, a DVD (Digital Versatile Disk), a magneto-optical disk, a USB (Universal Serial Bus) memory, or the like. . In addition, the storage unit may be a storage medium of another device connected via a communication IF (Interface) (not shown).

  The CPU 20 is connected to the SerDes control unit 22 via the CPU bus 26. The CPU bus 26 is a parallel bus provided with a plurality of signal lines.

  When the SerDes control unit 22 receives information (parallel signal) to be transmitted from the CPU 20 to the device control device 14 via the CPU bus 26, the SerDes control unit 22 converts the received parallel signal into packets, converts each packet into a serial signal, and converts the serial bus 40 to the serial bus 40. Is transmitted to the device control apparatus 14 via. When the SerDes control unit 22 receives a serial packet from the device control device 14 via the serial bus 40, the SerDes control unit 22 converts the received packet into a parallel packet, decodes the converted parallel packet, Data included in the packet is extracted.

  The copy register group 24 includes a memory including a plurality of registers (storage areas). The stored contents of each register of the input / output control register group 32 included in the device control device 14 are copied to the copy register group 24. Here, copying refers to reading out data stored in the register from the input / output control register group 32 and transmitting the read data to the main controller 12 via the serial bus 40 to each register of the copy register group 24. A series of processing to write.

  The device control device 14 includes a serializer / deserializer controller 30 (hereinafter referred to as “SerDes controller 30”), an input / output control register group 32, and a drive / receiver circuit 34.

  When the SerDes control unit 30 receives a serial packet from the main controller 12 via the serial bus 40, the SerDes control unit 30 converts the received packet into a parallel packet, decodes the parallel packet, and includes the packet in the packet. Data to be retrieved. In addition, the SerDes control unit 30 packetizes information (parallel signal) to be transmitted to the main controller 12, converts each packet into a serial signal, and transmits the serial signal to the main controller 12 via the serial bus 40.

  The input / output control register group 32 includes a memory including a plurality of registers (storage areas). The plurality of registers of the input / output control register group 32 includes an input register and an output register. Data indicating the state of each device is written in the input register. In the output register, data for controlling each device transmitted from the CPU 20 of the main controller 12 is written. The input / output control register group 32 includes a register to which data indicating the occurrence of an interrupt is written and a register to which data indicating an interrupt factor is written.

  The contents stored in each register of the input / output control register group 32 are copied to the copy register group 24 of the main controller 12 as described above. In the present embodiment, the CPU 20 can refer to the same data as the data written to the input / output control register group 32 by reading the data copied to the copy register group 24. In addition, in the present embodiment, the CPU 20 can also read out and acquire data written in the input / output control register group 32 via the serial bus 40. In the present embodiment, the memory size of the copy register group 24 and the memory size of the input / output control register group 32 are equal to each other, and when copying from the input / output control register group 32 to the copy register group 24, It is assumed that the data read from the input / output control register group 32 is written to the register of the copy register group 24 corresponding to the register of the input / output control register group 32 in which the data is stored.

  The drive / reception circuit 34 is connected to each device of the device group 16 constituting the image forming apparatus 10. When data for controlling the device is written in the output register of the input / output control register group 32, the drive / reception circuit 34 outputs a drive signal corresponding to the data to the device corresponding to the output register. The device is driven according to the output drive signal. When a signal indicating the state of the device is input from the connected device, data corresponding to the signal is written into a data input register indicating the state of the device. For example, if the device is a sensor, the data indicating the state may be data indicating the detection result of the sensor. Further, for example, when the device is a motor, it may be data indicating the rotation state of the motor.

  The CPU 20 that controls the entire image forming apparatus 10 grasps the state of the device from the data written in the input register, and controls the drive of each device by writing control data in the output register.

  When the SerDes control unit 22 of the main control device 12 of the present embodiment receives an interrupt packet notifying the occurrence of an interrupt from the device control device 14, it monitors the update status of the copy register group 24 and sends it to the CPU 20. Processing for notifying interruption (hereinafter referred to as “interrupt notification processing”) is performed. For example, in the present embodiment, the interrupt packet is transmitted from the device control apparatus 14 to the main control apparatus 12 when the capture of a predetermined number of data is completed.

  The functions and operations related to the interrupt notification process will be described in detail.

  The SerDes control unit 30 of the device control device 14 generates an address from which data is read when data is read from the input / output control register group 32 and copied to the copy register group 24, and is output to an address counter (not shown). To do. Copying of data to the copy register group 24 is performed by reading data of a predetermined size from the input / output control register group 32 and sequentially transferring the data to the main controller 12, so that data of a predetermined size is stored. Is read from the input / output control register group 32, an address incremented by the size is output. The address counter is reset when reading of data from the input / output control register group 32 for copying to the copy register group 24 is completed or reading of data is started.

  The SerDes control unit 30 of the device control device 14 reads the data from the input / output control register group 32 and copies the data written in each register of the input / output control register group 32 to the copy register group 24. A packet to be written in the register group 24 (hereinafter referred to as “copy packet”) is generated. The copy packet is serially converted by a parallel-serial conversion circuit (not shown) and transferred to the main controller 12 via the serial bus 40.

  In addition, when data indicating the occurrence of an interrupt is written in the interrupt register of the input / output control register group 32, the SerDes control unit 30 of the device control device 14 generates an interrupt packet that notifies the occurrence of the interrupt. The generated interrupt packet is converted into a serial packet by a parallel-serial conversion circuit (not shown) and transmitted to the main controller 12.

  When receiving the interrupt packet, the SerDes control unit 22 of the main control device 12 generates an interrupt notification signal for notifying the interrupt. When the CPU 20 receives the interrupt notification signal, the CPU 20 grasps that the interrupt has occurred, reads data indicating the interrupt factor from the copy register group 24, and performs processing corresponding to the interrupt factor (interrupt process).

  FIG. 2 shows an example of the configuration of the SerDes control unit 22 related to the interrupt notification processing function of the main control device 12. The SerDes control unit 22 of this embodiment includes a packet reception unit 41, a copy register group control unit 42, an interrupt control unit 44, a register 46, and a CPU bus 47. In FIG. 2, for convenience of illustration, the copy register group 24 is shown in the SerDes control unit 22, but actually, the copy register group 24 is provided outside the SerDes control unit 22.

  The packet receiving unit 41 has a function of converting the serial format packet received from the device control apparatus 14 into a parallel format and extracting the data. The packet receiving unit 41 includes a serial-parallel conversion circuit (deserializer), a buffer, and a packet decoding circuit (not shown). The serial-parallel conversion circuit has a function of converting a serial packet received from the device control device 14 via the serial bus 40 into a parallel packet. The buffer has a function of temporarily storing a parallel packet converted by the serial / parallel conversion circuit. The packet decoding circuit has a function of decoding a parallel packet temporarily stored in a buffer and extracting data contained in the packet.

  When receiving the copy packet, the packet receiving unit 41 outputs the copy register group packet data extracted from the copy packet to the copy register group control unit 42. Further, when receiving the interrupt packet, the packet receiving unit 41 outputs the interrupt packet data to the interrupt control unit 44.

  The copy register group control unit 42 has a function of performing control for writing copy register group packet data to the copy register group 24. The copy register group control unit 42 outputs a copy register group address (a signal indicating the address) and a copy register group write signal to the copy register group 24 and the interrupt control unit 44. The copy register group address is a signal indicating a write location (address) of the copy register group packet data. The copy register group write signal is a signal indicating whether or not writing to the copy register group is permitted. In the copy register group 24, the copy register group packet data is written to the copy register group address designated by the copy register group control unit 42 at a timing based on the copy register group write signal.

  The register 46 is connected to the CPU 20 and the CPU bus 47 via a CPU bus interface (not shown).

  In the register 46, the storage location (reference data storage address) of the copy register group 24 in which reference data to be referred to when the CPU 20 performs an interrupt process is written (stored) is at a predetermined timing such as when the system is started. It is set by the CPU 20 in advance. The reference data storage address is output to the interrupt control unit 44.

  The interrupt control unit 44 compares the copy register group address with the reference data storage address at the timing according to the copy register group write signal and the interrupt packet data, and outputs an interrupt notification to the CPU 20 when they match. Have. The interrupt control unit 44 of the present embodiment is realized by hardware resources such as a comparison circuit. FIG. 3 shows a block diagram of a specific example of the interrupt control unit 44 of the present embodiment.

  The interrupt control unit 44 illustrated in FIG. 3 includes a sequencer 50 and a comparator 52.

  The sequencer 50 receives interrupt packet data and a copy register group write signal. When the interrupt packet data is input, the sequencer 50 outputs an address comparison valid signal for validating (comparing) the comparison of the comparator 52 to the comparator 52.

  The comparator 52 is a comparison circuit, compares the copy register group address with the reference data storage address based on the address comparison valid signal, and outputs the comparison result (see “Comparison match” in FIG. 3) to the sequencer 50. To do.

  The sequencer 50 outputs an interrupt notification to the CPU 20 when the copy register group address matches the reference data storage address based on the comparison result. If the copy register group address matches the reference data storage address, an address comparison valid signal for invalidating the comparison of the comparator 52 (ending the comparison) is output to the comparator 52.

  The configuration of the interrupt control unit 44 is not limited to that shown in FIG. FIG. 4 shows a configuration diagram of another specific example of the interrupt control unit 44 of the present embodiment.

  The interrupt control unit 44 illustrated in FIG. 4 includes a latch 54 and a comparator 56.

  The latch 54 receives interrupt packet data and an interrupt notification. The latch 54 outputs an address comparison valid signal for validating (comparing) the comparison of the comparator 56 to the comparator 56 during the period from the input of the interrupt packet data to the output of the interrupt notification.

  The comparator 56 includes a comparison circuit, and compares the copy register group address with the reference data storage address at a timing based on the address comparison valid signal. When the copy register group address matches the reference data storage address, the comparator 56 outputs an interrupt notification to the CPU 20 at a timing based on the copy register group write signal.

  Next, the interrupt notification processing operation in the SerDes control unit 22 of the present embodiment will be described in detail. FIG. 5 is a flowchart showing the overall flow of an example of the interrupt notification process. FIG. 6 shows a timing chart of an example of the interrupt notification process.

  In this embodiment, the CPU 20 stores in advance the address of the copy register group 24 to which the reference data referred to by the CPU 20 in the interrupt processing is written for each interrupt factor (or packet type) in the register 46. Keep it. FIG. 7 shows an example of addresses stored in the register 46. As shown in FIG. 7, in the present embodiment, the storage unit 46A of the register 46 stores the setting regarding whether or not to notify the interrupt after waiting for the update (write end) of the copy register group 24. deep. For example, when the main control device 12 receives an interrupt packet regarding data such as measurement values of the device group 16 from the device control device 14, the CPU 20 does not refer to the reference data written in the copy register group 24. Perform interrupt processing. Therefore, in such a case, the interrupt is notified without waiting for the update of the copy register group 24.

  In addition, the storage unit 46B of the register 46 stores, for each interrupt factor, a copy register group address for storing data necessary for processing the interrupt factor. In the specific example shown in FIG. 7, a case is shown in which copy register group addresses corresponding to 14 types of interrupt factors from interrupt factor 0 to interrupt factor 13 are stored.

  The interrupt notification process is started when the packet receiving unit 41 of the SerDes control unit 22 receives packet data.

  First, in step S100, it is determined whether the received packet is an interrupt packet. If the packet is not an interrupt packet, such as a copy packet, the CPU 20 is not notified of the interrupt, and the process is terminated. On the other hand, if it is an interrupt packet, the process proceeds to step S102.

  In step S102, it is determined whether or not the CPU 20 refers to the reference data of the copy register group 24 in the interrupt process. When not referring, it progresses to step S110. On the other hand, when referring, it progresses to step S104.

  In step S104, comparison between the copy register group address and the reference data storage address is started. As shown in the timing chart of FIG. 6, when the interrupt packet data is received, the interrupt control unit 44 compares the copy register group address with the reference data storage address to compare the H level (valid) address. The valid signal is output to an internal comparator (see the comparator 52 in FIG. 3 and the comparator 56 in FIG. 4).

  In the next step S106, the interrupt control unit 44 compares the copy register group address with the reference data storage address corresponding to the interrupt factor of the received interrupt packet, and determines whether or not they match. FIG. 6 shows a case where the reference data storage address is “N” as a specific example.

  If they do not match, the comparison between the copy register group address and the reference data storage address is repeated. On the other hand, if they match, the process proceeds to step S108. In the next step S108, the interrupt control unit 44 sends an L level (invalid) address comparison valid signal to the internal comparator (comparison in FIG. 3) so as to finish the comparison between the copy register group address and the reference data storage address. Output to the comparator 52 and the comparator 56 in FIG. In the next step S110, the interrupt control unit 44 notifies the CPU 20 of the interrupt, and then ends the present process.

  As shown in the timing chart of FIG. 6, the interrupt control unit 44 of the present embodiment receives a copy register group write signal when the copy register group address matches the reference data storage address “N” (copy register group signal). At the timing when the group write signal falls from the H level to the L level, the CPU 20 is notified of the interrupt.

  More specifically, the timing at which the interrupt control unit 44 notifies the CPU 20 of the interrupt differs depending on the address of the copy register group 24 (copy register group address) when the packet receiving unit 41 receives the interrupt packet. The timing for notifying interrupts in three different cases will be described below with reference to FIGS. 8 to 10 show a case where the cycle for transferring the data in the input / output control register group 32 of the device control device 14 to the main control device 12 is 1 ms. 8 to 10 show a case where the reference data storage address is “N” as in FIG. 6.

  First, the case where the copy register group address when receiving the interrupt packet is less than the reference data storage address will be described. FIG. 8 shows a time chart of an example when the copy register group address when receiving the interrupt packet is less than the reference data storage address.

  When the packet reception unit 41 receives a copy packet (see Mirror_PKT), the copy register group address counter (not shown) increases in response to the received copy packet written to the copy register group 24, and the copy is performed. The register group address increases. After receiving the copy packet, it is in a standby state until the copy packet of the next cycle is received, and the value of the copy register group address becomes “0”.

  When the capture of a predetermined number of data is completed, the packet receiving unit 41 receives an interrupt packet (IRQ_PKT, see). FIG. 8 shows a case where the address of the copy register group address when the packet receiving unit 41 receives an interrupt packet is “N−x”. The copy register group address is smaller than the reference data storage address. When writing to the copy register group 24 proceeds and the value of the copy register group address becomes “N”, the copy register group address matches the reference data storage address, and the interrupt control unit 44 interrupts the CPU 20 ( IRQ: Interrupt ReQuest). When the CPU 20 receives the interrupt notification, the CPU 20 reads (refers to) the interrupt processing from the copy register group 24.

  Next, a case where the copy register group address when receiving the interrupt packet is equal to or higher than the reference data storage address will be described. FIG. 9 shows an example time chart when the copy register group address when receiving the interrupt packet is equal to or higher than the reference data storage address.

  FIG. 9 shows a case where the value of the copy register group address is “N + x” when the packet receiving unit 41 receives an interrupt packet. The copy register group address is larger than the reference data storage address. In this case, writing of the copy packet in which data is currently written is completed, the value of the copy register group 24 returns to “0”, and the value of the copy register group 24 is changed according to the copy packet received in the next period. When it increases to “N”, the copy register group address matches the reference data storage address. When the copy register group address matches the reference data storage address, the interrupt control unit 44 notifies the CPU 20 of an interrupt (IRQ: Interrupt ReQuest). When the CPU 20 receives the interrupt notification, the CPU 20 reads (refers to) the interrupt processing from the copy register group 24. In this embodiment, even when the copy register group address when the interrupt packet is received is the same as the reference data storage address, the copy register group address and the reference data storage address coincide in the next cycle. Then, notify the interrupt.

  Next, the case where the value of the copy register group address when receiving the interrupt packet is “0” will be described. FIG. 10 shows an example time chart when the copy register group address when receiving the interrupt packet is “0”. As described above, when the value of the copy register group address is “0”, the SerDes control unit 22 is in a standby state until reception of a copy packet of the next cycle.

  When the value of the copy register group 24 is “0”, the value of the copy register group 24 increases in accordance with the copy packet received in the next period and becomes “N”. Match. When the copy register group address matches the reference data storage address, the interrupt control unit 44 notifies the CPU 20 of an interrupt (IRQ: Interrupt ReQuest). When the CPU 20 receives the interrupt notification, the CPU 20 reads (refers to) the interrupt processing from the copy register group 24.

  As described above, the SerDes control unit 22 of the main control device 12 according to the present embodiment includes the packet receiving unit 41, the copy register group control unit 42, the interrupt control unit 44, and the register 46. In the register 46, the CPU 20 stores in advance an address at which the reference data referred to by the CPU 20 in the interrupt processing is written in the copy register group 24 as a reference data storage address. When the packet receiving unit 41 receives the interrupt packet, the interrupt control unit 44 determines the copy register group address, the reference data storage address, and the timing based on the timing when the copy register group write signal and the interrupt packet data are received. Compare When the copy register group address matches the reference data storage address, the interrupt control unit 44 notifies the CPU 20 of the interrupt. The CPU 20 executes an interrupt process in response to the interrupt notification.

  As described above, the main controller 12 of the present embodiment determines completion of the update of the copy register group 24 by comparing the copy register group address with the reference data storage address. Thus, after receiving the interrupt packet, the interrupt control unit 44 notifies the CPU 20 of an interrupt after waiting for completion of the update of the copy register group 24.

  The transfer of the copy packet and the notification of the interrupt packet from the main control device 12 to the device control device 14 are asynchronous. Therefore, in the conventional main control device, when the CPU of the main control device refers to the reference data written in the copy register group in the interrupt processing, the software executed by the CPU for completing the data update of the copy register group Interrupt processing was performed after waiting for the wear processing. For this reason, there is a concern that the load on the CPU increases.

  On the other hand, in the main controller 12 of the present embodiment, the interrupt control unit 44 of the SerDes control unit 22 monitors the copy register group address of the copy register group 24, and notifies the CPU 20 of the interrupt when the update is completed. Therefore, the load on the CPU 20 can be reduced.

  In the present embodiment, the interrupt control unit 44 is realized by hardware resources, but is not limited thereto, and may be realized by software processing. Note that the load on the CPU 20 can be further reduced by implementing the interrupt control unit 44 with hardware resources as in the present embodiment. In addition, when realizing by software processing, it is possible to reduce the load on the CPU 20 by providing a processing unit such as a microcomputer separately from the CPU 20 and realizing the interrupt control unit 44 by software processing executed by the processing unit. From the viewpoint of

  In the present embodiment, the case where the communication apparatus of the present invention is applied to the main control apparatus 12 has been described. However, the present invention is not limited to this, and the present invention may be applied to a master of a communication apparatus having a so-called master-slave relationship. There is no particular limitation. Similarly, a communication system other than the control device 11 may be used.

  Moreover, each said embodiment is an example of this invention, and it cannot be overemphasized that it can change according to a condition within the range which does not deviate from the main point of this invention. The configurations and operations of the image forming apparatus 10, the control apparatus 11, the main control apparatus 12, the device control apparatus 14, and the like described in the present embodiment are merely examples, and can be used according to the situation without departing from the gist of the present invention. Needless to say, it can be changed.

DESCRIPTION OF SYMBOLS 10 Image forming apparatus 12 Main control apparatus 14 Equipment control apparatus 20 CPU
22 SerDes Control Unit 24 Copy Register Group 40 Serial Bus 41 Packet Receiver 42 Copy Register Group Control Unit 44 Interrupt Control Unit 46 Registers 52 and 56 Comparator

Claims (5)

A document for writing in the storage unit reference data to be referred to when the central processing unit performs interrupt processing based on the packet data transmitted from another communication device and the interrupt packet transmitted from the other communication device. Including
Storage means for storing an address of the storage unit to which the other reference data is written by the writing means;
Based on the interrupt packet transmitted from the other communication device, a write address of the storage unit to which the writing unit has written the reference data, and an address of the storage unit stored in the storage unit An interrupt control means for performing control to notify the central processing unit of an interrupt when they match,
A communication device comprising: The interrupt control means, when the central processing unit performs the interrupt processing without referring to the reference data stored in the storage unit, the write address and the storage means stored in the storage means Regardless of whether or not the address of the storage unit matches, control to notify the central processing unit of the interrupt,
The communication apparatus according to claim 1. The interrupt control unit includes a comparison circuit that compares the write address with the address of the storage unit stored in the storage unit, and interrupts the central processing unit based on the comparison result of the comparison circuit. Control to notify
The communication apparatus according to claim 2. A slave communication device;
The communication device according to any one of claims 1 to 3, wherein the communication device receives packet data transmitted from the slave communication device by serial communication.
A communication system comprising:   A communication processing program for causing a computer to function as at least one of a writing unit and an interrupt control unit of the communication device according to any one of claims 1 to 3.

Images