JP6217206B2 - Communication control device, image processing device, transfer control program - Google Patents

Description

  The present invention relates to a communication control device, an image processing device, and a transfer control program.

  When connecting via serial communication between the master communication control unit with a CPU that controls the control system and the slave communication control unit that controls the operation of the device, it is transmitted from the master communication control unit on the transmission side. In response to the received command (packet data), the slave communication control unit on the receiving side returns an Ack signal when it is normally received, and returns a Nack signal when it is a retransmission request based on an error or the like. There are systems that advance the protocol.

  On the other hand, there is a system that transmits a command (packet data) from a master communication control unit on the transmission side to a slave communication control unit on the reception side at a predetermined interval without checking the Ack signal or the Nack signal.

  In Patent Document 1, even in applications where there are strong restrictions on synchronous transfer such that a certain amount of data must be transmitted in a short cycle, processing at the time of occurrence of an error with low cost and low retransmission overhead is performed. A data communication device, an image processing system, and a data communication method that can be processed efficiently have been proposed.

  Further, Patent Document 2 proposes a data communication device that performs data communication appropriately and efficiently. For example, when a packet cannot be transferred normally, data communication for retransmitting the packet after a predetermined time has elapsed. It is described to do.

JP 2008-204245 A JP 2011-39897 A

  The present invention provides a communication control device, an image processing device, and a transfer control program that can prevent the transmission order and the reception order in packet data from being switched without creating new commands on the transmission side and the reception side. Is the purpose.

The invention according to claim 1 is a reception function for receiving packet data transmitted at regular intervals based on a transmission side communication function provided on the transmission side, and requests at least normal or retransmission to the transmission side. A communication control means having a reply function for returning an abnormal response signal; a normal transmission buffer for storing packet data received by normal transmission other than the retransmission and having two or more storage areas; A retransmission trust buffer for storing packet data received by transmission, shifting the storage area of the packet data stored in the normal transmission buffer based on a first-in first-out method to the next step, and sending the packet data to the retransmission trust buffer. and transmission control means for sending the stored packet data to the next step, the packet data transmitted by said transmission control means The packet data stored in the storage area at the most downstream stage of the normal transmission buffer is deleted and deleted from the normal transmission buffer or the retransmission trust buffer, and the cause of the retransmission The packet data stored in the retransmission trust buffer until the packet data stored in the retransmission trust buffer is sent to the next process, and the most downstream stage of the normal transmission buffer. And prohibiting means for prohibiting deletion of packet data that is a cause of the abnormal response signal.

According to a second aspect of the present invention, in the first aspect of the invention, the transmission control unit includes a transmission type determination unit that determines whether the received packet data is normal transmission or retransmission, and the transmission type. Based on the determination result of the determination means, a designation means for designating the packet data write destination as either the normal transmission buffer or the retransmission trust buffer, and a response signal for determining whether the response signal is normal or abnormal Control the execution of the determination means, the deletion means and the prohibition means, and when the determination result in the response signal determination means is a normal response signal, both packets of the normal transmission buffer and the retransmission trust buffer remove the data, in case of abnormality in the response signal to delete the packet data of the retransmission buffer, the re-transmission buffer for storing packet data to the next step Until protruding, and a deletion instruction means for instructing the above are normally stored in the storage area of the most downstream stage of the transmission buffer, to prohibit deletion of packet data which causes the response signal of the abnormality .

According to a third aspect of the present invention, there is provided an image forming unit that forms an image on a recording sheet based on at least received image information, an image forming control unit that controls image forming processing by the image forming unit, and the image forming control. A main control unit that is connected to the unit via a serial communication line having a smaller number of wires than a parallel communication line, and transmits the received image information to the image formation control unit, and the main control unit is a transmission side, The image formation control unit is a receiving side, and a normal or abnormal response signal is returned from the receiving side that receives packet data via the serial communication line at regular intervals, and an abnormal response signal is received. sender, receiving and communication control means for controlling the communication procedure by interrupting the transmission retransmits the corresponding packet data and the predetermined interval, the normal transmission other than the retransmission packets A normal transmission buffer for storing data and having two or more storage areas; and a retransmission trust buffer for storing packet data received by the retransmission, the packet data stored in the normal transmission buffer being Based on the first-in first-out method, the storage area is shifted and sent to the next process, the packet data stored in the retransmission trust buffer is sent to the next process, and the packet data sent by the transmission control means is The packet data stored in the storage area in the most downstream stage of the normal transmission buffer is deleted from the normal transmission buffer or the retransmission trust buffer and allowed to store the next packet data. Packet data that is to be deleted without being sent to the next process; Until the packet data stored in the file is sent to the next process, deletion of the packet data that is stored in the most downstream storage area of the normal transmission buffer and causes the abnormal response signal is prohibited. And an prohibiting unit .

The invention according to claim 4 receives the packet data at regular intervals , stores the packet data received by normal transmission other than retransmission, and stores the packet data in the normal transmission buffer provided with two or more storage areas. the packet data received by the normal transmission to store, stores the packet data received by retransmission to retransmission buffer, the packet data to which the are usually stored in the transmission buffer is shifted to the storage area based on the first-in first-out following And sending the packet data stored in the retransmission trust buffer to the next step, deleting the transmitted packet data from the normal transmission buffer or the retransmission trust buffer , and storing the next packet data. together to allow said is usually stored in a storage area of the most downstream stage of the transmission buffer Pakettode If the packet data is the cause of the retransmission, the packet data is deleted without being sent to the next process and allowed to store the next packet data. Until the transmitted packet data is sent to the next process, it is prohibited to delete the packet data stored in the storage area at the most downstream stage of the normal transmission buffer and causing the abnormal response signal. This is a transfer control program to be executed.

According to the first aspect of the present invention, it is possible to prevent the transmission order and the reception order in the packet data from being switched without newly creating commands on the transmission side and the reception side.

According to the second aspect of the present invention, an existing response signal can be used to determine whether or not packet data can be deleted. According to the third aspect of the present invention, a new command is created on the transmission side and the reception side. Therefore, it is possible to prevent the transmission order and the reception order in the packet data from being switched.

According to the fourth aspect of the present invention, it is possible to prevent the transmission order and the reception order in the packet data from being switched without newly creating commands on the transmission side and the reception side.

2 is a block diagram showing an outline of a control device of the image forming apparatus according to the present embodiment. FIG. It is a block diagram which shows the outline of a main control part among the control apparatuses which concern on this Embodiment. It is a block diagram which shows the outline of an apparatus control part among the control apparatuses which concern on this Embodiment. (A) is a format diagram showing an example of packet data according to the present embodiment, (B) is a format diagram showing details of the header area in the packet format, and (C) is data in the CS area in the header area. (D) is a data development view of the Code area in the header area, and (E) is a data development view of the SP area in the header area. It is a block diagram which shows the outline of the packet data alignment circuit provided with the slave side communication control part which concerns on this Embodiment. It is a timing chart which shows the communication protocol of the packet data between the master side communication control part and slave side communication control which concern on this Embodiment. It is a flowchart which shows the motor lock setting control routine performed with the image forming part which concerns on this Embodiment.

  FIG. 1 is a diagram illustrating a configuration example of a control device 10 of the image forming apparatus according to the present embodiment. In the control device 10, a main control unit 12 as a master and a device control unit 14 as a slave are connected via a serial bus 16.

  The serial bus 16 includes a signal line Tx for transmission to the device control unit 14 when viewed from the main control unit 12 and a signal line Rx for reception from the device control unit 14 when viewed from the main control unit 12. It is a full-duplex transmission line (for example, LVDS (Low Voltage Differential Signaling).

  The main control unit 12 includes a CPU control unit 18 and a master side communication control unit 20.

  The device control unit 14 includes a machine controller 22 and a slave side communication control unit 24.

  The CPU control unit 18 includes a CPU 26 and a CPU / I / F 28. The CPU 18 collectively controls other image processing such as image reading and FAX transmission / reception including image formation. In the image formation in the present embodiment, image data transmission / reception for executing the image formation and control for executing the image formation are managed, and the master side communication is performed via the CPU / I / F 28. The serial bus control unit 30 of the control unit 20 is connected.

  In addition to the serial bus control unit 30, the master side communication control unit 20 includes a first buffer 32, a second buffer 34, a Tx serializer / deserializer control unit (TxSERDES) 36, an Rx serializer / deserializer control unit (RxSERDES). These are connected to each other by a bus 39 such as a data bus or a control bus to be connected.

  The serial bus control unit 30 executes a program stored in a storage unit (not shown) and controls the entire image forming process (details will be described later, see FIG. 2).

  The serial bus control unit 30 receives a transmission request such as image data and a transmission packet from the CPU 26 via the CPU / I / F 28.

  Further, the serial bus control unit 30 sends a reception completion notification and a reception packet to the CPU 26 via the CPU / I / F 28 in response to reception of the transmission packet.

  The first buffer 32 includes a transmission buffer unit 32A and a retransmission buffer unit 32B, and temporarily stores information (parallel signals) received from the serial bus control unit 30, respectively.

  The second buffer 34 includes a reception buffer unit 34A, and temporarily stores information (serial signal) received from the RxSERDES 38.

  The TxSERDES 36 includes a parallel-serial conversion circuit 36A and a formatter 36B, and receives information (parallel signal) to be transmitted from the first buffer 32 to the device control unit 14.

  In this TxSERDES 36, the information (parallel signal) is packetized, each packet is converted into a serial signal, and transmitted to the device control unit 14 via the serial bus 16.

  Further, the RxSERDES 38 includes a serial-parallel conversion circuit 38A. When the packetized information (serial signal) is received from the device control unit 14 via the serial bus 16, the received information is converted into a parallel signal and decoded. The information contained in the packet is extracted and sent to the second buffer 34.

  On the other hand, a plurality of drive systems and sensors are connected to the machine controller 22 of the device control unit 14. For example, a drive system and sensors for forming an image include a motor for rotating a photoconductor and a developing roll, a sensor for detecting paper, a sensor for detecting toner density, and the like. Further, the image formation is not limited to the electrophotographic method, and the image formation may be performed by an ink jet method.

  The slave side communication control unit 24 of the device control unit 14 has the same hardware configuration as that of the master side communication control unit 20. That is, the slave-side communication control unit 24 includes a serial bus control unit 40, a first buffer 42 (a transmission buffer unit 42A, a retransmission buffer unit 42B), a second buffer 44 (a reception buffer unit 44A), and a TxSERDES 46 (parallel-serial). A conversion circuit 46A, a formatter 46B), and an RxSERDES 48 (serial-parallel conversion circuit 48A), which are connected to each other by a bus 49.

  When receiving a packet of information (serial signal) from the TxSERDES 36 of the master side communication control unit 20 via the serial bus 16, the RxSERDES 48 converts the received packet into a parallel signal, decodes it, and stores it in the reception buffer 44.

  The TxSERDES 46 packetizes information (parallel signals) to be transmitted to the main control unit 12, converts each packet into a serial signal, and transmits the serial signal to the RxSERDES 38 of the master side communication control unit 20 via the serial bus 16.

  The serial bus control unit 40 receives a transmission request such as image data and a transmission packet from the machine controller 22 via the I / O 50.

  In addition, the serial bus control unit 40 sends a reception completion notification and a reception packet to the machine controller 22 via the I / O 50 in response to reception of the transmission packet.

  The I / O 50 of the machine controller 22 includes, as an electrophotographic image formation control system, a Y color image control unit 52, an M color image control unit 54, a C color image formation control unit 56, and a K color image formation control unit 58. In addition, a sensor and a motor interrupt I / F 59 are provided.

  As shown in FIG. 2, the serial bus control unit 30 of the master side communication control unit 20 includes a controller 60, a packet generation circuit 62, a packet decode circuit 64, an address counter 66, and a copy register group 68.

  The controller 60 controls the first buffer 32, the second buffer 34, the TxSERDES 36, and the RxSERDES 38 by controlling protocol control, operation timing of each component, and the like.

  The packet generation circuit 62 generates packet data based on the information and sends it to the first buffer 32.

  The packet decoding circuit 64 decodes the packet data temporarily stored in the reception buffer 34 and extracts information included in the packet.

  The address counter 66 is read and transferred from the input / output control register group 78 (see FIG. 3, described later) which is a part of the control system of the serial bus control unit 40 of the slave side communication control unit 24 to the copy register group 68. A write destination address for writing the data is generated and output to the controller 60.

  As shown in FIG. 3, the serial bus control unit 40 of the slave side communication control unit 24 includes a controller 70, a packet decoding circuit 72, a packet generation circuit 74, an address counter 76, and an input / output control register group 78.

  The controller 70 controls the first buffer 42, the second buffer 44, the TxSERDES 46, and the RxSERDES 48 by controlling the protocol control, the operation timing of each component, and the like.

  The packet decoding circuit 72 decodes the parallel-format packet temporarily stored in the second buffer 44, and extracts data included in the packet.

  The packet generation circuit 74 generates a packet and sends it to the first buffer 42.

  The address counter 76 generates an address from which data is read when data is read from the input / output control register group 78 and copied to the copy register group 68 (see FIG. 2), and is output to the controller 70.

  Copying of data to the copy register group 70 (see FIG. 2) is performed by reading data of a predetermined size from the input / output control register group 68 and sequentially transferring the data to the master side communication control unit 20. Each time data of a predetermined size is read from the input / output control register group 68, an address incremented by the size is output. The address counter 76 is reset when reading of data from the input / output control register group 78 for copying to the copy register group 68 (see FIG. 2) is completed or when reading of data is started.

(Packet data alignment control)
Here, in the control device 10 of the image forming apparatus according to the present embodiment, when performing packet communication from the main control unit 12 to the device control unit 14, as a part of the high-speed transfer process, the main control unit 12 side receives the device control unit 14. The packet communication is executed at predetermined intervals without waiting for the Ack / Nack signal.

  In the packet communication by the TxSERDES 36 of the master side communication control unit 20 shown in FIG. 1, the formatter 36B constructs a packet format 80 as shown in FIG. As shown in FIG. 4A, the packet format 80 includes a 7-bit header area 80A, five areas 80B to 80E (ADR area 80B (14 bits), DATA area 80C (16 bits), Pad area) 80D (5 bits), CRC7 area 80E (7 bits)).

  As shown in FIG. 4B, the header area 80A further includes a chip select area (CS area) 82 (2 bits), a code area (Code area) 84 (4 bits), and a retransmission presence / absence area (SP area) 86 (1 bit). ).

  As shown in FIG. 4C, the signal in the CS area 82 is 2 bits, and two types of chip select codes (Chip0, Chip1) are classified by the bit signals.

  As shown in FIG. 4D, the signal in the Code area 84 is 4 bits, and four types of packet data (WriteWord, WriteBlock, ReadWord, ReadBlock) are classified by the bit signal.

  As shown in FIG. 4E, the signal in the SP area 86 is 1 bit, that is, a 0/1 (L / H) signal. In this embodiment, the signal “0 (L)” is not retransmitted. The signal “1 (H)” indicates the presence of retransmission.

  That is, when the packet data is analyzed by the serial bus control unit 40 of the slave side communication control unit 24 shown in FIG. 1, the bit data in the SP area 86 of the header area 80A is determined so that the packet data is transmitted normally. Whether it is data (normal data) or retransmission data can be recognized.

  By the way, numbering is not performed on packet data including normal data and retransmission data. This is intended for faster transmission than numbered.

  On the other hand, in the slave-side communication control unit 24, the order in which the packet data is received may be changed. When this change is made, the sequence control executed based on the information acquired by the packet data (for example, the motor lock of the image forming unit) In some cases, the switching of packet data before and after retransmission data may not be noticed until an error due to a shift in command procedure (for example, setting control) (see FIG. 7 (described later)) occurs.

  Note that when an error occurs in the sequence control, the communication of the corresponding information is performed again from the beginning.

  Here, in this embodiment, as shown in FIG. 3, a packet data alignment circuit unit 88 is provided in the controller 70 of the serial bus control unit 40 (slave side communication control unit 24) to correct the exchange of packet data. I did it.

  The packet data alignment circuit unit 88 transmits unnumbered packet data transmitted from the TxSERDES 36 (see FIG. 2) of the master side communication control unit 20 and received by the RxSERDES 48 (see FIG. 3) of the slave side communication control unit 24. Before temporarily storing in the reception buffer 44A of the second buffer 44, the header area 80A (see FIG. 4) of the packet data is analyzed to extract retransmission data and arranged in an appropriate order for normal transmission. A process of changing (alignment process) is performed.

  FIG. 5 is a block diagram in which the sorting processing by the packet data sorting circuit unit 88 shown in FIG. 3 is classified by function. Each block in FIG. 5 does not limit the hardware configuration of the packet data alignment circuit unit 88. For example, the packet data alignment circuit unit 88 may be an ASIC including a CPU and a memory, and the function of each unit may be processed by software.

  The packet data alignment circuit unit 88 includes a determination circuit unit 90 and a processing circuit unit 92. The bit of the SP area 86 (see FIG. 4) provided as a part of the header area 80A of the packet data in the determination circuit unit 90. The signal is determined, and the packet data is replaced by the processing circuit unit 92 based on the determined result.

  The determination circuit unit 90 includes a data analysis unit 94 that receives unnumbered packet data received by the RxSERDES 48 of the slave side communication control unit 24.

  The data analysis unit 94 sends the received packet data to the reception buffer cell 96, selects the bit signal of the SP area 86 included in the header area 80A from the packet data, and sends it to the SP signal determination unit 98. .

  The SP bit determination unit 98 determines whether the bit signal in the SP area 86 is a “0” signal or a “1” signal, and the determination result is sent to the write destination designation unit 99. The write destination is a specific destination of a buffer that temporarily stores (writes) packet data in the processing circuit unit 90 to be described later, and “reception 0” or “reception 1” is set as the write destination information. .

  The write destination designation unit 99 adds write destination information (reception 0 or reception 1) to the packet data sent from the data analysis unit 94 to the reception buffer cell 96.

  The reception buffer cell 96 is connected to the reception 1 buffer 100 and the reception 0 buffer 102 of the processing circuit unit 92. Here, the packet data temporarily stored in the reception buffer cell 96 of the determination circuit 90 is sent to either the reception 1 buffer 100 or the reception 0 buffer 102. At this time, the transmission destination (write destination) ) Is specified based on the write destination information (reception 0 or reception 1).

  That is, when the write destination information is “reception 0”, it is sent to the reception 0 buffer 102, and when the write destination information is “reception 1”, it is sent to the reception 1 buffer 100. Data is temporarily stored in the processing circuit unit 92.

  Here, the reception 0 buffer 102 has a two-stage shift register (reception 0 buffer “A” 102A, reception 0 buffer “B” 102B), and the reception 0 buffer 102 receives the packet data received from the determination circuit unit 90. In the case of storing, the data is first stored in the reception buffer 0 “B” 102B.

  In the reception 0 buffer 102, when the packet data is stored in the reception buffer 0 “B” 102B, the reception buffer 0 “A” 102A is empty (cleared and not stored). The packet data can be shifted from the reception buffer 0 “B” 102 B to the reception buffer 0 “A” 102 A.

  In other words, when packet data remains in the reception buffer 0 “A” 102A, the next packet data received by the reception buffer 0 “B” 102B is prohibited from shifting.

  The reception 0 buffer 102 and the reception 1 buffer 100 are connected to the buffer cell 104, respectively. The buffer cell 104 sends the packet data transferred from the reception 0 buffer 102 or the reception 1 buffer 100 to the reception buffer 44A of the second buffer 44.

  In normal reception, the second buffer 44 sends the received packet data downstream and outputs a reception completion notification. An Ack / Nack determination unit 106 is connected to the second buffer 44. The Ack / Nack determination unit 106 transmits an Ack / Nack signal transmitted from the second buffer 44 to the RxSERDES 38 (see FIG. 1) of the master-side communication control unit 20 (Ack signal in normal reception, abnormal reception). (Nack signal) is branched and input.

  The Ack / Nack determination unit 106 is connected to the buffer clear instruction unit 108.

  Based on the Ack / Nack signal received from the Ack / Nack determining unit 106, the buffer clear instructing unit 108 independently issues a clear instruction (deletion) to each of the reception 0 buffer 102, reception 1 buffer 100, and buffer cell 104. Command) signal is output.

  More specifically, when an Ack signal is received from Ack / Nack determination unit 106, a clear instruction signal is output to reception 0 buffer 102 (reception 0 buffer “A” 102 A), reception 1 buffer 100, and buffer cell 104. The

  On the other hand, when a Nack signal is received from the Ack / Nack determination unit 106, a clear instruction signal is output to the reception 1 buffer 100 and the buffer cell 104, and the reception 0 buffer 102 (reception 0 buffer “A” 102A) is output. Clear instruction signal is not output.

  The operation of this embodiment will be described below.

  In this embodiment, when packet data is transferred from the TxSERDES 36 of the master-side communication control unit 20 to the RxSERDES 48 of the slave-side communication control unit 24, the packet data is transferred at regular intervals without being numbered.

  The slave side communication control unit 24 analyzes the packet data according to the received order, and executes sequence control (for example, motor clock setting control) in the image forming unit based on the analyzed information.

  Incidentally, the packet data may be retransmitted based on the Nack signal from the slave side communication control unit 24. At this time, packet data is not numbered, including normal data and retransmission data.

  For this reason, in the slave side communication control part 24, the order which receives packet data may change.

  Therefore, in the present embodiment, the slave side communication control unit 24 (packet data alignment circuit unit 88) corrects the replacement of packet data.

  FIG. 6 shows a packet data communication protocol between the master side communication control unit 20 and the slave side communication control unit 24.

  In the following description, “WriteWord1” to “WriteWord5” are abbreviated as W1 to W5, respectively.

  First, when normal reception continues as in “W1” and “W2” in FIG. 6, the reception 0 buffer 102 is applied, and the reception buffer cell 96 → the reception 0 buffer “B” 102B of the determination circuit 90 → The reception 0 buffer “A” 102A → the buffer cell 104 is transferred, and the reception 0 buffer “A” 102A and the buffer cell 104 are repeatedly cleared.

  On the other hand, when there is an abnormal reception as in “W3” in FIG. 6, a Nack signal (“Nack3”) is output, and in response to the Nack signal, “W3” is retransmitted. Receive.

  However, as described above, based on the principle of packet transmission at regular intervals, as shown in “W4” in FIG. 6, before receiving retransmission data from the master side communication control unit 20 based on the Nack signal (“Nack4”). In addition, the packet data “W5” next to the abnormally received packet data “W4” may be received.

  In this case, if the reception 0 buffer 102 does not have a function of shifting the packet data step by step, the packet data “W5” is ahead of the packet data “W4” waiting for retransmission as in the comparative example of FIG. In some cases, the data is sent to the buffer cell 104.

  However, in the present embodiment, since the reception 0 buffer “A” 102A is not cleared based on the Nack signal (“Nack 4”) (see the period tc in FIG. 6), the packet data “W5” is the reception 0 buffer “B”. During this time, the retransmitted packet data “W4” is transferred from the reception buffer cell 96 to the reception 1 buffer 100.

  For this reason, the packet data “W4” retransmitted and temporarily stored in the reception 1 buffer 100 passes the packet data “W5” temporarily stored in the reception 0 buffer “B” 102B, and is sent to the buffer cell 104. .

  If the retransmitted packet data “W4” is normal, the reception 0 buffer “A” 102A and the buffer cell 104 are cleared based on the Ack signal, and the packet data “T” temporarily stored in the reception 0 buffer “B” 102B is stored. W5 ”is transferred from the reception 0 buffer“ A ”102A to the buffer cell 104.

  FIG. 7 is a flowchart showing an example of sequence control in the packet data image forming unit received by the slave side communication control unit 24. The flowchart of FIG. 7 operates normally when packet data is received in a predetermined order, and each step analyzes information (Word1 to Word1) analyzed from one or more packet data. Processing is performed based on Word 5).

  That is, FIG. 7 shows sequence control of motor lock setting in the image forming unit. First, initialization is performed in step 120, a count clock is selected in the next step 122, and then the process proceeds to step 124 to set the clock frequency. The process proceeds to step 126. In step 126, the number of output pulses is determined, and then the process proceeds to step 128, the clock circuit is turned on, and the process proceeds to step 130.

  In step 130, it is determined whether or not the operation of the motor clock setting sequence control in steps 120 to 128 is normal. If normal operation is confirmed (positive determination), the process proceeds to step 132 and ends normally. If the normal operation is not confirmed (negative determination), the process proceeds to step 134 and ends abnormally. If this abnormal termination occurs, an information reception abnormality is reported to the master side communication control unit 20.

  In the flowchart of FIG. 7, for example, when packet communication related to information necessary for the process of determining the number of output pulses in step 126 is abnormal, it is determined in step 134 that the packet communication is abnormal. The time until the normal operation is confirmed is delayed compared to the case where the slave side communication control unit 20 receives the packet data and notifies the retransmission and receives it normally.

  On the other hand, in the present embodiment, when packet data is not numbered, packet communication is performed at a higher speed than when the numbering is performed, and the slave-side communication control unit 20 receives an abnormal reception. The packet data after the abnormally received packet data is kept waiting until the retransmission data that is an alternative to the abnormal reception is normally received, and the reception order of the packet data is secured. Therefore, at the time of the sequence processing of the flowchart of FIG. Information loss can be avoided.

  In the present embodiment, the example in which the packet data alignment circuit 88 is incorporated in the controller 70 (slave side communication control unit 24) of the serial bus control unit 40 is shown, but it is not necessary to incorporate in the controller 70. It may be incorporated directly between the RxSERDES 48 and the second buffer 44, or may be connected via the bus 49 as a separate circuit if it functions as a part of the slave side communication control 24.

DESCRIPTION OF SYMBOLS 10 Control apparatus 12 Main control part 14 Equipment control part 16 Serial bus 18 CPU control part 20 Master side communication control part 22 Machine controller 24 Slave side communication control part 26 CPU
28 CPU ・ I / F
30 Serial Bus Control Unit 32 First Buffer 34 Second Buffer 36 Tx Serializer / Deserializer Control Unit (TxSERDES)
38 Rx Serializer / Deserializer Controller (RxSERDES)
39 Bus 32A Transmission buffer unit 32B Retransmission buffer unit 34A Reception buffer unit 36A Parallel-serial conversion circuit 36B Formatter 38A Serial-parallel conversion circuit 40 Serial bus control unit 42 First buffer 42A Transmission buffer unit 42B Retransmission buffer unit 44 Second retransmission buffer unit 44 Buffer 44B Reception buffer 46 TxSERDES
46A Parallel-serial conversion circuit 46B Formatter 48 RxSERDES
48A serial-parallel conversion circuit 49 bus 50 I / O
52 Y-color image control unit 54 M-color image control unit 56 C-color image formation control unit 58 K-color image formation control unit 59 Sensor, motor capture I / F
60 controller 62 packet generation circuit 64 packet decode circuit 66 address counter 68 copy register group 70 controller 72 packet decode circuit 74 packet generation circuit 76 address counter 78 input / output control register group 80 packet format 80A header area 80B ADR area 80C DATA area 80D Pad Area 80E CRC7 area 82 Chip select area (CS area)
84 Code area (Code area)
86 Retransmission presence / absence area (SP area)
88 packet data alignment circuit unit 90 determination circuit unit 92 processing circuit unit 94 data analysis unit 96 reception buffer cell 98 SP signal determination unit 99 write destination designation unit 100 reception 1 buffer 102 reception 0 buffer 102A reception 0 buffer “A”
102B Receive 0 buffer “B”
104 buffer cell 106 Ack / Nack determination unit 108 buffer clear instruction unit

Claims (4)

A reception function for receiving packet data transmitted at regular intervals based on a transmission side communication function provided on the transmission side, and a reply function for returning an abnormal response signal requesting at least normal or retransmission to the transmission side A communication control means comprising:
The normal transmission buffer for storing packet data received by normal transmission other than the retransmission and having two or more storage areas, and the retransmission credit buffer for storing the packet data received by the retransmission, A transmission control means for shifting the packet data stored in the normal transmission buffer to the next process by shifting the storage area based on a first-in first-out method, and sending the packet data stored in the retransmission trust buffer to the next process;
The packet data transmitted by the transmission control means is deleted from the normal transmission buffer or the retransmission trust buffer to permit storage of the next packet data and stored in the storage area at the most downstream stage of the normal transmission buffer. If the packet data is packet data that causes the retransmission, a deletion unit that deletes the packet data without sending it to the next process;
Until the packet data stored in the retransmission trust buffer is sent to the next step, the packet data that is stored in the storage area at the most downstream stage of the normal transmission buffer and causes the abnormal response signal is deleted. Prohibiting means to prohibit,
A communication control device. The delivery control means is
Transmission type determination means for determining whether the received packet data is normal transmission or retransmission;
Based on the determination result in the transmission type determination means, a designation means for designating the write destination of the packet data as either the normal transmission buffer or the retransmission trust buffer;
Response signal determining means for determining whether the response signal is normal or abnormal;
The execution of the deletion means and the prohibition means is controlled, and when the determination result by the response signal determination means is a normal response signal, the packet data in both the normal transmission buffer and the retransmission trust buffer are deleted. In the case of an abnormal response signal, the packet data in the retransmission trust buffer is deleted, and until the packet data stored in the retransmission trust buffer is sent to the next process, the storage area in the most downstream stage of the normal transmission buffer Delete instruction means for instructing prohibition of deletion of packet data that is a cause of the abnormal response signal,
A communication control device according to claim 1 .   An image forming unit that forms an image on a recording sheet based on at least the received image information;
  An image formation control unit that controls image formation processing by the image forming unit;
  A main control unit connected to the image formation control unit via a serial communication line having a smaller number of wires than a parallel communication line, and transmitting the received image information to the image formation control unit;
  The main control unit is a transmission side and the image formation control unit is a reception side, and a normal or abnormal response signal is returned to the transmission side from the reception side receiving packet data via the serial communication line at regular intervals. The transmission side that has received the abnormal response signal, communication control means for controlling the communication procedure for retransmitting the corresponding packet data by interrupting the transmission at the predetermined interval;
  The normal transmission buffer for storing packet data received by normal transmission other than the retransmission and having two or more storage areas, and the retransmission credit buffer for storing the packet data received by the retransmission, A transmission control means for shifting the packet data stored in the normal transmission buffer to the next process by shifting the storage area based on a first-in first-out method, and sending the packet data stored in the retransmission trust buffer to the next process;
  The packet data transmitted by the transmission control means is deleted from the normal transmission buffer or the retransmission trust buffer to permit storage of the next packet data and stored in the storage area at the most downstream stage of the normal transmission buffer. If the packet data is packet data that causes the retransmission, a deletion unit that deletes the packet data without sending it to the next process;
  Until the packet data stored in the retransmission trust buffer is sent to the next step, the packet data that is stored in the storage area at the most downstream stage of the normal transmission buffer and causes the abnormal response signal is deleted. Prohibiting means to prohibit,
An image processing apparatus.   Receive packet data at regular intervals,
  Stores packet data received by normal transmission other than retransmission and stores the packet data received by normal transmission in a normal transmission buffer having two or more storage areas, and stores packet data received by retransmission. Store it in the retransmission buffer,
  The packet data stored in the normal transmission buffer is sent to the next process by shifting the storage area based on a first-in first-out method, and the packet data stored in the retransmission trust buffer is sent to the next process,
  The transmitted packet data is deleted from the normal transmission buffer or the retransmission trust buffer to allow storage of the next packet data, and the packet data stored in the storage area at the most downstream stage of the normal transmission buffer is In the case of packet data that causes the retransmission, in principle, the packet data is deleted without being sent to the next process, and storage of the next packet data is permitted.
  As an exception, until the packet data stored in the retransmission trust buffer is sent to the next process, the packet data that is stored in the storage area at the most downstream stage of the normal transmission buffer and causes an abnormal response signal Prohibit the deletion of
A transfer control program that makes things happen.

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