JPH07121463A - Data communication control system - Google Patents

Abstract

PURPOSE:To realize a data communication by writing the information written in each RAM arranged in the prescribed address sections in the RAM of the opposite party, between two data processing systems. CONSTITUTION:In two data processing systems having each independent bus, data is written in a RAM 101 enabling the writing at a prescribed address section from the bus of a first data processing system 100, and at the same time, the address and data is written in an FIFO memory 102. The address and data written and stored in the FIFO memory are read in order of older address and data and are transmitted to a second data processing system 200 via a communication path 1. The signal transmitted to a second data processing system is received by the reception circuit 204 of this system, the signal is decoded into address and data, and this data is written in the address where a RAM 201 enabling the writing at a prescribed address section is received from the bus of this system, mediating between data and the reading and writing from the bus.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data communication control method between distributed control type data processing systems using a plurality of microcomputers, and more particularly to a data communication control method for transmitting / receiving data between respective local control systems. Regarding

[0002]

2. Description of the Related Art As a method of reflecting a change in data on one computer system on another computer system, a conventional method is to change the data on the RAM and the RAM.
Data is added to the transmission circuit provided separately from the data by the action of software and transmitted, and the receiving side receives the information on the receiving side, and the data is discriminated by the software and RAM Had been stored in.

Alternatively, instead of not adding information on what data is in the same circuit configuration as described above, there is a method in which data is sequentially sent and received collectively over all address divisions that may require transmission / reception of data. It was taken.

Further, the device itself uses a RAM having a plurality of access ports, or a circuit for arbitrating the access right is added, and a single RAM is shared by a plurality of computer systems, thereby transmitting and receiving data between the systems. I was doing

[0005]

By the way, the former requires software for adding information about what data is on the transmitting side and distinguishing it on the receiving side, and software for controlling communication. Since the load becomes large or redundant information that is not changed by the method of batch transfer is included, it takes a long time to process, and particularly in a device embedded system that requires high-speed real-time operation, it hinders the response performance of the entire device. It was a factor.

The latter is effective in reducing the load of software, which is a drawback of the former, and shortening the processing time. However, although the buses of the respective computer systems can be separated, the shared RAMs are different from each other. Since it is connected to the bus, it is impossible to electrically separate them, and there is a problem that the installation positions of the respective systems cannot be far apart.

Therefore, the present invention has been proposed in view of the above problems, and reduces the load of software to shorten the processing time and loosens the electrical connection between two systems. This makes it possible to increase the installation position of the system.

[0008]

As a technical means for achieving the above object, the present invention is a RAM which is writable in a predetermined address section from a bus, and when writing occurs in this RAM, an address and data for the RAM are written. F
A first data processing system including an IFO memory and a transmission circuit that sequentially cuts out an address and data from an output of the FIFO memory and sends the address and data, and receives a signal sent from the transmission circuit of the first data processing system and receives the address. And a second data processing system including a receiving circuit for decoding data and a RAM writable in a predetermined address section from a bus, and a communication path connecting the first and second data processing systems, The second data processing system is characterized by including means for arbitrating read / write from the bus to the RAM and writing the decoded data to the address of the RAM decoded by the receiving circuit.

By allowing both systems to have a transmission function and a reception function, it becomes possible to share data with each other.

[0010]

Since the communication can be performed by a simple process of writing to the RAM on the transmitting side and referring to the RAM on the receiving side, the load of software is reduced and the processing time can be shortened.

Both processing systems are loosely coupled by a channel, and the distance between the systems depends on the channel's capabilities.

[0012]

First Embodiment A first embodiment of a data communication control system according to the present invention will be described with reference to FIG. Address bus 191 and data bus 19 of the first data processing system 100
2 and a RAM 10 made writable in a predetermined address section from a bus 190 having a control bus 193
When the data is written to 1, the FIFO memory 1
The address and data are written in 02. FIFO
The addresses and data written and stored in the memory are read out in the oldest order and transmitted by the transmission circuit 103 to the second data processing system 200 via the communication path 1. The signal sent to the second data processing system is received by the receiving circuit 204 of this system, is decoded into an address and data, and is transmitted from the bus 290 having the address bus 291, the data bus 292, and the control bus 293 of this system. The data is written to the received address of the RAM 201 which is made writable in the address section while arbitrating the reading and writing from the bus.

A circuit diagram of the data communication control system of FIG. 1 will be described with reference to FIG. First, the first data processing system 300 will be described. Address decoder 30
5, the upper address 341 of the address bus 391 is a RAM
Output 34 when the address segment indicating 301 is matched
6 becomes valid, and the logical product of this output and the memory read signal 344 of the control bus 393 causes R
The write signal 348 for the RAM is obtained by activating the read signal 347 for the AM and taking the logical product of this output and the memory write signal 345 for the control bus.
To enable. When the write signal becomes valid, the RAM is designated by the lower address 342 of the address bus.
The data 343 on the data bus 392 is transferred to and held in the storage circuit in the AM. When the read signal becomes valid, the RAM outputs the data held in the storage circuit in the RAM specified by the lower address of the address bus to the data bus.

The FIFO memory 302 has a storage unit of a size obtained by adding the word length of the data bus and the number of bits of the lower address bus input to the RAM. When data is written to the RAM from the bus, the address and data written to the RAM are also written to the FIFO memory. However, F
RA when IFO memory full signal 352 is valid
When data is written to M, the wired OR wait signal 357 of the control bus is validated to enable the FIF.
The operation of the bus 390 is suspended until the O memory full signal becomes invalid. The FIFO memory holds addresses and data in a storage element in the order in which writing is performed, and reads out the addresses and data from the storage element in the order of oldness when reading is performed. The difference between the number of written information and the number of read information is defined as the effective number of information held in the FIFO memory in the FIFO.
It is counted inside the O memory. If the count value of the number of valid information in the FIFO memory is 0, the FIFO memory empty signal 3
53 is valid and if not 0, the FIFO memory empty signal is invalid. When the count value of the number of information items in the FIFO memory matches the storage capacity of the entire FIFO memory element, the full signal becomes valid and writing is prohibited.

The oscillator 306 generates a rectangular wave when the FIFO memory empty signal is invalid, and the rectangular wave generated here is supplied to the FIFO memory as a read signal 350 and to the driver 323 as a clock signal 358. When the FIFO memory receives a read signal from the oscillator, the FIFO memory outputs data and addresses in the oldest written order.

The drivers 321 are provided in parallel by the same number as the word length of the data bus, and the drivers 322 are provided in parallel by the same number as the number of bits of the lower address input to the RAM.
Sends the information read from the FIFO memory to the communication path 2 in synchronization with the clock signal output from the driver 323.

Next, the second data processing system 400 will be described. When the clock signal received by the receiver 428 is invalid, the output of the data selector 407 outputs the data 443 of the data bus 492 and the lower address 442 of the address bus 491. Address decoder 405
Indicates that the upper address 441 of the address bus is the RAM 401.
Output 446 becomes valid when the address section of the control bus 493 coincides with the memory read signal 44 of the control bus 493.
4 or the memory write signal 445, and the read signal 447 or the write signal 448 for the RAM is controlled. RAM data terminal 4
Since 12 is an output when reading and an input when writing, the three-state gates 414 and 415 controlled by the decoded memory read signal
A signal is sent from the RAM to the data bus when the RAM is read, and at other times, the data terminal 413 of the data selector.
From the RAM to the data terminal of the RAM. As a result, the RAM accepts reading and writing from the bus.

When the clock signal becomes valid, the output of the data selector outputs the data signal received by the receiver 426 and the address signal received by the receiver 427 in synchronization with the clock signal. At the same time the write signal to the RAM is enabled and writes this data to the received address of the RAM. When a read / write operation from the bus to the RAM occurs while the clock signal is enabled, the wired OR wait signal 457 is enabled to the control bus and the bus operation is suspended.

Due to the operation described above, the RA on the transmitting side
The contents written in M301 are transferred to the RAM 401 on the receiving side.

[0020]

Second Embodiment A second embodiment of the data communication control system according to the present invention will be described with reference to FIG. Address bus 591 and data bus 59 of the first data processing system 500
2 and a RAM 50 writable from a bus 590 having a control bus 593 in a predetermined address section
When data is written from the bus of this system to 1,
At the same time, the address and data are written in the FIFO memory 502. The addresses and data written and stored in the FIFO memory are read out in the order of oldest, and the transmission circuit 5
03 to the second data processing system 600 via the communication path 3. The signal sent to the second data processing system is received by the receiving circuit 604 of this system and is decoded into an address and data, and is transmitted from the bus 690 having the address bus 691, the data bus 692 and the control bus 693 of this system to a predetermined signal. Data is written to the received address of the RAM 601 that is writable in the address section while arbitrating with reading and writing from the bus.

When data is written to the RAM 601 from the bus 690 of the second data processing system, at the same time as the FI.
The address and data are written in the FO memory 602. The addresses and data written and stored in the FIFO memory are read out in the oldest order and transmitted by the transmission circuit 603 to the first data processing system via the communication path. The signal sent to the first data processing system is received by the receiving circuit 504 of this system, decoded into an address and data, and this data is written to the received address of the RAM 501 while arbitrating between reading and writing from the bus. .

FIG. 4 is a circuit diagram of the data communication control system of FIG.
Will be described with reference to. The memory decoder 708 determines that the high-order address 741 of the address bus 791 matches the address section indicating the RAM 701,
When the memory write signal 745 is input from No. 3, the output signals 748 and 749 are validated, and the memory read signal 744
Input makes the output signals 747 and 749 valid.

In the I / O decoder 709, the address 740 of the address bus is input port 711 and output port 7
Matches 10 address divisions, and I from the control bus
/ O read signal 754 is input, input port 711
When the I / O write signal 755 is input and the read signal 760 for the output port 710 is input, the write signal 761 for the output port 710 is input.

When the output 756 of the output port for exclusive control is valid or the reception clock 858 is invalid, the data selector 707 causes the RAM to accept reading and writing from the bus, and the output of the output port is invalid. When the reception clock is valid, the RAM is switched so that the reception address 842 and the reception data 843 are sent to the RAM.

The FIFO memory 702 is a data bus 792.
The storage unit is the size of the sum of the word length and the number of bits of the lower address bus for the RAM. When data is written to the RAM from the bus, the address and data written to the RAM are also written to the FIFO memory. However, if the RAM memory is written while the full signal 752 of the FIFO memory is valid, the wired OR wait signal 757 of the control bus is validated and F
Suspend bus operation until the IFO memory full signal is disabled.

The FIFO memory holds addresses and data in storage elements in the order in which they are written, and writes out addresses and data from the storage elements in the oldest order when reading is performed. The difference between the number of written information and the number of read information is F
The number of valid information held in the IFO memory is counted inside the FIFO memory. If the count value of the number of valid information inside the FIFO memory is 0, the FIFO memory empty signal 753
Is valid, and if not 0, the FIFO memory empty signal is invalid. When the count value of the number of information held in the FIFO memory matches the storage capacity of the entire FIFO memory element, the full signal becomes valid and writing is prohibited.

The oscillator 706 oscillates a rectangular wave when the FIFO memory empty signal is invalid, is given to the FIFO memory as a read signal 750, and is also sent as a clock signal 758 by the driver 723 to the other system through the communication path 4. . When the FIFO memory receives a read signal from the oscillator, the FIFO memory outputs data and addresses in the oldest written order, and the information is sent by the transmission data driver 721 and the transmission address driver 722 to the partner system through the communication path. The empty signal in the FIFO memory is notified by the driver 724 to the partner system via the communication path.

The output port is a 1-bit parallel port that can be rewritten from the bus and functions as exclusive control. When the exclusive control signal is enabled, the reception clock sent from the partner system is shut off, and the RAM
Prohibit writing from the other system. The content of this exclusive control is notified by the driver 725 to the partner system via the communication path.

The input port 711 is a parallel port which can be read from the bus. The FIFO memory full signal 752, the FIFO memory empty signal 753, the partner system exclusive control signal 856, and the partner system FIFO.
Empty signal 853 of memory, exclusive control signal 75 of output port
Enter 6.

The counterpart system has a circuit equivalent to this, and the driver 721 is the reception data receiver corresponding to the counterpart 726, the driver 722 is the reception address receiver corresponding to the counterpart 727, and the driver 723 is the counterpart. No. 728 of the receiving side, the driver 724 is connected to the receiving empty signal receiver corresponding to the other side 729, and the driver 725 is connected to the receiving exclusive control receiver corresponding to the other side 730 through the communication path.

When a write from the bus of the partner side occurs in the RAM corresponding to the partner side 701, the written address and data are accumulated in the FIFO memory corresponding to the partner side 702, and the oscillator corresponding to the partner side 706. The reception address and the reception data are sequentially received together with the reception clock signal from. When the reception control and the reception data synchronized with the reception clock are received from the other side when the exclusive control of the output port is disabled, the data selector 707 disconnects the RAM from the bus and writes the reception data to the reception address. When the writing of the RAM by the reception from the other side and the reading and writing of the RAM from the bus occur simultaneously, the wired OR wait signal 759 of the control bus is validated and the operation of the bus is temporarily suspended.

The software monitors the fullness, emptyness, and exclusive control state of the FIFO memory of itself and the other side and exchanges them.
By limiting the reading and writing of the RAM, it is possible to maintain the sameness of data when the information of the RAM is shared.

Although a parallel interface is assumed as the communication path in this embodiment, the communication path can be a serial interface by performing parallel / serial conversion on the transmitting side and serial / parallel conversion on the receiving side. It is also possible to electrically insulate each other by using a photocoupler or the like on the sending side or the receiving side of the path, or to modulate / demodulate an AC signal for AC transmission.

Furthermore, in the first and second embodiments, it is possible to add a second FIFO memory to the receiving side of the communication path to form a buffer.

[0035]

According to the data communication control method of the present invention, information is transmitted from software by a simple method of writing and reading to and from the RAM, so that the software development time can be shortened and the execution speed can be increased. In addition, since a function equivalent to a shared memory can be realized between computer systems that are loosely electrically connected via a communication path, its practical value is great.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a first embodiment of a data communication control system according to the present invention.

FIG. 2 is a circuit diagram of the data communication control system of FIG.

FIG. 3 is an explanatory diagram showing a second embodiment of the data communication control system according to the present invention.

FIG. 4 is a circuit diagram of the data communication control system of FIG.

[Explanation of symbols]

100, 300, 500, 700 First data processing system 101, 301, 501, 701 RAM 102, 302, 502, 702 FIFO memory 103, 503 Transmission circuit 504 Reception circuit 200, 400, 600, 800 Second data processing System 201, 401, 601 RAM 602 FIFO memory 603 Transmission circuit 204, 604 Reception circuit 1, 2, 3, 4 Communication path

Claims (4)

[Claims] 1. A RAM made writable in a predetermined address section from a bus, and R when writing occurs in this RAM.
A first data processing system including a FIFO memory for writing an address and data to an AM and a transmission circuit for sequentially extracting and transmitting the address and data from an output of the FIFO memory, and a transmission circuit for the first data processing system. A second data processing system comprising a receiving circuit for receiving the received signal and decoding the address and data, and a RAM writable in a predetermined address section from the bus; and the first and second data processing systems. And a communication path to be connected, wherein the second data processing system arbitrates reading and writing from the bus to the RAM and writes the decoded data to the address of the RAM decoded by the receiving circuit. Data communication control method having. 2. A second FIFO memory is added to the receiving side of the communication path to form a buffer.
Data communication control method described 3. A data processing system having buses independent of each other, each circuit having both a data transmitting side and a data receiving side of a data communication circuit, and making the RAM addresses of the transmitting side and the receiving side the same. A data communication control method that connects to each other via a communication path and shares mutual data. 4. A RAM made writable in a predetermined address section from a bus, and R when writing occurs in this RAM.
A FIFO memory for writing an address and data to the AM, a transmission circuit for sequentially extracting and transmitting the address and data from the output of this FIFO memory, and a signal transmitted from the transmission circuit of the partner data processing system are received to decode the address and data. And a RAM for receiving the signal.
4. The data communication control system according to claim 3, further comprising means for arbitrating reading and writing from the bus and writing the decoded data to the address of the RAM decoded by the receiving circuit.