JPH09120377A - Bus connection control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To start the design and production of an electronic equipment even before decision of a main bus or sub-bus to which the processing circuit constructing the electronic equipment is connected by providing a specific management means, a specific display means and a specific generation means respectively. SOLUTION: A management means 30 allocates 0 to the circuit that is mounted as an internal processing circuit 8a and 1 to the circuit that is mounted as an external processing circuit 8b respectively. Receiving the management data of the means 30, a display means 31 refers to only the output signal that is corresponding to the processing circuit where 1 is allocated by the means 30 among those output signals of a master detection means 20. When the circuit 8b serves as an accessing circuit to a memory 7, the means 30 outputs a display signal to show this fact. Receiving this signal, a generation means 32 outputs a control signal of the data direction toward a main address bus 1b from a sub-address bus 2b to a bus connection circuit 3 when the circuit 8b produces an address transfer signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus connection control circuit for issuing a data direction control signal to a bus connection circuit provided between a main bus and a sub bus included in an electronic device, and more particularly to a bus connection control circuit connected to a bus. The present invention relates to a bus connection control circuit that allows the processing circuit to be included in the design and manufacture even when it is not determined whether the processing circuit is connected to the main bus or the sub bus.

[0002]

2. Description of the Related Art In electronic equipment, MPU, memory, LSI
By adopting a configuration in which the processing circuit composed of
Between the MPU and the memory, between the MPU and the processing circuit,
The prescribed signal processing is executed by exchanging data between the memory and the processing circuit.

In such an electronic device, when the number of processing circuits to be mounted increases, one or a plurality of sub-buses in addition to the main bus (main data bus / main address bus) for connecting the MPU and the memory. (Sub data bus / sub address bus) is prepared and the processing circuit is connected to it.

In the case of adopting such a configuration, as shown in FIG. 6, a bus connecting circuit 3 having a driver / receiver function is provided between the main bus 1 and the sub bus 2, and the bus connecting circuit 3 is provided. The bus connection control circuit 4 for issuing a data direction control signal to In the figure, 5 is an MPU connected to the main bus 1, 6 is a main processing circuit connected to the main bus 1, 7 is a memory of the main processing circuit 6, and 8a is a process connected to the main bus 1. Circuits (hereinafter, referred to as internal processing circuits 8a) and 8b are processing circuits connected to the sub-bus 2 (hereinafter, external processing circuits 8b).
The bus connection control circuit 4 is provided in the main processing circuit 6, for example.

In the bus connection control circuit 4, the external processing circuit 8b DMA-writes in the memory 7 of the main processing circuit 6.
When writing by transfer, the external processing circuit 8b of the write request source sends an address to the main processing circuit 6 via the sub-address bus / main address bus, and also via the sub-data bus / main data bus. ,
Since data is sent to the main processing circuit 6, "sub address bus → main address bus" and "sub data bus → main data bus" are sent to the bus connection circuit 3.
A data direction control signal is issued to instruct the data direction.

Further, in the bus connection control circuit 4, when the external processing circuit 8b reads the memory 7 of the main processing circuit 6 by DMA transfer, the external processing circuit 8b of the read request source makes the sub address bus / main address. An address is sent to the main processing circuit 6 via the bus, and in response to this, the main processing circuit 6 sends via the main data bus / sub data bus to the external processing circuit 8b of the read request source. Then, the data direction control signal for instructing the data direction of "sub address bus → main address bus" and "main data bus → sub data bus" is issued to the bus connection circuit 3.

Further, the bus connection control circuit 4 includes an MPU 5
However, when writing to the register of the external processing circuit 8b, the MPU 5 sends an address to the external processing circuit 8b of the write destination via the main address bus / sub address bus, and the main data bus / sub data bus. Since data is sent to the write destination external processing circuit 8b via the, the data of “main address bus → sub address bus” and “main data bus → sub data bus” is sent to the bus connection circuit 3. A data direction control signal indicating a direction is issued.

Further, the bus connection control circuit 4 includes an MPU 5
However, when reading the register of the external processing circuit 8b, the MPU 5 sends an address to the external processing circuit 8b of the read destination via the main address bus / sub address bus, and in response to this, the read destination Since the external processing circuit 8b of FIG. 2 sends data to the MPU 5 via the sub data bus / main data bus, the "main address bus → sub address bus" and "sub data bus" are sent to the bus connection circuit 3. Bus → Main data bus ”
A data direction control signal is issued to instruct the data direction.

FIG. 7 shows a conventional configuration of a bus connection control circuit 4 for generating a data direction control signal between the main data bus and the sub data bus, and FIG. 8 shows such a main address bus and sub address bus. The conventional configuration of the bus connection control circuit 4 for generating the data direction control signal between the above and the following is illustrated.

Here, it is assumed that the bus connection control circuit 4 is provided with the processing circuit B as the internal processing circuit 8a and the processing circuits C and D as the external processing circuit 8b, as shown in FIG. doing. Further, in the bus connection control circuit 4, the bus connection circuit 3 has an initial state of flowing data in the direction of “main bus 1 → sub bus 2”, and the data direction control signal indicating a high level from the bus connection control circuit 4. It is assumed that the operation of switching the direction to the data direction of “sub bus 2 → main bus 1” is performed only when receiving the.

In the figure, reference numeral 10 denotes a master management block which has an output terminal associated with the external processing circuit 8b and monitors the bus use right permission signal issued by the MPU 5 to enable the external processing circuit 8b to operate. When it is detected whether it becomes a master having the bus use right (having the right to be the access source to the memory 7), and when it is detected that it becomes the master, the output terminal associated with the external processing circuit 8b is detected. It outputs a high level.

Reference numeral 11 denotes an address decoder block, which has an output terminal associated with the external processing circuit 8b and decodes an address issued by the master MPU 5 so that the external processing circuit 8b can access the MPU 5 as an access destination. When it is detected that the access destination is the access destination, a high level is output to the output terminal associated with the external processing circuit 8b.

As shown in FIG. 7, the conventional bus connection control circuit 4 calculates the logical sum value of the output signals of the master management block 10 and outputs it, and an OR circuit 12 and an OR circuit 12.
AND circuit 13 for calculating and outputting a logical product value of the output signal of the master output signal and the write signal (write signal to the memory 7) issued by the master internal processing circuit 8a / external processing circuit 8b.
An OR circuit 14 for calculating and outputting a logical sum value of output signals of the address decode block 11, an output signal of the OR circuit 14, and a register read signal issued by the MPU 5 (internal processing circuit 8a / external processing circuit 8b AN that calculates and outputs the logical product value with the read signal to the register that it has)
By including the D circuit 15, the output signal of the AND circuit 13, and the OR circuit 16 that calculates the logical sum value of the output signal of the AND circuit 15 and outputs the OR value to the bus connection circuit 3, the main data bus and the sub data Generates data direction control signals to and from the bus.

The conventional bus connection control circuit 4 is shown in FIG.
As shown in FIG. 4, an OR circuit 17 for calculating and outputting a logical sum value of output signals of the master management block 10, and an OR circuit 1
AND which outputs an output signal to the bus connection circuit 3 by calculating a logical product value of an output signal of the CPU 7 and an address transfer signal (address transfer signal to the memory 7) issued by the master internal processing circuit 8a / external processing circuit 8b. By including the circuit 18, the data direction control signal between the main address bus and the sub address is generated.

In the conventional bus connection control circuit 4 thus constructed, in the case of generating the data direction control signal between the main data bus and the sub data bus, the external processing circuit 8b has the structure shown in FIG. Becomes a master, the master management block 10 outputs a high-level output signal to the output terminal associated with the external processing circuit 8b, so that in the AND circuit 13, the external processing circuit 8b causes the main processing device 6 to operate. When a write signal is issued to the memory 7 via the memory 7, a high-level output signal is output, and in response to this, the OR circuit 16 instructs the bus connection circuit 3 to “sub data bus → main data bus”. A data direction control signal for instructing switching to the data direction of “” is output. on the other hand,
The AND circuit 13 outputs a low-level output signal when the external processing circuit 8b does not issue a write signal to the memory 7 via the main processing device 6, that is, during a read operation, and receives this. The OR circuit 16 is
A data direction control signal for maintaining the data direction of “main data bus → sub data bus” in the initial state is output to the bus connection circuit 3.

When the MPU 5 is the master and the external processing circuit 8b is the access destination, the address decode block 11 outputs a high level output signal to the output terminal associated with the external processing circuit 8b. The AND circuit 15 outputs a high level output signal when the MPU 5 issues a register read signal to the external processing circuit 8b, and in response to this, the OR circuit 16 connects the bus connection. A data direction control signal for instructing switching to the data direction of “sub data bus → main data bus” is output to the circuit 3. on the other hand,
The AND circuit 15 outputs a low-level output signal when the MPU 5 does not issue a register read signal to the external processing circuit 8b, that is, when it is a write operation. A data direction control signal for maintaining the data direction of “main data bus → sub data bus” in the initial state is output to the bus connection circuit 3.

Further, in the conventional bus connection control circuit 4 having such a configuration, when the data direction control signal between the main address bus and the sub address bus is generated,
According to the configuration of FIG. 8, when the external processing circuit 8b becomes the master, the master management block 10 outputs a high-level output signal to the output terminal associated with the external processing circuit 8b. When the external processing circuit 8b issues an address transfer signal to the memory 7 via the main processing device 6, it outputs a high-level output signal to the bus connection circuit 3 so that "sub-address bus → main A data direction control signal for instructing switching of the "address bus" to the data direction is output. And
When the MPU 5 becomes the master, the data direction control signal is not output to the bus connection circuit 3 so that the data direction of "main address bus → sub address bus" in the initial state is maintained.

As described above, the conventional bus connection control circuit 4
Is the sub-bus 2 among the processing circuits incorporated in the electronic device.
A circuit is constructed by identifying the external processing circuit 8b to be connected to and using the state of the external processing circuit 8b (states of the processing circuits C and D in the example of FIGS. 7 and 8) as signal elements. The method of doing it was adopted.

[0019]

However, according to such a conventional technique, there is a specification as to whether the processing circuit forming the electronic device is mounted as the external processing circuit 8b or the internal processing circuit 8a. If not decided, the bus connection control circuit 4 cannot be designed.

According to the prior art, if the board design of the electronic device is not completed, the processing circuit and the bus connection control circuit cannot be designed or manufactured, which delays the design or manufacturing of the electronic device. was there.

According to such a conventional technique, when the internal processing circuit 8a is changed to the external processing circuit 8b or the external processing circuit 8b is changed to the internal processing circuit 8a, the bus connection control circuit 4 is changed. There was a problem that it had to be designed and manufactured again.

The present invention has been made in view of the above circumstances, and is designed and manufactured even when it is not determined which of the main bus and the sub bus the processing circuit constituting the electronic device is connected to. The purpose is to provide a new bus connection control circuit.

[0023]

1 and 2 show the principle configuration of a bus connection control circuit 4 of the present invention. In the figure, FIG.
The same components as those described in 1 are indicated by the same symbols, 1a is a main data bus, 1b is a main address bus, 2a is a sub data bus, and 2b is a sub address bus. Here, as shown in FIG. 6, the memory 7 is managed by the main processing circuit 6 and indirectly connected to the main data bus 1a.
/ Sub-data bus 2a, but as shown in FIGS. 1 and 2, it may be directly connected to main data bus 1a / sub-data bus 2a.

The bus connection control circuit 4 of the present invention, the principle configuration of which is shown in FIG. 1, generates a data direction control signal between the main data bus 1a and the sub data bus 2a. And access destination detection means 21
A management unit 22, a second management unit 23, a first display unit 24, a second display unit 25, a third display unit 26, and a generation unit 27.

The master detecting means 20 has output terminals associated with the internal processing circuit 8a and the external processing circuit 8b constituting the electronic equipment, and monitors the bus use right permission signal issued by the MPU 5, When it is detected whether the processing circuit becomes a master having the bus use right (having the right to access the memory 7 connected to the main data bus 1a), and when it is detected that the processing circuit becomes the master, the processing circuit is An output signal to that effect is output to the associated output terminal.

The access destination detecting means 21 has an output terminal associated with the internal processing circuit 8a and the external processing circuit 8b constituting the electronic device, and decodes the address issued by the master MPU 5 so that Become M
A processing circuit to be accessed by the PU 5 is detected, and an output signal to that effect is output to an output terminal associated with the processing circuit.

The management means 22 manages whether each processing circuit constituting the electronic device is the internal processing circuit 8a connected to the main data bus 1a or the external processing circuit 8b connected to the sub data bus 2a. To do. The second management means 23 manages whether or not each processing circuit forming the electronic device is of a multiple type that transfers an address to a data bus.

The first display means 24 receives the management data of the management means 22 and the output signal of the master detection means 20 as input, and when the external processing circuit 8b becomes the access source to the memory 7, the first display means 24 indicates that. Output a display signal. The second display means 25 receives the management data of the management means 22 and the output signal of the access destination detection means 21 as input, and the external processing circuit 8
When b is the access destination of the MPU 5, a display signal to that effect is output.

The third display means 26 is the second management means 2
3, the management data and the information indicating whether or not each processing circuit generated by the first display means 24 upon output of the display signal is the external processing circuit 8b of the access source,
When the external processing circuit 8b of the multiplex type is the access source to the memory 7, a display signal to that effect is output.

The generation means 27 generates a data direction control signal using the display signals of the first display means 24 / second display means 25 and the issued read / write signal, and outputs the data direction control signal to the bus connection circuit 3. A data direction control signal is generated by outputting or using the display signal of the first display means 24 / the second display means 25 / the third display means 26 and the issued read / write signal / access transfer signal. And outputs it to the bus connection circuit 3.

In the bus connection control circuit 4 of the present invention, the principle configuration of which is shown in FIG.
Is assigned to, for example, "0" for the internal processing circuit 8a and "1" for the external processing circuit 8b, so that each processing circuit constituting the electronic device is assigned an internal processing circuit. 8a, external processing circuit 8b
Manage what is.

Upon receiving the management data of the management means 22,
Of the output signals of the master detection means 20, the first display means 24 refers to only the output circuit of the master detection means 20 that is associated with the processing circuit to which "1" is assigned, so that the external processing circuit 8b transfers to the memory 7. It is detected whether or not it is an access source, and when it is an access source, a display signal to that effect is output.

On the other hand, in response to the management data of the management means 22, the second display means 25 displays the access destination detection means 21.
Of the output signals of the above, the management means 22 refers to only the one associated with the processing circuit to which “1” is assigned, for example, to detect whether or not the external processing circuit 8b is the access destination of the MPU 5, and access When it comes first, a display signal to that effect is output.

In response to the display signals of the first and second display means 24 and 25, the generation means 27 causes the first display means 2 to operate.
4 indicates that the external processing circuit 8b is the access source, when the external processing circuit 8b issues a write signal to the memory 7, the bus connection circuit 3 is instructed to "sub data bus 2a → main When the data direction control signal of the data direction of the data bus 1a "is output and the write signal is not issued, that is, when the read operation is performed, the data direction control signal of the data direction of the" main data bus 1a → the sub data bus 2a "is output. Output.

When the second display means 25 displays that the external processing circuit 8b is the access destination of the MPU 5, the generation means 27 instructs the bus connection circuit 3 when the MPU 5 issues a read signal. Then, when the data direction control signal in the data direction of “sub data bus 2a → main data bus 1a” is output and the read signal is not issued, that is, during the write operation, the “main data bus 1
The data direction control signal of the data direction of "a-> sub data bus 2a" is output.

When a multiplex type for transferring an address to the data bus is used as the processing circuit, the second managing means 23 is, for example, "1" for the multiplex type mounted, and the multiplex type. By allocating “0” to those not mounted, it is managed whether each processing circuit forming the electronic device is of the multiple type or not.

In response to the management data of the second management means 23, the third display means 25 has the respective processing circuits generated by the first display means 24 for outputting the display signal, and the external processing circuits 8b of the access source. Of the information that indicates whether or not
For example, the second management means 23 refers to only those associated with the processing circuit to which “1” is assigned to determine whether or not the external processing circuit 8b and the multiplex type are the access sources to the memory 7. When it is detected and becomes an access source, a display signal to that effect is output.

Upon receiving the display signal of the third display means 25, the generation means 27 displays from the third display means 25 that the external processing circuit 8b and the multiplex type are the access sources. When the external processing circuit 8b issues an address transfer signal, the bus connection circuit 3 is instructed to "sub-data bus 2a → main data bus 1a" in response to the address transfer using the data bus. "
The data direction control signal of the data direction of is output.

On the other hand, the bus connection control circuit 4 of the present invention, whose principle structure is shown in FIG. 2, generates a data direction control signal between the main address bus 1b and the sub address bus 2b. In addition to the master detection means 20 described above, a management means 30, a display means 31, and a generation means 32.
And

In this management means 30, the internal processing circuit 8a is connected to the main address bus 1b, and the external processing circuit 8b.
1 is connected to the sub address bus 2b.
The same processing as that of the management means 22 described in step 1 is executed. In the display means 31, the internal processing circuit 8a has the main address bus 1b.
And the external processing circuit 8b is connected to the sub-address bus 2b.
The same processing as that of the first display means 24 described with reference to FIG. 1 is executed except that it is connected to. The generation means 32 generates a data direction control signal using the display signal of the display means 31 and the issued address transfer signal, and outputs it to the bus connection circuit 3.

In the bus connection control circuit 4 of the present invention, the principle configuration of which is shown in FIG.
Is assigned to, for example, "0" for the internal processing circuit 8a and "1" for the external processing circuit 8b, so that each processing circuit constituting the electronic device is assigned an internal processing circuit. 8a, external processing circuit 8b
Manage what is.

Upon receiving the management data of the management means 30,
The display means 31 is one of the output signals of the master detection means 20.
For example, when the management means 30 refers to only the processing circuit to which “1” is allocated, whether or not the external processing circuit 8b is the access source to the memory 7 is detected. , And outputs a display signal to that effect.

In response to the display signal from the display means 31, when the display means 31 indicates that the external processing circuit 8b is the access source of the memory 7, the generation means 32 sends the address to the external processing circuit 8b. When issuing the transfer signal,
A data direction control signal in the data direction of “sub address bus 2b → main address bus 1b” is output to the bus connection circuit 3.

Thus, the bus connection control circuit 4 of the present invention
Then, the processing circuit mounted on the electronic device is the internal processing circuit 8
Regardless of whether it is implemented as a or as the external processing circuit 8b, the flag indicating which is to be implemented is simply registered in the management means 22 and 30 without changing the circuit configuration. Just do it.

Further, in the bus connection control circuit 4 of the present invention, even when the processing circuit mounted on the electronic device is mounted in the multiple type for transferring the address to the data bus, it is not mounted in the multiple type. Even in such a case, it suffices to simply register the flag indicating which is to be mounted in the second management means 23 without changing the circuit configuration.

From now on, by using the bus connection control circuit 4 of the present invention, even if the board design of the electronic device is not completed, the processing circuit and the bus connection control circuit 4 constituting the electronic device can be designed and manufactured. Like Then, even if there is a change from the internal processing circuit 8a to the external processing circuit 8b or a change from the external processing circuit 8b to the internal processing circuit 8a, it becomes possible to easily deal with it.

[0047]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail according to embodiments. FIG. 3 shows an embodiment of the bus connection control circuit 4 of the present invention.

The bus connection control circuit 4 of this embodiment generates a data direction control signal between the main data bus 1a and the sub data bus 2a, and is a multiplex type processing circuit for transferring an address to the data bus. Is assumed not to be used.

Here, in this embodiment, as shown in FIG. 9, it is assumed that the processing circuit B is provided as the internal processing circuit 8a and the processing circuits C and D are provided as the external processing circuit 8b. . Although the main processing circuit 6 is also one of the internal processing circuits 8a, it is specified that the main processing circuit 6 is connected to the main data bus 1a.
Removed from a. Further, only when the bus connection circuit 3 has an initial state of flowing data in the direction of “main data bus 1a → sub data bus 2a” and receives a data direction control signal indicating a high level from the bus connection control circuit 4. It is assumed that the operation is switched to the data direction of “sub data bus 2a → main data bus 1a”.

In the figure, reference numeral 40 denotes a master management block, which has output terminals associated with the processing circuits B, C, and D constituting the electronic equipment, and monitors the bus use right permission signal issued by the MPU 5. By doing so, the processing circuit has the master right to use the bus (right to access the memory 7).
When it is detected that it becomes a master, it outputs an output signal to that effect to an output terminal associated with the processing circuit.

Reference numeral 41 is an address decoding block, which has output terminals associated with the processing circuits B, C, and D constituting the electronic equipment, and decodes the address issued by the master MPU 5 to output the MPU 5 A processing circuit to be accessed is detected, and an output signal to that effect is output to an output terminal associated with the processing circuit.

Reference numeral 42 denotes an LSI layout information setting register, which is composed of latch circuits associated with the processing circuits B, C, and D which form the electronic equipment, and the processing circuits forming a pair are internally provided in these latch circuits. When it is the processing circuit 8a, data indicating "0" is latched, and when it is the external processing circuit 8b, data indicating "1" is latched and output. The register value will be set by the MPU 5.

The bus connection control circuit 4 of this embodiment is provided so as to correspond to the processing circuits B, C and D constituting the electronic equipment, and the corresponding output signal output from the master management block 40 and the LSI layout information. Three ANs for calculating and outputting a logical product value with the corresponding output signal output from the setting register 42
D circuits 43, 44, 45 and these three AND circuits 4
An OR circuit 46 that calculates and outputs the logical sum value of the output signals of 3, 44, and 45, an output signal of the OR circuit 46, and a write signal issued by the processing circuits B, C, and D that are masters (to the memory 7). AND signal 47) and an AND circuit 47 for calculating and outputting a logical product value thereof and a processing circuit B constituting an electronic device,
Three provided to be associated with C and D to calculate and output a logical product value of the corresponding output signal output from the address decoding block 41 and the corresponding output signal output from the LSI layout information setting register 42. AND circuits 48, 49, 5
0, and an OR circuit 51 that calculates and outputs the logical sum value of the output signals of these three AND circuits 48, 49, 50, and OR
An AND circuit 52 for calculating a logical product value of an output signal of the circuit 51 and a register read signal issued by the MPU 5 (a read signal to a register of the processing circuits B, C, D), and A
An OR which calculates a logical sum value of the output signal of the ND circuit 47 and the output signal of the AND circuit 52 and outputs the calculated value to the bus connection circuit 3.
By including the circuit 53, a data direction control signal between the main data bus 1a and the sub data bus 2a is generated.

In the bus connection control circuit 4 of the present invention thus configured, the LSI layout information setting register 42 outputs a low level to the output terminal of the processing circuit B which is the internal processing circuit 8a, and the external processing circuit. 8b are processing circuits C and D
High level is output to the output terminal of.

As a result, the AND circuit 43 provided in association with the processing circuit B always outputs a low level regardless of the output signal of the master management block 40, and is associated with the processing circuit C which is the external processing circuit 8b. AND provided
The circuit 44 and the AND circuit 45 provided in association with the processing circuit D that is the external processing circuit 8b outputs a high level when the master management block 40 outputs a high level indicating that it is a master as an output signal. , When outputting a low level indicating that it is not a master, it outputs a low level.

In response to the output processing of the AND circuits 43, 44, 45, the OR circuit 46 outputs a high level when the processing circuits C, D, which are the external processing circuits 8b, become masters. The AND circuit 47 outputs a high level output signal when the external processing circuit 8b issues a write signal to the memory 7. Then, in response to this, the OR circuit 53, with respect to the bus connection circuit 3,
A high-level data direction control signal for instructing switching from the "sub data bus 2a to the main data bus 1a" in the data direction is output.

On the other hand, the AND circuit 47 outputs a low level output signal when the external processing circuit 8b does not issue a write signal to the memory 7, that is, when it is a read operation, and in response to this, The OR circuit 16 is
A data direction control signal for maintaining the data direction of “main data bus 1a → sub data bus 2a” in the initial state is output to the bus connection circuit 3.

Further, in response to the output processing of the LSI layout information setting register 42, the AND circuit 48 provided in association with the processing circuit B always outputs the low level regardless of the output signal of the address decoding 41, and the external processing. AND circuit 49 provided in association with the processing circuit C which is the circuit 8b
And the AND circuit 50 provided in association with the processing circuit D which is the external processing circuit 8b outputs a high level when the address decoding block 41 outputs a high level indicating that it is an access destination of the MPU 5 as an output signal. However, when the low level indicating that it is not the access destination is output, the low level is output.

In response to the output processing of the AND circuits 48, 49, 50, the OR circuit 51 outputs a high level when the processing circuits C, D, which are the external processing circuits 8b, are the access destinations of the MPU 5, and In response, the AND circuit 52
When the MPU 5 issues a register read signal to the external processing circuit 8b, it outputs a high level output signal. In response to this, the OR circuit 53 outputs a high level data direction control signal for instructing the bus connection circuit 3 to switch the data direction of "sub data bus 2a → main data bus 1a". .

On the other hand, the AND circuit 52 outputs a low-level output signal when the MPU 5 does not issue a register read signal to the external processing circuit 8b, that is, when it is a write operation, and receives this, OR circuit 5
3 outputs to the bus connection circuit 3 a low-level data direction control signal for maintaining the data direction of "main data bus 1a → sub data bus 2a" in the initial state.

In this way, by following the bus connection control circuit 4 of the present invention of FIG. 3, the same data direction control signal as that of the prior art described with reference to FIG. 7 can be generated, but the bus of the present invention is used. According to the connection control circuit 4, even if it is not decided whether the processing circuits B, C, and D are mounted in the internal processing circuit 8a or the external processing circuit 8b,
It has the feature of being included in its design and manufacturing.

FIG. 4 shows another embodiment of the bus connection control circuit 4 of the present invention. Here, in the figure, the same components as those described in FIG. 3 are denoted by the same symbols. The bus connection control circuit 4 of this embodiment includes processing circuits B, C and D.
It is assumed that a multiplex type that transfers an address to the data bus may be used.

Reference numeral 54 is an LSI type information setting register, which is composed of latch circuits associated with the processing circuits B, C, and D constituting the electronic equipment. Data of "1" is latched when it is of the multiplex type for transferring an address to the bus, and "0" is latched and output when it is not of the multiplex type. The register value is
It will be set by the MPU 5.

The bus connection control circuit 4 of this embodiment is shown in FIG.
In addition to the circuit elements provided in the embodiment, an AND circuit 55 that calculates and outputs a logical product value of the output signal of the AND circuit 43 and the output signal of the processing circuit B output from the LSI type information setting register 54, The output signal of the AND circuit 44 and LS
AND circuit 56 for calculating and outputting a logical product value with the output signal of the processing circuit C output from the I type information setting register 54
And an AND circuit 57 for calculating and outputting a logical product value of the output signal of the AND circuit 45 and the output signal of the processing circuit D output by the LSI type information setting register 54, and these three AND circuits 55, 56, An OR circuit 58 that calculates and outputs a logical sum value of the output signals of 57, an output signal of the OR circuit 58, and an address phase signal that is issued by the processing circuits B, C, and D that are masters (address using a data bus). AND circuit 59 for calculating a logical product value with a signal indicating that it is in the phase of transferring and for inputting it to the OR circuit 53.

In the bus connection control circuit 4 of the present invention thus configured, the LSI type information setting register 54 outputs a high level to the output terminal of the multiplex type processing circuit for transferring the address to the data bus, A low level is output to the output terminal of the processing circuit that is not the multiplex type.

As a result, the AND circuits 55, 56, 57.
Among these, the one provided in association with the multiplex type processing circuit for transferring the address to the data bus becomes effective, and the AND circuits 55, 56,
When a high level indicating that the external processing circuit 8b has become the master is output from 57, the OR circuit 58 outputs the high level, and in response to this, the AND circuit 59 causes the external processing circuit to be the master. When 8b outputs the address phase signal, it outputs a high level output signal. In response to this, the OR circuit 53 causes the bus connection circuit 3
In contrast, “sub data bus 2a → main data bus 1
A high level data direction control signal for instructing switching to the data direction of "a" is output.

In this way, according to the bus connection control circuit 4 of the present invention of FIG. 4, the processing circuits B, C and D are
Even if it is not decided whether to implement using the multiplex type that transfers addresses to the data bus or to implement without using the multiplex type, there is a feature that it can be included in the design and manufacture.

FIG. 5 shows an embodiment of the bus connection control circuit 4 of the present invention. Bus connection control circuit 4 of this embodiment
Is for generating a data direction control signal between the main address bus 1b and the sub address bus 2b.

In this embodiment, as shown in FIG. 9, it is assumed that the processing circuit B is provided as the internal processing circuit 8a and the processing circuits C and D are provided as the external processing circuit 8b. . In addition, the bus connection circuit 3
Only when a data direction control signal indicating a high level is received from the bus connection control circuit 4 with an initial state of flowing data in the direction of “main address bus 1b → sub address bus 2b”, the direction is changed to “sub address bus 2b → It is assumed that the operation of switching to the data direction of the "main address bus 1b" is performed.

In the figure, reference numeral 60 denotes a master management block, which has the same function as the master management block 40 described with reference to FIG. 3, and 61 is an LSI layout information setting register, which is the LSI described with reference to FIG. It has the same function as the arrangement information setting register 54.

The bus connection control circuit 4 of this embodiment is provided so as to correspond to the processing circuits B, C and D constituting the electronic equipment, and the corresponding output signal output from the master management block 60 and the LSI placement information. Three ANs for calculating and outputting a logical product value with the corresponding output signal output from the setting register 61
D circuits 62, 63, 64 and these three AND circuits 6
An OR circuit 65 for calculating and outputting a logical sum value of the output signals of 2, 63, 64, a logic of the output signal of the OR circuit 65, and an address transfer signal issued by the processing circuits B, C, D as masters. AN for calculating the product value and outputting it to the bus connection circuit 3
By including the D circuit 66, the main address bus 1b
And a data direction control signal between the sub address 2b and the sub address 2b.

In the bus connection control circuit 4 of the present invention thus configured, the LSI placement information setting register 61 outputs a low level to the output terminal of the processing circuit B which is the internal processing circuit 8a, and the external processing circuit. 8b are processing circuits C and D
High level is output to the output terminal of.

As a result, the AND circuit 62 provided in association with the processing circuit B always outputs a low level regardless of the output signal of the master management block 60, and is associated with the processing circuit C which is the external processing circuit 8b. AND provided
The circuit 63 and the AND circuit 64 provided in association with the processing circuit D that is the external processing circuit 8b outputs a high level when the master management block 60 outputs a high level indicating that it is a master as an output signal. , When outputting a low level indicating that it is not a master, it outputs a low level.

In response to the output processing of the AND circuits 62, 63, 64, the OR circuit 65 outputs a high level when the processing circuits C, D, which are the external processing circuits 8b, become masters. The AND circuit 66, when the external processing circuit 8b issues an address transfer signal to the memory 7, issues a high-level data direction instructing switching from the "sub address bus 2b to the main address bus 1b" in the data direction. Output a control signal.

In this way, by following the bus connection control circuit 4 of the present invention shown in FIG. 5, the same data direction control signal as in the prior art described with reference to FIG. 8 can be generated. According to the connection control circuit 4, even if it is not decided whether the processing circuits B, C, and D are mounted in the internal processing circuit 8a or the external processing circuit 8b,
It has the feature of being included in its design and manufacturing.

[0076]

As described above, in the bus connection control circuit of the present invention, whether the processing circuit mounted on the electronic device is mounted as an internal processing circuit or an external processing circuit, It suffices to register the flag of which is to be implemented without changing the circuit configuration.

In the bus connection control circuit of the present invention,
Whether the processing circuit implemented in the electronic device is implemented as a multiplex type that transfers an address to the data bus or not as the multiplex type, simply without changing the circuit configuration, You only need to register the flag to determine which is implemented.

From now on, by using the bus connection control circuit of the present invention, even if the board design of the electronic device is not completed, it can be included in the design and manufacture of the processing circuit and the bus connection control circuit which constitute the electronic device. Become. Then, even if the internal processing circuit is changed to the external processing circuit or the external processing circuit is changed to the internal processing circuit, it can be easily dealt with.

[Brief description of the drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a principle configuration diagram of the present invention.

FIG. 3 is an embodiment of the present invention.

FIG. 4 is an example of the present invention.

FIG. 5 is an example of the present invention.

FIG. 6 is a device configuration diagram of an electronic device.

FIG. 7 is an explanatory diagram of a conventional technique.

FIG. 8 is an explanatory diagram of a conventional technique.

FIG. 9 is an example of a bus connection of a processing circuit.

[Explanation of symbols]

 1a Main data bus 1b Main address bus 2a Sub data bus 2b Sub address bus 3 Bus connection circuit 4 Bus connection control circuit 5 MPU 7 Memory 8a Internal processing circuit 8b External processing circuit 20 Master detection means 21 Access destination detection means 22 Management means 23th 2 management means 24 1st display means 25 2nd display means 26 3rd display means 27 generation means 30 management means 31 display means 32 generation means

Claims (3)

[Claims] 1. Used in an electronic device having a main data bus connecting a MPU and directly or indirectly connecting a memory, and between the main data bus and the sub data bus. In the bus connection control circuit that issues a data direction control signal to the bus connection circuit provided in, manages whether each processing circuit that constitutes the electronic device is connected to the main data bus or the sub data bus. A processing circuit connected to the sub data bus receives the management means (22), the management data of the management means (22), and information indicating whether or not the processing circuit is the access source of the memory, and Is it the first display means (24) that outputs a display signal to that effect when it is the access source, the management data of the management means (22), and the processing circuit of the MPU access destination? Or as input and information indicating,
When the processing circuit connected to the sub data bus is the access destination, the second display means (2) for outputting a display signal to that effect (2
5), a read / write signal to be issued, and a generation means (27) for generating the data direction control signal by using the display signals of the first and second display means (24, 25). A bus connection control circuit characterized by the above. 2. The bus connection control circuit according to claim 1, further comprising: second management means (23) for managing whether or not each processing circuit is of a multiplex type for transferring an address to a data bus.
And the management data of the second management means (23) and each processing circuit generated when the first display means (24) outputs the display signal are the access source processing circuits connected to the sub data bus. Third display means (26) that outputs a display signal indicating that the processing circuit connected to the sub data bus and of the above-mentioned multiplex type becomes the access source, by inputting information indicating whether or not The generating means (27) generates the data direction control signal in consideration of the address transfer signal issued by the processing circuit and the display signal of the third display means (26). And bus connection control circuit. 3. A main address bus for connecting an MPU and connecting a memory directly or indirectly,
A bus connection control circuit that is used in an electronic device including a sub address bus and that issues a data direction control signal to a bus connection circuit provided between the main address bus and the sub address bus configures the electronic device. A management means (30) for managing whether each processing circuit is connected to the main address bus or the sub address bus, management data of the management means (30), and a processing circuit of an access source to the memory. And information indicating whether or not the display circuit outputs a display signal to that effect when the processing circuit connected to the sub-address bus is the access source.
(31), an address transfer signal issued by the processing circuit, and the display means
A bus connection control circuit comprising: a generation means (32) for generating the data direction control signal using the display signal of (31).