JP2003281564A - Image generating device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem in a conventional image generating device using Z buffer method that the speeding up of both calculating processing and buffer read/write is insufficient to attain an increase in speed of calculating processing and buffer read/write. <P>SOLUTION: A buffer 16 divides a screen formed of a plurality of pixels arranged in a lattice shape into a plurality of buffer blocks, and stores depth values and luminance values thereof in buffer blocks unit with buffer block numbers assigned thereto, respectively. A cache part 13 receives the read address or write address of a buffer corresponding to a pixel position, calculates the buffer block number corresponding to the input address, and reads and outputs, when the calculate buffer block number is stored in a cache memory 14, the depth value corresponding to the pixel position from the cache memory 14 to a drawing circuit 12, or writes the depth value and luminance value from the drawing circuit 12 to the cache memory 14. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image generating apparatus, and more particularly to an image generating apparatus for generating an image in which a hidden surface of a three-dimensional object is removed by computer graphics.

[0002]

2. Description of the Related Art As a conventional image generating apparatus for generating a hidden surface-erased image of a three-dimensional object by computer graphics, an apparatus for generating a hidden surface-erased image by a Z-buffer method is well known. The Z buffer method uses a Z buffer that stores a depth value (Z value) that is a distance from a viewpoint to an object for each pixel, and a frame buffer that stores a brightness value that represents brightness for each pixel. , The depth value and the brightness value of the three-dimensional object are calculated for each pixel, and Z
By comparing the depth value in the buffer with the depth value of the three-dimensional object and leaving the depth value and the luminance value closer to the viewpoint in the Z buffer and the frame buffer, when the viewpoint is finally viewed from a certain viewpoint. This is a method of generating an image in which a hidden surface is erased in a frame buffer so that an invisible object or a part of the object is not displayed.

[0003]

However, in the conventional image generating apparatus using the above Z-buffer method, calculation processing and buffering are performed for each pixel included in a projected image when a three-dimensional object is projected on the screen. Read / write is performed, but if static random access memory (SRAM) is used for the Z buffer and frame buffer, calculation processing and buffer read / write can be speeded up, but dynamic random access Access memory (DR
The cost is higher than that of AM).

On the other hand, in the conventional DRAM, the speeding up of both the calculation process and the buffer read / write is insufficient, and in recent years, there has been an increasing demand for higher image quality in the display of three-dimensional computer graphics. Due to the dramatic increase in the number of polygons, speeding up of calculation processing and buffer read / write is strongly desired.

The present invention has been made in view of the above points,
The screen is divided into a plurality of blocks, data is transferred between the buffer memory (hereinafter simply referred to as a buffer) and the cache memory in block units, and the drawing circuit performs read / write operations on the cache memory. It is an object of the present invention to provide an image generation apparatus capable of generating an image in which a hidden surface is erased from a three-dimensional object at high speed by speeding up read / write, parallelizing drawing circuits, and pipelining.

[0006]

In order to achieve the above object, the image generating apparatus of the first invention divides a screen composed of a plurality of pixels arranged in a grid into a plurality of buffer blocks, each of which is divided into a plurality of buffer blocks. A buffer that stores a depth value and a brightness value that represent a distance from the viewpoint in units of buffer blocks with buffer block numbers is defined, and a three-dimensional object is defined as a set of polygons that are basic shapes. It receives as input the polygon data in which the depth value and the brightness value representing the position on the screen and the distance from the viewpoint for each vertex are described, and by interpolating the depth value and the brightness value, the pixel position of the pixel in the polygon, The depth value and the brightness value are calculated, and the interpolation is performed only when the depth value calculated by interpolation is smaller than the depth value corresponding to the pixel position input from the buffer. Therefore, a drawing circuit that outputs the depth value and the brightness value that are obtained, and a cache memory that stores the depth value and the brightness value of a plurality of buffer blocks in units of this buffer block and that is composed of a plurality of cache blocks with cache block numbers A cache control unit, a buffer control unit, and a calculation unit.

Here, the cache control unit receives the read address or write address of the depth value and the brightness value corresponding to the pixel position of the buffer from the drawing circuit, and responds to the input read address or write address. The buffer block number is calculated, and whether the buffer block with the calculated buffer block number is stored in the cache memory is detected by comparing the calculated buffer block number with the buffer block number stored for each cache block. , When it is stored in the cache memory, the depth value corresponding to the pixel position is read from the cache memory and output to the drawing circuit, or the depth value and the brightness value input from the drawing circuit are written to the cache memory and cached. When not stored in memory Select one cache block, transfer the depth value and the brightness value stored in the selected cache block from the cache memory to the buffer, and then store the buffer block with the calculated buffer block number in the selected cache block. Output a control signal.

Further, the buffer control unit transfers the depth value and the brightness value stored in the selected cache block from the cache memory to the buffer based on the control signal from the cache control unit, and thereafter, the read address or the write value. The depth value and the brightness value of the buffer block having the buffer block number corresponding to the address are transferred from the buffer to the selected cache block and stored therein. Further, the arithmetic means controls the operation of the drawing circuit so that the drawing circuit outputs at least the read address and the write address independently of each other, and controls the buffer control unit before starting the drawing of the polygon on the screen. Then, the buffer is initialized, and when the drawing of all polygons in the screen is completed, the brightness value from the buffer is read and output to the buffer control unit.

According to the first aspect of the present invention, the screen is divided into a plurality of buffer blocks, and the depth value and the luminance value are transferred between the buffer and the cache memory in units of the buffer blocks, so that the drawing circuit uses the buffer read address. The buffer write address can be output independently.

Further, in order to achieve the above object, in the image generating apparatus of the second invention, the cache control unit is reset when the depth value and the brightness value of the buffer block are transferred from the buffer to the cache memory, and the drawing circuit. From the cache block to the cache block of the cache memory, a write flag that is set at the time of writing the depth value and the brightness value is provided for each cache block. It is characterized in that the brightness value is transferred to the buffer.

In the second invention, the buffer control section is
Only when the write flag is set, the depth value and the brightness value are transferred from the cache block to the buffer. Therefore, when the cache block is updated, the write flag assigned to the cache block to be updated is not set. At times, it is possible to eliminate the need to transfer the depth value and the brightness value of the cache block to the buffer.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of a first embodiment of an image generating apparatus according to the present invention. The image generating apparatus according to this embodiment defines an object arranged in a three-dimensional space as a set of polygons having a basic shape, and corresponds to each pixel position on the screen composed of pixels arranged in a grid pattern. An image generation apparatus that generates an image with hidden surface removed based on the depth value using a buffer that stores a depth value (Z value) that represents the distance from a viewpoint to an object and a brightness value. Central processing unit (CPU) 11
A drawing circuit 12 to which polygon data is input, a cache control unit 13 connected to the drawing circuit 12, a cache memory 14 whose operation is controlled by the cache control unit 13, a buffer control unit 22, and a buffer control unit. 15
And a buffer 16 for storing the above-mentioned depth value (Z value) and brightness value.

The cache memory 14 is composed of, for example, a static random access memory (SRAM). On the other hand, since the buffer 16 is required to have a large capacity, it is easy to secure a large capacity in the synchronous DRA.
It is composed of M (SDRAM). SDRAM
Compared to reading / writing a small amount of data,
There is a characteristic that the data transfer capability is improved by reading / writing a large amount of collected data.

Next, the operation of this embodiment will be described. In this embodiment, a Z-buffer method is used to generate an image in which a hidden surface of a three-dimensional object is removed. In the Z-buffer method,
Since it is necessary to initialize the buffer 16 before drawing the screen,
First, the CPU 11 supplies a buffer initialization request together with the buffer start address, the screen vertical line number, and the screen horizontal pixel number to the buffer control unit 15, and the buffer control unit 15 initializes the buffer 16.

Subsequently, the CPU 11 outputs a drawing command to the drawing circuit 12. When receiving the drawing command as an input, the drawing circuit 12 takes in polygon data input from the outside. This polygon data is shape data of three-dimensional coordinates treated as a planar polygon (for example, a triangle) called a polygon. For each vertex of the polygon, a depth value (Z value) representing the position on the screen and the distance from the viewpoint and The brightness value is described. The drawing circuit 12 interpolates the depth value and the brightness value of the polygon data to obtain the pixel position, the depth value and the brightness value of the pixel in the polygon, and together with them, the buffer for each pixel from each pixel position in the polygon. The read address is calculated and supplied to the cache control unit 13.

The buffer 16 is a memory for storing a depth value and a brightness value representing a distance from the viewpoint, which corresponds to each pixel position on the screen composed of pixels arranged in a grid pattern, and is stored in the buffer 16. The depth value and the luminance value of the displayed screen are divided into blocks each having m vertical lines and n horizontal pixels, and each block (hereinafter, also referred to as a buffer block)
Is assigned a buffer block number.

On the other hand, the cache memory 14 is a memory for storing a plurality of the above buffer blocks, and a cache block number is given to each cache block for storing each buffer block. The cache control unit 13
The buffer block number stored in each cache block is stored.

Here, the buffer block number of the buffer block stored in the buffer 16, the buffer block number stored in the cache memory 14, the cache block number stored in the cache control unit 13, and the buffer The correspondence between block numbers will be described in detail with reference to FIG. As an example, when the depth value and the brightness value of a screen having 16 lines (pixels) vertically and 16 pixels (pixels) horizontally are divided into blocks each having 4 lines (pixels) vertically and 4 pixels (pixels) horizontally, FIG. (A)
Each of these buffer blocks as shown in
6 is stored, and a buffer block number is added to each buffer block.

On the other hand, assuming that the cache memory 14 has a capacity for storing four buffer blocks as an example, the capacity of the cache memory 14 is divided into four cache blocks as shown in FIG. 2B. The cache block numbers 0 to 3 are assigned to the respective cache blocks.

When the drawing circuit 12 wants to read the buffer block with the buffer block number 9 from the cache memory 14, the cache control unit 13 assigns the buffer block number 9 to any of the cache block numbers 0 to 3 in the cache memory 14. It is necessary to check whether or not the data of the buffer block is stored. For that purpose, the cache block number 0 of the cache memory 14 is
It is necessary for the cache control unit 13 to store which buffer block is currently stored in each of 3 to 3.

In the example of FIG. 2, as shown in FIGS. 2B and 2C, the buffer block number 0 is assigned to the cache block of cache block number 0 of the cache memory 14.
Buffer block, the cache block of cache block number 1 is the buffer block of buffer block number 9, the cache block of cache block number 2 is the buffer block of buffer block number 5, and the cache block of cache block number 3 is The buffer block with the buffer block number 4 is stored therein, and the correspondence relation is stored in the cache control unit 13.

Referring back to FIG. 1 again, when the buffer read address is input from the drawing circuit 12, the cache control unit 13 calculates the buffer block number (buffer read block number) to be read from the cache read address, and the cache memory It is compared with the buffer block number held by each cache block in 14.

If the comparisons match, the cache control unit 1
3 outputs the read address corresponding to the pixel position to the cache memory 14, reads the depth value corresponding to the pixel position from the cache memory 14, and outputs the depth value to the drawing circuit 12.

If the above comparisons do not match, the cache control unit 13 inactivates the cache hit signal to the CPU 11 to suppress the output of a new drawing command from the CPU 11 and select the cache block to be updated. , A buffer write start address is calculated from the buffer block number corresponding to the cache block to be updated, a cache start address is calculated from the cache block number of the cache memory 14 to be updated, and is output to the buffer control unit 15 together with the cache update request. .

When a cache update request is input from the cache control unit 13, the buffer control unit 15 obtains a depth value and a brightness value for one buffer block from the cache start address also input from the cache control unit 13 in the cache memory 14. From the cache control unit 13 and stores it in the location of the buffer 16 indicated by the buffer write start address which is also input from the cache control unit 13.

Thereafter, the buffer control unit 15 reads one buffer block from the storage location of the buffer 16 indicated by the buffer read start address input from the cache control unit 13, and caches the one buffer block. Store in the location indicated by 14 cache start addresses. After that, the buffer control unit 1
5 outputs a cache update acknowledge to the cache control unit 13.

Since the buffer 16 is composed of the SDRAM, the buffer control section 15 causes the buffer 16 to perform chip select (CS), row address strobe (RAS),
The column address strobe (CAS), write enable (WE), and address are output, and the depth value and the brightness value are written / read.

The operation when the above comparisons do not match will be described more specifically with reference to FIG. As an example, the buffer 16 shown in FIG. 3 (a) (same as FIG. 2 (a)) 1
It is assumed that 6 buffer blocks are stored, and
The depth values and the brightness values of the buffer blocks with the buffer block numbers shown in FIG. 2C are stored in the cache blocks with cache block numbers 0 to 3 that indicate the four storage areas of the cache memory 14 shown in FIG. 3B. It has been done. In this state, when the buffer read address output from the drawing circuit 12 to the cache control unit 13 corresponds to the buffer block number 10, the cache control unit 13 stores the buffer block with the buffer block number 10 in the four cache blocks. As a result of the above comparison, the comparison does not match.

Therefore, when the cache memory 14 is in the state of FIG. 3B, the cache control unit 13 stores the buffer block in the full capacity, and the buffer block with the buffer block number 10 is stored in the cache memory 14 as it is. Since it cannot be written, one cache block to be updated is selected from the four cache blocks (here, as an example, cache block number 0
The depth value and the brightness value of the buffer block with the buffer block number 0 stored in the selected cache block are read and written to the buffer 16, and then the depth value and the brightness value of the buffer block with the buffer block number 10 are read. The value is stored in the cache block with the cache block number 0 selected as the cache block to be read from the buffer 16 and updated.

As a result, as shown in FIG. 3C, the cache memory 14 assigns the buffer block number 1 to the cache block having the cache block number 0 to be updated.
The depth value and the brightness value of the buffer block of 0 are stored. After the storage ends, the buffer control unit 15 outputs a cache update acknowledge to the cache control unit 13. The cache block to be updated may be selected at random, but in order to increase the probability that the comparisons match (cache hit rate), the LRU
Algorithm (Drawing circuit 1 among all cache blocks
It is preferable to use an algorithm that selects a cache block that has been most accessed since 2).

Returning to FIG. 1, the description will be continued. When the cache update acknowledge is input, the cache control unit 13 activates the cache hit signal and
The buffer read block number is compared again with the buffer block number held by each cache block, and the read address corresponding to the pixel position is set in the cache memory 1.
4, the depth value is read from the cache memory 14 and output to the drawing circuit 12.

When the depth value is input from the cache memory 14, the drawing circuit 12 compares it with the depth value obtained by interpolation from the depth value at the apex described in the polygon data, and obtains the depth obtained by interpolation. If the value is smaller than the input depth value, the pixel obtained by the interpolation is closer to the viewpoint, so the depth value and the luminance value obtained by the interpolation are stored in the cache memory 1
In order to write to 4, the buffer write address, write enable, depth value, and brightness value are output to the cache control unit 13. If the depth value obtained by interpolation is larger than the input depth value, the depth value and luminance value obtained by interpolation are not written to the cache memory 14.

When the buffer write address is input from the drawing circuit 12, the cache control unit 13 calculates the buffer write block number from the buffer write address and compares it with the buffer block number held by each cache block.
If the comparisons match, the cache control unit 13 outputs the write address, write enable, depth value, and brightness value of the cache block for which the comparisons match to the cache memory 14, and writes the depth value and the brightness value to the cache memory 14.

If the above comparisons do not match, the cache control unit 13 inactivates the cache hit signal to the CPU 11 to suppress the output of a new drawing command from the CPU 11 and select the cache block to be updated. The buffer write start address is calculated from the buffer block number of the buffer block held by the cache memory 14 to be updated, the cache start address is calculated from the cache block number of the cache memory 14 to be updated, and the buffer is written from the buffer write block number. Calculate the read start address,
Output to the buffer control unit 15 together with the cache update request.

When a cache update request is input from the cache control unit 13, the buffer control unit 15 obtains a depth value and a brightness value for one buffer block from the cache start address also input from the cache control unit 13 in the cache memory 14. From the cache control unit 13 and stores it in the location of the buffer 16 indicated by the buffer write start address which is also input from the cache control unit 13.

Thereafter, the buffer control unit 15 reads one buffer block from the storage location of the buffer 16 indicated by the buffer read start address input from the cache control unit 13, and caches the one buffer block. Store in the location indicated by 14 cache start addresses. After that, the buffer control unit 1
5 outputs a cache update acknowledge to the cache control unit 13.

Since the buffer 16 is composed of the SDRAM, the buffer control unit 15 causes the buffer 16 to perform chip select (CS), row address strobe (RAS),
The column address strobe (CAS), write enable (WE), and address are output, and the depth value and the brightness value are written / read.

When the cache update acknowledge is input, the cache control unit 13 activates the cache hit signal and re-compares the buffer write block number with the buffer block number held by each cache block. The write address, the write enable, the brightness value, and the depth value of the cache block in which the comparison is matched are output to the cache memory 14, and the brightness value and the depth value are written to the cache memory 14.

When all the polygons on the screen have been drawn, the CPU 11 outputs the image output request, the buffer start address, the number of vertical screen lines, and the number of horizontal screen pixels to the buffer control unit 15. When the image output request is input, the buffer control unit 15 reads and outputs the brightness value from the location of the buffer 16 in the area indicated by the input information of the buffer start address, the screen vertical line number, and the screen horizontal pixel number.

Since the drawing circuit 12 can output the buffer read address and the buffer write address independently,
The buffer read of the next pixel can be performed before the buffer write of the previous pixel is completed, and the drawing circuit 12 can be pipelined. Further, the drawing circuit 12 is capable of parallel processing of pixels in the block. As a result, the read / write speed of the buffer 16 can be increased, and an image can be generated at high speed by the parallel processing and pipeline processing of the drawing circuit 12.

Next, a second embodiment of the present invention will be described. FIG. 4 shows a block diagram of a second embodiment of the image generating apparatus according to the present invention. In the figure, the same components as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted as appropriate. In FIG. 4, the cache control unit 21 controls, for each cache block of the cache memory 14, a write flag that is reset at the time of transfer from the buffer 16 to the cache memory 14 and is set at the time of writing from the drawing circuit 12 to the cache memory 14. The buffer control unit 22 is added with a function of outputting to the cache memory 1
When the depth value and the brightness value of the buffer block from 4 are transferred to the buffer 16, the depth value and the brightness value of the buffer block are transferred to the buffer 16 only when the write flag is set.

Next, the operation of this embodiment will be described. First, the CPU 11 supplies a buffer initialization request to the buffer control unit 22 together with the buffer start address, the screen vertical line number, and the screen horizontal pixel number, and the buffer control unit 22 initializes the buffer 16.

Subsequently, the CPU 11 outputs a drawing command to the drawing circuit 12. When receiving the drawing command as an input, the drawing circuit 12 takes in polygon data input from the outside. In the polygon data, as described above, the depth value (Z value) and the brightness value representing the position on the screen and the distance from the viewpoint are described for each vertex of the polygon, and the drawing circuit 12 stores these values. By inserting, the pixel position of the pixel in the polygon, the depth value, and the brightness value are obtained, and together with these, the buffer read address for each pixel is calculated from each pixel position in the polygon, and is supplied to the cache control unit 21.

The cache control unit 21 stores the buffer block number of the buffer block stored in the cache block of the cache memory 14, and sets a write flag for storing that each cache block has been written by the drawing circuit 12. To have. Further, when the buffer read address is input from the drawing circuit 12, the cache control unit 21 calculates the buffer block number (buffer read block number) to be read from it, and each cache block in the cache memory 14 holds the buffer block number. Compare with buffer block number.

If the comparisons match, the cache control unit 2
1 outputs the read address of the cache block number indicating the matched cache block to the cache memory 14, reads the depth value of the matched cache block (buffer block of the read buffer block number) from the cache memory 14, and draws the drawing circuit. Output to 12.

If the above comparisons do not match, the cache control unit 21 inactivates the cache hit signal to the CPU 11 to suppress the output of a new drawing command from the CPU 11 and select the cache block to be updated. , The buffer write start address is calculated from the buffer block number of the cache block held by the cache memory 14 to be updated, the cache start address is calculated from the cache block number of the cache memory 14 to be updated, and the buffer is updated together with the cache update request. Output to the control unit 22.

When the cache update request is input from the cache control unit 21, the buffer control unit 22 determines whether the write flag also input from the cache control unit 21 is active. When the write flag is active, the buffer control unit 22 inputs the cache update request. The depth value and the brightness value for one buffer block are read from the cache block of the cache memory 14 from the cache start address thus stored, and stored in the location of the buffer 16 indicated by the buffer write start address which is also input from the cache control unit 21. To do. The buffer control unit 22 does not perform the above buffer write when the write flag is inactive.

After that, the buffer control unit 22 reads the depth value for one buffer block from the storage location of the buffer 16 indicated by the buffer read start address input from the cache control unit 21, and for that one buffer block. And stores the depth value in the cache memory 14 at the location indicated by the cache start address. After that, the buffer control unit 22 outputs a cache update acknowledge to the cache control unit 21.

As described above, the buffer 16 is SDRA.
Since it is composed of M, the buffer control unit 22 causes the buffer 16 to include a chip select (CS), a row address strobe (RAS), and a column address strobe (CA).
S), write enable (WE), output address,
Write / read depth value and brightness value.

When the cache update acknowledge is input, the cache control unit 21 activates the cache hit signal and inactivates the write flag of the updated cache block to hold the buffer read block number and each cache block. Then, the read address of the cache block in which the comparison is matched is output to the cache memory 14, the depth value is read from the cache memory 14 and output to the drawing circuit 12.

When the depth value is input from the cache memory 14, the drawing circuit 12 compares it with the depth value obtained by interpolation, and if the depth value obtained by interpolation is smaller than the input depth value. , The cache write address, the write enable, the depth value, and the brightness value are output to the cache control unit 21 in order to write the depth value and the brightness value obtained by the interpolation into the cache memory 14.

When the buffer write address is input from the drawing circuit 12, the cache controller 21 calculates the buffer write block number from the buffer write address and compares it with the buffer block number held by each cache block of the cache memory 14. If the comparison is matched, the cache control unit 21 outputs the write address, write enable, depth value, and brightness value of the cache block for which the comparison is matched to the cache memory 14, and the cache memory 14
Further, the drawing circuit 12 writes the depth value and the brightness value obtained by the interpolation, and activates the write flag of the cache block in which the comparison matches.

If the above comparisons do not match, the cache control unit 21 inactivates the cache hit signal to the CPU 11 to suppress the output of a new drawing command from the CPU 11 and to update the cache memory 1.
4 cache block is selected, the buffer write start address is calculated from the buffer block number of the selected cache block, the cache start address is calculated from the cache block number of the cache block to be updated, and the buffer read from the buffer write block number. The start address is calculated and output to the buffer control unit 22 together with the write flag of the cache block to be updated and the cache update request.

When a cache update request is input from the cache control unit 21, the buffer control unit 22 sends 1 from the cache start address from the cache control unit 21 if the write flag input from the cache control unit 21 is active. The depth value and the brightness value for the buffer block are read from the cache memory 14 and stored in the location of the buffer 16 indicated by the buffer write start address also input from the cache control unit 21. If the write flag is inactive, buffer write is not performed.

Thereafter, the buffer control unit 22 reads one buffer block from the storage location of the buffer 16 indicated by the buffer read start address input from the cache control unit 21, and caches the one buffer block. Store in the location indicated by 14 cache start addresses. After that, the buffer control unit 2
2 outputs a cache update acknowledge to the cache control unit 21.

Since the buffer 16 is composed of the SDRAM, the buffer control unit 22 causes the buffer 16 to perform chip select (CS), row address strobe (RAS),
The column address strobe (CAS), write enable (WE), and address are output, and the depth value and the brightness value are written / read.

When the cache update acknowledge is input, the cache control unit 21 activates the cache hit signal and inactivates the write flag of the updated cache block to hold the buffer write block number and each cache block. The buffer block number is being compared again, and the write address, write enable, brightness value, and depth value of the cache block for which the comparison matches are output to the cache memory 14, and the brightness value and depth value are written to the cache memory 14. At the same time, the write flag of the cache block in which the comparison matches is activated.

When the drawing of all the polygons on the screen is completed, the CPU 11 outputs the image output request, the buffer start address, the screen vertical line number, and the screen horizontal pixel number to the buffer control unit 22. When the image output request is input, the buffer control unit 22 reads and outputs the brightness value from the location of the buffer 16 in the area indicated by the input information of the buffer start address, the screen vertical line number, and the screen horizontal pixel number.

Next, the effect of this embodiment will be described. The cache control unit 21 of this embodiment has a write flag that stores whether the data (depth value and brightness value) of the buffer block stored in the cache memory 14 is overwritten by the drawing circuit 12.
For example, immediately after the buffer block with the buffer block number 0 is stored in the cache block with the cache block number 0 in FIG. 3B, the write flag of the cache block number 0 is 0 (inactive).

After that, when the drawing circuit 12 writes (overwrites) the depth value and the brightness value into the cache block of the cache block number 0, the write flag of the cache block number 0 becomes 1 (active). If the drawing circuit 12 does not write the depth value and the brightness value to the cache block with the cache block number 0, the write flag remains 0.

In order to store the buffer block with the buffer block number 10 in the cache block with the cache block number 0 in the cache memory 14, the buffer block with the buffer block number 0 originally stored in the cache block with the cache block number 0. Is stored in the buffer 16, if the write flag of the cache block number 0 is 1, it is necessary to write to the buffer 16, but if the write flag of the cache block number 0 is 0, the cache block number 0
Since the cache block of 2 is not overwritten by the drawing circuit 12, writing to the buffer 16 is unnecessary. As a result, according to the present embodiment, the time for suppressing the drawing command output can be reduced, the drawing speed can be increased, and the cache block update time can be shortened.

The present invention is not limited to the above-described embodiments, and for example, the buffer 16 may be a memory other than the SDRAM, which can easily secure a large capacity.

[0063]

As described above, according to the present invention,
By dividing the screen into multiple buffer blocks, transferring the depth value and the brightness value between the buffer and the cache memory in units of these buffer blocks, and the drawing circuit outputting the buffer read address and the buffer write address independently, The buffer read of the next pixel can be performed before the buffer write of the previous pixel is completed, which allows the buffer read / write to be performed at high speed and the drawing circuit to be pipelined, and the parallel processing of the drawing circuit. Since it is possible to realize the above, it is possible to generate an image in which the hidden surface is erased by the Z buffer method at high speed.

Further, according to the present invention, the buffer control unit transfers the depth value and the luminance value from the cache block to the buffer only when the write flag is set, so that the buffer block is assigned to the cache block to be updated. When the light flag is not set,
Since it is not necessary to transfer the depth value and the brightness value of the cache block to the buffer, the cache block update time can be shortened and the drawing speed can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a correspondence relationship between a cache block of a cache memory and a buffer block of a buffer.

FIG. 3 is a diagram illustrating updating of one cache block of a cache memory.

FIG. 4 is a block diagram of a second embodiment of the present invention.

[Explanation of symbols]

11 Central Processing Unit (CPU) 12 Drawing circuit 13, 21 Cache control unit 14 cache memory 15, 22 Buffer control unit 16 buffers (buffer memory)

Claims (2)

[Claims] 1. A screen composed of a plurality of pixels arranged in a grid pattern is divided into a plurality of buffer blocks, and a depth value and a luminance value representing a distance from a viewpoint are displayed in units of buffer blocks each having a buffer block number. A buffer that stores each of the plurality of pixels, and a three-dimensional object is defined as a set of polygons that are basic shapes, and a depth value and a brightness value that represent a position on the screen and a distance from a viewpoint are defined for each vertex of the polygon. The pixel position, the depth value and the brightness value of the pixel in the polygon are obtained by receiving the described polygon data as an input and interpolating the depth value and the brightness value, and the pixel position input from the buffer. The depth value and the brightness value obtained by the interpolation are output only when the depth value obtained by the interpolation is smaller than the depth value corresponding to A drawing circuit which, the depth value and the luminance values of the plurality of buffer blocks,
A cache memory that stores a plurality of cache block numbers, each of which is stored in the buffer block unit, and a read address or a write address of a depth value and a luminance value corresponding to the pixel position of the buffer from the drawing circuit. The buffer block number and the cache block that have been received and are calculated to calculate the buffer block number corresponding to the read address or the write address that has been input, and whether the buffer block having the calculated buffer block number is stored in the cache memory It is detected by comparing the buffer block numbers stored for each, and when stored in the cache memory, the depth value corresponding to the pixel position is read from the cache memory and output to the drawing circuit, or Or The depth value and the brightness value input from the drawing circuit are written to the cache memory, and when not stored in the cache memory, one cache block is selected and the depth value stored in the selected cache block is selected. And a cache control unit that outputs a control signal for storing a brightness value from the cache memory to the buffer and then stores the buffer block having the calculated buffer block number in the selected cache block, and a cache control unit from the cache control unit. Based on the control signal, after transferring the depth value and the brightness value stored in the selected cache block from the cache memory to the buffer, the buffer block number of the buffer block corresponding to the read address or the write address Depth A buffer control unit for transferring and storing a threshold value and a brightness value from the buffer to the selected cache block, and an operation of the drawing circuit so that the drawing circuit outputs at least the read address and the write address independently. The buffer control unit before the drawing of polygons on the screen is started, and when the drawing of all polygons in the screen is completed, the buffer control unit is controlled from the buffer. And an arithmetic means for reading and outputting the brightness value of the image generation apparatus. 2. The cache control unit is reset when the depth value and the brightness value of the buffer block are transferred from the buffer to the cache memory, and the depth value from the drawing circuit to the cache block of the cache memory and A write flag that is set when writing a brightness value is provided for each cache block, and the buffer control unit transfers the depth value and the brightness value from the cache block to the buffer only when the write flag is set. The image generation apparatus according to claim 1, wherein